ATMEL AT45DB041-TI, AT45DB041-TC, AT45DB041-RI, AT45DB041-RC, AT45DB041-JI Datasheet

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ATMEL AT45DB041-TI, AT45DB041-TC, AT45DB041-RI, AT45DB041-RC, AT45DB041-JI Datasheet

Features

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Single 2.7V - 3.6V Supply

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial Interface Architecture

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Page Program Operation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

– Single Cycle Reprogram (Erase and Program)

 

 

 

 

 

 

 

 

 

– 2048 Pages (264 Bytes/Page) Main Memory

 

 

 

 

 

 

 

 

 

 

Two 264-Byte SRAM Data Buffers – Allows Receiving of Data

 

 

 

 

 

 

 

While Reprogramming of Non-Volatile Memory

 

 

 

 

 

 

 

 

 

 

Internal Program and Control Timer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fast Page Program Time – 7 ms Typical

 

 

 

 

 

 

 

 

 

 

 

 

 

4-Megabit

120 μs Typical Page to Buffer Transfer Time

 

 

 

 

 

 

 

 

 

 

Low Power Dissipation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.7-volt Only

 

– 4 mA Active Read Current Typical

 

 

 

 

 

 

 

 

 

 

 

 

 

 

– 8 μA CMOS Standby Current Typical

 

 

 

 

 

 

 

 

 

 

 

 

5 MHz Max Clock Frequency

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial

Hardware Data Protection Feature

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3

 

 

 

 

 

DataFlash®

CMOS and TTL Compatible Inputs and Outputs

 

 

 

 

 

 

 

 

Commercial and Industrial Temperature Ranges

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AT45DB041

The AT45DB041 is a 2.7-volt only, serial interface Flash memory suitable for in-sys-

tem reprogramming. Its 4,325,376 bits of memory are organized as 2048 pages of

264-bytes each. In addition to the main memory, the AT45DB041 also contains two

SRAM data buffers of 264-bytes each. The buffers allow receiving of data while a

page in the main memory is being reprogrammed. Unlike conventional Flash memo-

ries that are accessed randomly with multiple address lines and a parallel interface,

the DataFlash uses a serial interface to sequentially access its data. The simple serial

interface facilitates hardware layout, increases system reliability, minimizes switching

Pin Configurations

 

 

 

 

 

 

 

 

 

 

 

 

 

(continued)

 

 

 

PLCC

 

 

 

 

SOIC

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name

Function

 

CS

NC

NC

GND

VCC

NC

NC

 

GND

 

1

 

28

VCC

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

2

 

27

NC

 

CS

Chip Select

 

 

 

 

 

 

 

 

 

 

 

 

 

4

3

2

1

32

31

30

 

NC

 

3

 

26

NC

 

 

 

SCK

WP

 

 

 

 

 

5

 

 

 

 

 

29

CS

 

4

 

25

WP

 

SCK

Serial Clock

SI

6

 

 

 

 

 

28

RESET

 

 

 

 

 

 

 

 

SCK

 

5

 

24

RESET

 

 

 

SO

7

 

 

 

 

 

27

RDY/BUSY

SI

 

6

 

23

RDY/BUSY

 

SI

Serial Input

NC

8

 

 

 

 

 

26

NC

 

 

 

 

 

 

 

 

SO

 

7

 

22

NC

 

NC

9

 

 

 

 

 

25

NC

 

 

 

 

 

 

 

 

 

 

NC

 

8

 

21

NC

 

 

 

NC

10

 

 

 

 

 

24

NC

 

 

 

SO

Serial Output

 

 

 

 

 

NC

 

9

 

20

NC

 

NC

11

 

 

 

 

 

23

NC

 

 

 

 

 

 

 

 

 

 

NC

 

10

 

19

NC

 

 

 

NC

12

 

 

 

 

 

22

NC

 

 

 

 

Hardware Page Write

 

 

 

 

 

NC

 

11

 

18

NC

 

 

NC

13

 

 

 

 

 

21

NC

 

 

 

WP

 

 

 

 

 

NC

 

12

 

17

NC

 

Protect Pin

 

14

15

16

17

18

19

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

13

 

16

NC

 

RESET

Chip Reset

 

NC

NC

DC

DC

NC

NC

NC

 

NC

 

14

 

15

NC

 

 

 

 

 

 

 

 

 

 

Note: PLCC package pins 16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RDY/BUSY

Ready/Busy

and 17 are DON’T CONNECT.

 

 

 

 

 

 

 

TSOP Top View

 

 

 

 

 

 

 

 

CBGA Top View

 

 

 

Type 1

 

 

 

 

 

 

 

 

 

Through Package

 

 

RDY/BUSY

1

 

 

28

 

NC

 

 

 

 

1

2

3

4

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

2

 

 

27

 

NC

 

 

 

 

 

 

 

 

 

 

 

WP

3

 

 

26

 

NC

 

 

 

 

 

 

 

 

 

 

 

NC

4

 

 

25

 

NC

 

 

 

 

 

 

 

 

 

 

 

NC

5

 

 

24

 

NC

 

 

 

A

 

 

 

 

 

 

 

VCC

6

 

 

23

 

NC

 

 

 

B

 

NC

NC

NC

NC

 

 

GND

7

 

 

22

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

SCK GND VCC

NC

 

 

NC

8

 

 

21

 

NC

 

 

 

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

9

 

 

20

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

CS RDY/BSY WP

NC

 

 

NC

10

 

 

19

 

NC

 

 

 

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CS

11

 

 

18

 

NC

 

 

 

E

NC

SO

SI

RESET NC

 

 

SCK

12

 

 

17

 

NC

 

 

 

NC

NC

NC

NC

NC

 

 

SI

13

 

 

16

 

NC

 

 

 

 

Rev. 0669D–07/98

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SO

14

 

 

15

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

noise, and reduces package size and active pin count. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power are essential. Typical applications for the DataFlash are digital voice storage, image storage, and data storage. The device operates at clock frequencies up to 5 MHz with a typical active read current consumption of 4 mA.

To allow for simple in-system reprogrammability, the AT45DB041 does not require high input voltages for pro-

gramming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB041 is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).

All programming cycles are self-timed, and no separate erase cycle is required before programming.

Block Diagram

WP

 

FLASH MEMORY ARRAY

 

PAGE (264 BYTES)

 

 

BUFFER 1 (264 BYTES)

BUFFER 2 (264 BYTES)

SCK

 

 

CS

 

I/O INTERFACE

RESET

 

 

 

VCC

 

 

GND

 

 

RDY/BUSY

SI

SO

Device Operation

The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Table 1 and Table 2. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (serial input) pin. All instructions, addresses, and data are transferred with the most significant bit (MSB) first.

Read

By specifying the appropriate opcode, data can be read from the main memory or from either one of the two data buffers.

MAIN MEMORY PAGE READ: A main memory read allows the user to read data directly from any one of the 2048 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read, the 8-bit opcode, 52H, is followed by 24 address bits and 32 don’t care bits. In the AT45DB041, the first four address bits are reserved for larger density devices (see Notes on page 8), the next 11 address bits

(PA10-PA0) specify the page address, and the next nine address bits (BA8-BA0) specify the starting byte address within the page. The 32 don’t care bits which follow the 24 address bits are sent to initialize the read operation. Following the 32 don’t care bits, additional pulses on SCK result in serial data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bits, and the reading of data. When the end of a page in main memory is reached during a main memory page read, the device will continue reading at the beginning of the same page. A low to high transition on the CS pin will terminate the read operation and tri-state the SO pin.

BUFFER READ: Data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. An opcode of 54H is used to read data from buffer 1, and an opcode of 56H is used to read data from buffer 2. To perform a buffer read, the eight bits of the opcode must be followed by 15 don’t care bits, nine address bits, and eight don't care bits. Since the buffer size is 264-bytes, nine address bits (BFA8-BFA0) are required to specify the first byte of data to be read from the buffer.

2

AT45DB041

 

 

 

The CS pin must remain low during the loading of the opcode, the address bits, the don’t care bits, and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low to high transition on the CS pin will terminate the read operation and tri-state the SO pin.

MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred from the main memory to either buffer 1 or buffer 2. An 8-bit opcode, 53H for buffer 1 and 55H for buffer 2, is followed by the four reserved bits, 11 address bits (PA10-PA0) which specify the page in main memory that is to be transferred, and nine don’t care bits. The CS pin must be low while toggling the SCK pin to load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the transfer of a page of data (tXFR), the status register can be read to determine whether the transfer has been completed or not.

MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can be compared to the data in buffer 1 or buffer 2. An 8-bit opcode, 60H for buffer 1 and 61H for buffer 2, is followed by 24 address bits consisting of the four reserved bits, 11 address bits (PA10-PA0) which specify the page in the main memory that is to be compared to the buffer, and nine don't care bits. The loading of the opcode and the address bits is the same as described previously. The CS pin must be low while toggling the SCK pin to load the opcode, the address bits, and the don't care bits from the SI pin. On the low to high transition of the CS pin, the 264 bytes in the selected main memory page will be compared with the 264 bytes in buffer 1 or buffer 2. During this time (tXFR), the status register will indicate that the part is busy. On completion of the compare operation, bit 6 of the status register is updated with the result of the compare.

Program

BUFFER WRITE: Data can be shifted in from the SI pin into either buffer 1 or buffer 2. To load data into either buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2, is followed by 15 don't care bits and nine address bits (BFA8-BFA0). The nine address bits specify the first byte in the buffer to be written. The data is entered following the address bits. If the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer until a low to high transition is detected on the CS pin.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written into either buffer 1 or buffer 2 can be programmed into the main memory. An 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, is followed by the four reserved bits, 11 address bits (PA10-PA0) that specify the page in the main memory to be written, and

AT45DB041

nine additional don't care bits. When a low to high transition occurs on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the erase and the programming of the page are internally self timed and should take place in a maximum time of tEP. During this time, the status register will indicate that the part is busy.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previously erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. An 8-bit opcode, 88H for buffer 1 or 89H for buffer 2, is followed by the four reserved bits, 11 address bits (PA10-PA0) that specify the page in the main memory to be written, and nine additional don’t care bits. When a low to high transition occurs on the CS pin, the part will program the data stored in the buffer into the specified page in the main memory. It is necessary that the page in main memory that is being programmed has been previously programmed to all 1s (erased state). The programming of the page is internally self timed and should take place in a maximum time of tP. During this time, the status register will indicate that the part is busy.

MAIN MEMORY PAGE PROGRAM: This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-In Erase operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and then programmed into a specified page in the main memory. An 8- bit opcode, 82H for buffer 1 or 85H for buffer 2, is followed by the four reserved bits and 20 address bits. The 11 most significant address bits (PA10-PA0) select the page in the main memory where data is to be written, and the next nine address bits (BFA8-BFA0) select the first byte in the buffer to be written. After all address bits are shifted in, the part will take data from the SI pin and store it in one of the data buffers. If the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. When there is a low to high transition on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the erase and the programming of the page are internally self timed and should take place in a maximum of time tEP. During this time, the status register will indicate that the part is busy.

AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion. This mode is a combination of two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-In Erase. A page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. An 8-bit opcode, 58H for buffer 1 or 59H for buffer 2, is followed by the four reserved bits, 11 address

3

bits (PA10-PA0) that specify the page in main memory to be rewritten, and nine additional don't care bits. When a low to high transition occurs on the CS pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. The operation is internally self-timed and should take place in a maximum time of tEP. During this time, the status register will indicate that the part is busy.

If the main memory is programmed or reprogrammed sequentially page by page, then the programming algorithm shown in Figure 1 is recommended. Otherwise, if multiple bytes in a page or several pages are programmed randomly in the main memory, then the programming algorithm shown in Figure 2 is recommended.

STATUS REGISTER: The status register can be used to determine the device’s ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the device density. To read the status register, an opcode of 57H must be loaded into the device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The five most-signifi- cant bits of the status register will contain device information, while the remaining three least-significant bits are reserved for future use and will have undefined values. After bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting again with bit 7. The data in the status register is constantly updated, so each repeating sequence will output new data.

Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy state. The user can continuously poll bit 7 of the status register by stopping SCK once bit 7 has been output. The status of bit 7 will continue to be output on the SO pin, and once the device is no longer busy, the state of SO will change from 0 to 1. There are six operations which can cause the device to be in a busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program with Built-In Erase, Buffer to Main Memory Page Program without Built-In Erase, Main Memory Page Program, and Auto Page Rewrite.

The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the data in the buffer. If bit 6 is a 1, then at

least one bit of the data in the main memory page does not match the data in the buffer.

The device density is indicated using bits 5, 4, and 3 of the status register. For the AT45DB041, the three bits are 0, 1, and 1. The decimal value of these three binary bits does not equate to the device density; the three bits represent a combinational code relating to differing densities of Serial DataFlash devices, allowing a total of eight different density configurations.

Read/Program Mode Summary

The modes listed above can be separated into two groups

— modes which make use of the flash memory array (Group A) and modes which do not make use of the flash memory array (Group B).

Group A modes consist of:

1.Main memory page read

2.Main memory page to buffer 1 (or 2) transfer

3.Main memory page to buffer 1 (or 2) compare

4.Buffer 1 (or 2) to main memory page program with built-in erase

5.Buffer 1 (or 2) to main memory page program without built-in erase

6.Main memory page program

7.Auto page rewrite

Group B modes consist of:

1.Buffer 1 (or 2) read

2.Buffer 1 (or 2) write

3.Status read

If a Group A mode is in progress (not fully completed) then another mode in Group A should not be started. However, during this time in which a Group A mode is in progress, modes in Group B can be started.

This gives the Serial DataFlash the ability to virtually accommodate a continuous data stream. While data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details.

HARDWARE PAGE WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memory cannot be reprogrammed. The only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned.

Status Register Format

Bit 7

 

Bit 6

Bit 5

Bit

4

Bit

3

Bit 2

Bit 1

Bit 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COMP

0

1

 

1

 

X

X

X

RDY/BUSY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

AT45DB041

 

 

 

AT45DB041

RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level.

The device also incorporates an internal power-on reset circuit; therefore, there are no restrictions on the RESET pin during power-on sequences.

READY/BUSY: This open drain output pin will be driven low when the device is busy in an internally self-timed operation. This pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during program-

Absolute Maximum Ratings*

Temperature Under Bias

................................ -55°C to +125°C

Storage Temperature .....................................

-65°C to +150°C

All Input Voltages

 

(including NC Pins)

 

with Respect to Ground ...................................

-0.6V to +6.25V

All Output Voltages

 

with Respect to Ground .............................

- 0.6V to VCC + 0.6V

 

 

ming operations, compare operations, and during page-to- buffer transfers.

The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed.

Power On/Reset State

When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI mode 3. In addition, the SO pin will be in a high impedance state, and a high to low transition on the CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge of CS by sampling the inactive clock state.

*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC and AC Operating Range

 

 

AT45DB041

 

 

 

Operating Temperature (Case)

Com.

0°C to 70°C

 

 

Ind.

-40°C to 85°C

 

 

 

 

VCC Power Supply(1)

2.7V to 3.6V

Note: 1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an operational mode is started.

5

DC Characteristics

Symbol

Parameter

 

Condition

Min

Typ

Max

Units

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

= VIH, all inputs at

 

 

 

 

ISB

Standby Current

 

CS,

RESET,

WP

 

8

20

μA

 

CMOS levels

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICC1

Active Current, Read

 

f = 5 MHz; IOUT = 0 mA; VCC = 3.6V

 

4

10

mA

Operation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICC2

Active Current,

 

VCC = 3.6V

 

15

35

mA

Program/Erase Operation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ILI

Input Load Current

VIN = CMOS levels

 

 

1

μA

ILO

Output Leakage Current

VI/O = CMOS levels

 

 

1

μA

VIL

Input Low Voltage

 

 

 

 

 

 

 

 

 

0.6

V

VIH

Input High Voltage

 

 

 

 

 

 

 

2.0

 

 

V

VOL

Output Low Voltage

 

IOL = 1.6 mA; VCC = 2.7V

 

 

0.4

V

VOH

Output High Voltage

 

IOH = -100 μA

VCC - 0.2V

 

 

V

AC Characteristics

Symbol

Parameter

 

 

 

 

 

 

 

 

 

 

 

Min

Typ

Max

 

Units

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fSCK

 

SCK Frequency

 

 

 

 

 

5

 

MHz

tWH

 

SCK High Time

 

 

 

80

 

 

 

ns

tWL

 

SCK Low Time

 

 

 

80

 

 

 

ns

tCS

 

Minimum

 

High Time

 

 

 

350

 

 

 

ns

CS

 

 

 

 

tCSS

 

 

Setup Time

 

 

 

350

 

 

 

ns

 

CS

 

 

 

 

tCSH

 

 

Hold Time

 

 

 

350

 

 

 

ns

 

CS

 

 

 

 

tCSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CS

High to RDY/BUSY

Low

 

 

 

 

 

200

 

ns

tSU

 

Data In Setup Time

 

 

 

15

 

 

 

ns

tH

 

Data In Hold Time

 

 

 

35

 

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHO

 

Output Hold Time

 

 

 

0

 

 

 

ns

tDIS

 

Output Disable Time

 

 

 

 

 

100

 

ns

tV

 

Output Valid

 

 

 

 

 

 

 

 

 

 

 

 

 

120

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tXFR

 

Page to Buffer Transfer/Compare Time

 

120

250

 

μs

tEP

 

Page Erase and Programming Time

 

10

20

 

ms

tP

 

Page Programming Time

 

 

 

 

7

14

 

ms

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRST

 

 

 

Pulse Width

 

 

 

10

 

 

 

μs

 

RESET

 

 

 

 

tREC

 

 

 

Recovery Time

 

 

 

 

 

1

 

μs

 

RESET

 

 

 

 

 

Input Test Waveforms and Measurement Levels

Output Test Load

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AC

 

2.4V

 

2.0

AC

 

DEVICE

 

 

 

 

 

DRIVING

 

 

 

 

 

 

 

 

 

 

MEASUREMENT

 

UNDER

 

 

 

 

 

 

 

 

 

 

 

 

 

0.8

 

TEST

 

 

 

 

 

LEVELS

 

 

 

 

 

 

 

 

LEVEL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.45V

 

 

 

 

 

 

 

 

30 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tR, tF < 20 ns (10% to 90%)

6

AT45DB041

 

 

 

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