ATMEL AT29C512-90TI, AT29C512-90TC, AT29C512-90PI, AT29C512-90PC, AT29C512-90JI Datasheet

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ATMEL AT29C512-90TI, AT29C512-90TC, AT29C512-90PI, AT29C512-90PC, AT29C512-90JI Datasheet

AT29C512

Features

Fast Read Access Time - 70 ns

5-Volt-Only Reprogramming

Sector Program Operation

Single Cycle Reprogram (Erase and Program) 512 Sectors (128 bytes/sector)

Internal Address and Data Latches for 128-Bytes

Internal Program Control and Timer

Hardware and Software Data Protection

Fast Sector Program Cycle Time - 10 ms

DATA Polling for End of Program Detection

Low Power Dissipation

50 mA Active Current

μ

Typical Endurance > 10,000 Cycles

Single 5V ±10% Supply

CMOS and TTL Compatible Inputs and Outputs

Commercial and Industrial Temperature Ranges100 A CMOS Standby Current

Description

The AT29C512 is a 5-volt-only in-system Flash programmable and erasable read only memory (PEROM). Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 μA. The device endurance is such that any sector can typically be written to in excess of 10,000 times.

(continued)

DIP Top View

Pin Configurations

 

Pin Name

Function

 

A0 - A15

Addresses

 

 

 

 

 

 

 

 

 

 

 

CE

Chip Enable

 

 

 

 

 

 

OE

Output Enable

 

 

 

 

 

 

 

 

 

 

WE

Write Enable

 

 

 

 

 

 

I/O0 - I/O7

Data Inputs/Outputs

 

NC

No Connect

PLCC Top View

TSOP Top View

Type 1

512K (64K x 8)

5-volt Only CMOS Flash Memory

0456B

4-117

Description (Continued)

To allow for simple in-system reprogrammability, the AT29C512 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C512 is performed on a sector basis; 128-bytes of data are loaded into the device and then simultaneously programmed.

Block Diagram

Device Operation

READ: The AT29C512 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus contention.

BYTE LOAD: Byte loads are used to enter the 128bytes of a sector to be programmed or the software codes for data protection. A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.

PROGRAM: The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any byte that is not loaded during the programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high to low transition on WE (or CE) within 150 μs of the low to high transition of WE (or CE) of the preceding byte. If a high to low transition is not detected within 150 μs of the last low to high transition, the load period will end and the internal programming

4-118 AT29C512

During a reprogram cycle, the address locations and 128bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected, a new access for a read or program can begin.

period will start. A7 to A15 specify the sector address. The sector address must be valid during each high to low transition of WE (or CE). A0 to A6 specify the byte address within the sector. The bytes may be loaded in any order; sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation.

SOFTWARE DATA PROTECTION: A software controlled data protection feature is available on the AT29C512. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user; when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the sector program timing specifications. Once set, the software data protection feature remains active unless its disable command is issued. Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions.

(continued)

Device Operation (Continued)

Once set, software data protection will remain active unless the disable command sequence is issued.

After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, a read operation will effectively be a polling operation.

After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 128-bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation.

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT29C512 in the following ways: (a) VCC sense— if V CC is below 3.8V (typical), the program function is inhibited. (b) VCC power on delay— once V CC has reached the VCC sense level, the device will automatically time out 5 ms (typical) before programming. (c) Program inhibit— holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter— pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming al-

AT29C512

gorithm for the Atmel product. In addition, users may wish to use the software product identification mode to identify the part (i.e. using the device code), and have the system software use the appropriate sector size for program operations. In this manner, the user can have a common board design for 256K to 4-megabit densities and, with each density’s sector size in a memory map, have the system software apply the appropriate sector size.

For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING: The AT29C512 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.

TOGGLE BIT: I n a d d i t i o n t o DATA p o l li ng t he AT29C512 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a 6-byte software code. Please see Software Chip Erase application note for details.

Absolute Maximum Ratings*

Temperature Under Bias

................. -55°C to +125°C

Storage Temperature......................

-65°C to +150°C

All Input Voltages

 

(including NC Pins)

 

with Respect to Ground ...................

-0.6V to +6.25V

All Output Voltages

 

with Respect to Ground .............

- 0.6V to VCC + 0.6V

 

 

 

 

Voltage on OE

 

with Respect to Ground ...................

-0.6V to +13.5V

 

 

 

 

*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

4-119

DC and AC Operating Range

 

 

AT29C512-70

AT29C512-90

AT29C512-12

AT29C512-15

Operating

Com.

0°C - 70°C

0°C - 70°C

0°C - 70°C

0°C - 70°C

Temperature (Case)

Ind.

 

-40°C - 85°C

-40°C - 85°C

-40°C - 85°C

VCC Power Supply

 

5V ± 5%

5V ± 10%

5V ± 10%

5V ± 10%

Operating Modes

Mode

 

 

 

 

 

 

Ai

I/O

CE

OE

WE

 

Read

VIL

VIL

VIH

 

Ai

DOUT

Program (2)

VIL

VIH

VIL

 

Ai

DIN

5V Chip Erase

VIL

VIH

VIL

 

Ai

 

Standby/Write Inhibit

VIH

X (1)

X

 

X

High Z

Program Inhibit

X

X

VIH

 

 

 

Program Inhibit

X

VIL

X

 

 

 

Output Disable

X

VIH

X

 

 

High Z

Product Identification

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1 - A15 = VIL, A9 = VH,(3)

Manufacturer Code (4)

Hardware

VIL

VIL

VIH

 

A0 = VIL

 

 

A1 - A15 = VIL, A9 = VH,(3)

Device Code (4)

 

 

 

 

 

 

 

A0 = VIH

 

Software (5)

 

 

 

 

 

 

A0 = VIL

Manufacturer Code (4)

 

 

 

 

 

 

A0 = VIH

Device Code (4)

 

 

 

 

 

 

 

Notes: 1. X can be VIL or VIH.

 

 

 

 

 

4. Manufacturer Code: 1F, Device Code: 5D

2. Refer to AC Programming Waveforms.

 

5. See details under Software Product Identification Entry/Exit.

3. VH = 12.0V ± 0.5V

 

 

 

 

 

 

 

 

DC Characteristics

Symbol

Parameter

Condition

Min

Max

Units

ILI

Input Load Current

VIN = 0V to VCC

 

10

μA

ILO

Output Leakage Current

VI/O = 0V to VCC

 

10

μA

ISB1

VCC Standby Current CMOS

 

Com.

 

100

μA

 

 

CE = VCC - 0.3V to VCC

 

300

μA

 

 

 

Ind.

 

ISB2

 

 

 

 

 

 

VCC Standby Current TTL

CE = 2.0V to VCC

 

3

mA

ICC

VCC Active Current

f = 5 MHz; IOUT = 0 mA

 

50

mA

VIL

Input Low Voltage

 

 

 

0.8

V

VIH

Input High Voltage

 

 

2.0

 

V

VOL

Output Low Voltage

IOL = 2.1 mA

 

.45

V

VOH1

Output High Voltage

IOH = -400 μA

2.4

 

V

VOH2

Output High Voltage CMOS

IOH = -100 μA; VCC = 4.5V

4.2

 

V

4-120 AT29C512

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