ATMEL AT28LV64B-25PC, AT28LV64B-25JI, AT28LV64B-25JC, AT28LV64B-20TI, AT28LV64B-20TC Datasheet

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ATMEL AT28LV64B-25PC, AT28LV64B-25JI, AT28LV64B-25JC, AT28LV64B-20TI, AT28LV64B-20TC Datasheet
Pin Configurations

AT28LV64B

Features

Single 3.3V ± 10% Supply

3-Volt-Only Read and Write Operation

Software-Protected Programming

Low Power Dissipation

15 mA Active Current

μ

Fast Read Access Time 200 ns

Automatic Page Write Operation20 A CMOS Standby Current

Internal Address and Data Latches for 64-Bytes Internal Control Timer

Fast Write Cycle Times

Page Write Cycle Time: 10 ms Maximum

1to 64-Byte Page Write Operation

DATA Polling for End of Write Detection

High Reliability CMOS Technology Endurance: 10,000 Cycles Data Retention: 10 Years

JEDEC Approved Byte-Wide Pinout

Commercial and Industrial Temperature Ranges

Description

The AT28LV64B is a high-performance electrically erasable programmable read only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 μA.

The AT28LV64B is accessed like a static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow

(continued)

 

Pin Name

 

 

Function

 

A0 - A12

 

 

Addresses

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

Chip Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

Output Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

 

 

Write Enable

 

I/O0 - I/O7

 

 

Data Inputs/Outputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

 

No Connect

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DC

 

 

Don’t Connect

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLCC

 

 

 

 

 

 

 

Top View

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PDIP, SOIC

Top View

TSOP

Top View

64K (8K x 8) Low Voltage CMOS E2PROM with Page Write and Software Data Protection

Note: PLCC package pins 1 and

17 are DON’T CONNECT.

0299C

2-135

Description (Continued)

writing of up to 64-bytes simultaneously. During a write cycle, the addresses and 1 to 64-bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin.

Atmel’s 28LV64B has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. A software data protection mechanism guards against inadvertent writes. The device also includes an extra 64-bytes of E2PROM for device identification or tracking.

Block Diagram

Absolute Maximum Ratings*

Temperature Under Bias

................. -55°C to +125°C

Storage Temperature......................

-65°C to +150°C

All Input Voltages

 

(including NC Pins)

 

with Respect to Ground ...................

-0.6V to +6.25V

All Output Voltages

 

with Respect to Ground .............

- 0.6V to VCC + 0.6V

 

 

 

 

Voltage on OE and A9

 

with Respect to Ground ...................

-0.6V to +13.5V

 

 

 

 

*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2-136 AT28LV64B

Device Operation

READ: The AT28LV64B is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their systems.

BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cy- cle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation.

PAGE WRITE: The p ag e wr i te operation of the AT28LV64B allows 1 to 64-bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 100 ms (tBLC) of the previous byte. If the tBLC limit is exceeded, the AT28LV64B will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 to A12 inputs. For each WE high to low transition during the page write operation, A6 to A12 must be the same.

The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.

DATA POLLING: The AT28LV64B features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle.

TOGGLE BIT: I n a d d i t i o n t o DATA Polling, the AT28LV64B provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be

AT28LV64B

read. Reading the toggle bit may begin at any time during the write cycle.

DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes.

HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28LV64B in the following ways: (a) VCC power-on delayonce VCC has reached 1.8V (typical) the device will automatically time out 10 ms (typical) before allowing a write; (b) write inhibit¾holding any one of OE low, CE high or WE high inhibits write cycles; (c) noise filter¾pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle.

SOFTWARE DATA PROTECTION: A software-control- led data protection feature has been implemented on the AT28LV64B. Software data protection (SDP) helps prevent inadvertent writes from corrupting the data in the device. SDP can prevent inadvertent writes during power-up and power-down as well as any other potential periods of system instability.

The AT28LV64B can only be written using the software data protection feature. A series of three write commands to specific addresses with specific data must be presented to the device before writing in the byte or page mode. The same three write commands must begin each write operation. All software write commands must obey the page mode write timing specifications. The data in the 3-byte command sequence is not written to the device; the addresses in the command sequence can be utilized just like any other location in the device.

Any attempt to write to the device without the 3-byte sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations.

DEVICE IDENTIFICATION: A n e x t r a 6 4 - b y t e s o f E2PROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH, the additional bytes may be written to or read from in the same manner as the regular memory array.

2-137

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