AT28C64B
Features
∙Fast Read Access Time - 150 ns
∙Automatic Page Write Operation
Internal Address and Data Latches for 64-Bytes ∙ Fast Write Cycle Times
Page Write Cycle Time: 10 ms Maximum
1to 64-Byte Page Write Operation
∙Low Power Dissipation
40mA Active Current
μ
∙Hardware and Software Data Protection
∙DATA Polling and Toggle Bit for End of Write Detection
∙High Reliability CMOS Technology100 A CMOS Standby Current
Endurance: 100,000 Cycles
∙Single 5V ± 10% Supply
∙CMOS and TTL Compatible Inputs and Outputs
∙JEDEC Approved Byte-Wide Pinout
∙Commercial and Industrial Temperature RangesData Retention: 10 Years
Description
The AT28C64B is a high-performance electrically erasable and programmable read only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 100 μA.
(continued)
Pin Configurations |
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PDIP, SOIC |
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Pin Name |
Function |
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Top View |
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A0 - A12 |
Addresses |
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CE |
Chip Enable |
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OE |
Output Enable |
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WE |
Write Enable |
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I/O0 - I/O7 |
Data Inputs/Outputs |
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NC |
No Connect |
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DC |
Don’t Connect |
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PLCC
Top View
TSOP
Top View
Note: PLCC package pins 1 and 17 are DON’T CONNECT.
64K (8K x 8) CMOS E2PROM with Page Write and Software Data Protection
0270E
2-205
Description (Continued)
The AT28C64B is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64-bytes simultaneously. During a write cycle, the addresses and 1 to 64-bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin.
Atmel’s AT28C64B has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64-bytes of E2PROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature Under Bias |
................. -55°C to +125°C |
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Storage Temperature...................... |
-65°C to +150°C |
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All Input Voltages |
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(including NC Pins) |
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with Respect to Ground ................... |
-0.6V to +6.25V |
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All Output Voltages |
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with Respect to Ground ............. |
- 0.6V to VCC + 0.6V |
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Voltage on OE and A9 |
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with Respect to Ground ................... |
-0.6V to +13.5V |
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*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2-206 AT28C64B
Device Operation
READ: The AT28C64B is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the highimpedance state when either CE or OE is high. This dual line control gives designers flexibility in preventing bus contention in their systems.
BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cy- cle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation.
PAGE WRITE: The p ag e wr i te operation of the AT28C64B allows 1 to 64-bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63 additional bytes. Each successive byte must be loaded within 150 μs (tBLC) of the previous byte. If the tBLC limit is exceeded, the AT28C64B will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 to A12 inputs. For each WE high to low transition during the page write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
DATA POLLING: The AT28C64B features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at any time during the write cycle.
TOGGLE BIT: In addition to DATA Polling, the AT28C64B provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling, and valid data will be read. Toggle bit reading may begin at any time during the write cycle.
AT28C64B
DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent writes to the AT28C64B in the following ways: (a) VCC sense - if VCC is below 3.8V (typical), the write function is inhibited; (b) VCC power-on delay - once VCC has reached 3.8V, the device will automatically time out 5 ms (typical) before allowing a write; (c) write inhibit - holding any one of OE low, CE high, or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C64B. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C64B is shipped from Atmel with SDP disabled.
SDP is enabled by the user issuing a series of three write commands in which three specific bytes of data are written to three specific addresses (refer to the Software Data Protection Algorithm diagram in this data sheet). After writing the 3-byte command sequence and waiting tWC, the entire AT28C64B will be protected against inadvertent writes. It should be noted that even after SDP is enabled, the user may still perform a byte or page write to the AT28C64B by preceding the data to be written by the same 3-byte command sequence used to enable SDP.
Once set, SDP remains active unless the disable command sequence is issued. Power transitions do not disable SDP, and SDP protects the AT28C64B during powerup and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not actually written into the device; their addresses may still be written with user data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device. However, for the duration of tWC, read operations will effectively be polling operations.
DEVICE IDENTIFICATION: A n e x t r a 6 4 - b y t e s o f EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 1FC0H to 1FFFH, the additional bytes may be written to or read from in the same manner as the regular memory array.
2-207
DC and AC Operating Range
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AT28C64B-15 |
AT28C64B-20 |
AT28C64B-25 |
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Operating |
Com. |
0°C - 70°C |
0°C - 70°C |
0°C - 70°C |
Temperature (Case) |
Ind. |
-40°C - 85°C |
-40°C - 85°C |
-40°C - 85°C |
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VCC Power Supply |
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5V ± 10% |
5V ± 10% |
5V ± 10% |
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Operating Modes
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Mode |
CE |
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OE |
WE |
I/O |
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Read |
VIL |
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VIL |
VIH |
DOUT |
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Write (2) |
VIL |
VIH |
VIL |
DIN |
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Standby/Write Inhibit |
VIH |
X (1) |
X |
High Z |
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Write Inhibit |
X |
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X |
VIH |
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Write Inhibit |
X |
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VIL |
X |
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Output Disable |
X |
VIH |
X |
High Z |
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Chip Erase |
VIL |
VH (3) |
VIL |
High Z |
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Notes: 1. X can be VIL or VIH. |
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3. VH = 12.0V ± 0.5V. |
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2.Refer to the AC Write Waveforms diagrams in this data sheet.
DC Characteristics
Symbol |
Parameter |
Condition |
Min |
Max |
Units |
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ILI |
Input Load Current |
VIN = 0V to VCC + 1V |
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10 |
μA |
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ILO |
Output Leakage Current |
VI/O = 0V to VCC |
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10 |
μA |
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μA |
ISB1 |
VCC Standby Current CMOS |
CE = VCC - 0.3V to VCC + 1V Com., Ind. |
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ISB2 |
VCC Standby Current TTL |
CE = 2.0V to VCC + 1V |
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2 |
mA |
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ICC |
VCC Active Current |
f = 5 MHz; IOUT = 0 mA |
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40 |
mA |
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VIL |
Input Low Voltage |
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0.8 |
V |
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VIH |
Input High Voltage |
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2.0 |
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V |
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VOL |
Output Low Voltage |
IOL = 2.1 mA |
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.40 |
V |
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VOH |
Output High Voltage |
IOH = -400 μA |
2.4 |
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V |
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2-208 AT28C64B