ATMEL AT28C040-20BISL703, AT28C040-20BI, AT28C040-20BC, AT28C040-25LISL703, AT28C040-25LI Datasheet

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ATMEL AT28C040-20BISL703, AT28C040-20BI, AT28C040-20BC, AT28C040-25LISL703, AT28C040-25LI Datasheet

Features

Read Access Time - 200 ns

Automatic Page Write Operation

Internal Address and Data Latches for 256 Bytes

Internal Control Timer

Fast Write Cycle Time

Page Write Cycle Time - 10 ms Maximum

1 to 256 Byte Page Write Operation

Low Power Dissipation

80 mA Active Current

Hardware and Software Data Protection

DATA Polling for End of Write Detection

High Reliability CMOS Technology

Endurance: 10,000 Cycles

Data Retention: 10 Years

Single 5V ± 10% Supply

CMOS and TTL Compatible Inputs and Outputs

JEDEC Approved Byte-Wide Pinout

Description

The AT28C040 is a high-performance electrically erasable and programmable read only memory (E2PROM). Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 440 mW.

(continued)

Pin Configurations

 

Pin Name

Function

 

 

 

 

A0 - A18

Addresses

 

 

 

 

 

 

 

 

 

 

 

Chip Enable

 

CE

 

 

 

 

 

 

 

 

 

 

Output Enable

 

OE

 

 

 

 

 

 

 

 

 

Write Enable

 

WE

 

 

 

 

I/O0 - I/O7

Data Inputs/Outputs

 

 

 

 

NC

No Connect

 

 

 

 

 

 

SIDE BRAZE,

FLATPACK

Top View

LCC

Top View

4-Megabit

(512K x 8)

Paged E2PROM

AT28C040

Rev. 0542B–04/98

1

The AT28C040 is accessed like a static RAM for the read or write cycle without the need for external components. The device contains a 256-byte page register to allow writing of up to 256 bytes simultaneously. During a write cycle, the address and 1 to 256 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by

DATA POLLING of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin.

Atmel's AT28C040 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 256 bytes of E2PROM for device identification or tracking.

Block Diagram

Absolute Maximum Ratings*

Temperature Under Bias

................................ -55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

 

 

 

 

Maximum Ratings” may cause permanent dam-

Storage Temperature .....................................

-65°C to +150°C

age to the device. This is a stress rating only and

 

 

 

 

functional operation of the device at these or any

All Input Voltages

 

other conditions beyond those indicated in the

(including NC pins)

 

operational sections of this specification is not

with Respect to Ground ...................................

-0.6V to +6.25V

implied. Exposure to absolute maximum rating

All Output Voltages

 

conditions for extended periods may affect device

- 0.6V to VCC + 0.6V

reliability.

with Respect to Ground .............................

 

Voltage on

 

and A9

 

 

OE

 

 

with Respect to Ground ...................................

-0.6V to +13.5V

 

 

 

 

 

 

2

AT28C040

 

 

 

Device Operation

READ: The AT28C040 is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their systems.

BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation.

PAGE WRITE: The page write operation of the AT28C040 allows 1 to 256 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 255 additional bytes. Each successive byte must be written within 150 μs (tBLC) of the previous byte. If the tBLC limit is exceeded, the AT28C040 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A8 - A18 inputs. For each WE high to low transition during the page write operation, A8 - A18 must be the same.

The A0 to A7 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.

DATA POLLING: The AT28C040 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle.

TOGGLE BIT: In addition to DATA Polling, the AT28C040 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.

DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware

AT28C040

and software features that will protect the memory against inadvertent writes.

HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28C040 in the following ways: (a) VCC sense - if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay - once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle.

SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C040. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C040 is shipped from Atmel with SDP disabled.

SDP is enabled when the host system issues a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after tWC, the entire AT28C040 will be protected against inadvertent write operations. It should be noted that once protected, the host can still perform a byte or page write to the AT28C040. To do so, the same 3-byte command sequence used to enable SDP must precede the data to be written.

Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP, and SDP will protect the AT28C040 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device, and the memory addresses used in the sequence may be written with data in either a byte or page write operation.

After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations.

DEVICE IDENTIFICATION: An extra 256 bytes of E2PROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 7FF80H to 7FFFFH, the bytes may be written to or read from in the same manner as the regular memory array.

OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software erase code. Please see Software Chip Erase application note for details.

3

DC and AC Operating Range

 

 

AT28C040-20

AT28C040-25

 

 

 

 

 

 

 

Operation

 

Operation

 

 

 

 

 

 

 

 

 

Read

Program

Read

 

Program

 

 

 

 

 

 

 

Operating

Commercial

0°C - 70°C

0°C - 70°C

0°C - 70°C

 

0°C - 70°C

 

 

 

 

 

 

 

 

 

 

 

 

Temperature

Industrial

-40°C - 85°C

-40°C - 85°C

-40°C - 85°C

 

-40°C - 85°C

(Case)

 

 

 

 

 

 

Extended

-55°C - 125°C

-40°C - 85°C

-55°C - 125°C

 

-40°C - 85°C

 

 

 

 

 

 

 

 

 

VCC Power Supply

 

5V ± 10%

5V ± 10%

5V ± 10%

 

5V ± 10%

Operating Modes

Mode

CE

OE

WE

I/O

 

 

 

 

 

Read

VIL

VIL

VIH

DOUT

Write(2)

V

IL

V

IH

V

IL

D

 

 

 

 

IN

Standby/Write Inhibit

V

 

X(1)

X

High Z

 

IH

 

 

 

 

 

Write Inhibit

X

X

VIH

 

Write Inhibit

X

VIL

X

 

Output Disable

X

VIH

X

High Z

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.

DC Characteristics

Symbol

Parameter

Condition

Min

Max

Units

 

 

 

 

 

 

ILI

Input Load Current

VIN = 0V to VCC + 1V

 

10

μA

ILO

Output Leakage Current

VI/O = 0V to VCC

 

10

μA

ISB1

VCC Standby Current CMOS

 

 

= VCC - 0.3V to VCC + 1V

 

3

mA

 

CE

 

ISB2

VCC Standby Current TTL

 

 

= 2.0V to VCC + 1V

 

3

mA

CE

 

ICC

VCC Active Current

 

f = 5 MHz; IOUT = 0 mA

 

80

mA

VIL

Input Low Voltage

 

 

 

 

0.8

V

VIH

Input High Voltage

 

 

 

2.0

 

V

VOL

Output Low Voltage

 

IOL = 2.1 mA

 

0.45

V

VOH1

Output High Voltage

 

IOH = -400 μA

2.4

 

V

VOH2

Output High Voltage CMOS

IOH = -100 μA; VCC = 4.5V

4.2

 

V

4

AT28C040

 

 

 

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