ATMEL AT28C010E-25UM-883, AT28C010E-25LM-883, AT28C010E-25EM-883, AT28C010E-25DM-883, AT28C010E-20UM-883 Datasheet

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AT28C010 Mil
1 Megabit
(128K x 8)
Paged
CMOS
E
PROM
Military
Features
Fast Read Access Time - 120 ns
Automatic Page Write Operation
Internal Address and Data Latches for 128-Bytes
Internal Control Timer
Fast Write Cycle Tim e
Page Write Cycle Time - 10 ms Maximum
1 to 128-Byte Page Write Ope rati on
Low Power Dissipation
80 mA Active Current
300 µA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Dete cti on
High Reliabili ty C MOS Technology
Endurance: 10
4
or 10
5
Cycles
Data Retention: 10 Years
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-Wid e Pin ou t
Description
The AT28C010 is a high-performance Electrically Erasable and Progr ammable Read
Only Memory. Its one megabit of memory is organized as 131,072 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology , the device offers
(continued)
CERDIP, FLATPACK
Top View
Pin Name Function
A0 - A16 Addresses
CE Chip Enable
OE Output E nable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
Pin Configurations
44 LCC
Top View
32 LCC
Top View
PGA
Top View
0353C
AT28C010 Mil
2-243
Block Diagram
Temperature Under Bias.................-55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed un der “Abso lute Maxi-
mum Ratings” may cause permanen t dama ge to th e de vice .
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Absolute Maximum Ratings*
access times to 120 ns with power dissipation of just 440
mW. When the device is deselected, the CMOS standby
current is less than 300 µA.
The AT28C010 is accessed like a Static RAM for the read
or write cycle without the need for external components.
The device contains a 128-byte page register to allow writ-
ing of up to 128-bytes simultaneously. During a write cy-
cle, the address and 1 to 128-bytes of data are internally
latched, freeing the address and data bus for other opera-
tions. Following the initiation of a write cycle, the device
will automatically write the latched data using an internal
control timer. The end of a write cycle can be detected by
DATA POLLING of I/O7. Once the end of a write cycle has
been detected a new access for a read or write can begin.
Atmel’s 28C010 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correc tion for extended endurance and improved
data retention characteristics. An optional software data
protection mechanism is available to guard against inad-
vertent w rites. The device also includes an extra 128-
bytes of E
2
PROM for device identification or tracking.
Description (Continued)
2-244 AT28C010 Mil
Device Operation
READ: The AT28C010 is accessed like a Static RAM.
When
CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either
CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention in their system.
BYTE WRITE: A low pulse on the
WE or CE input with CE
or
WE low (respectively) and OE high initiates a write cy-
cle. The address is latched on the falling edge of
CE or
WE, whichever occurs last. The data is latched by the firs t
rising edge of
CE or WE. Once a byte write has been
started it will automatically time itself to completion. Once
a programming operation has been initiated and for the
duration of t
WC
, a read operation will effectively be a poll-
ing operation.
PAGE WRITE: The page write operation of the AT28C010
allows 1 to 128-bytes of data to be written into the device
during a single internal programming period. A page write
operation is initiated in the same manner as a byte write;
the first byte written can then be followed by 1 to 127 ad-
ditional bytes. Each successive byte must be written within
150 µs (t
BLC
) of the previous byte. If the t
BLC
limit is ex-
ceeded the AT28C010 will cease accepting data and com-
mence the internal programming operation. All bytes dur-
ing a page write operation must reside on the same page
as defined by the state of the A7 - A16 inputs. For each
WE high to low transition during the page write operation,
A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
DATA POLLING: The AT28C010 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complem ent of the written data to be pre-
sented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin.
DATA Polling may begin at anytime during the
write cycle.
TOGGLE BIT: In addition to
DATA Polling the AT28C010
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling be-
tween one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory agains t
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28C010 in the follow-
ing ways: (a) V
CC
sense - if V
CC
is below 3.8V (typical) the
write function is inhibited; (b) V
CC
power-on delay - once
V
CC
has reached 3.8V the device will automatically time
out 5 ms (typical) before allowing a write: (c) write inhibit -
holding any one of
OE low, CE high or WE high inhibits
write cycles; (d) noise filter - pulses of less than 15 ns (typi-
cal) on the
WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software controlled
data protection feature has been implemented on the
AT28C010. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C010 is
shipped from Atmel with SDP disabled.
SDP is enabled by the h ost system issuing a series of
three write co mmands; three specific bytes of data are
written to three specific addresses (refer to Software Data
Protection Algorithm). After writing the 3-byte command
sequence and after t
WC
the entire AT28C010 will be pro-
tected against inadvertent write operations. It should be
noted, that o nce protected the host may sti ll perform a
byte or page write to the AT28C010. This is done by pre-
ceding the data to be written by the same 3-byte command
sequence used to enable SDP.
Once set, SDP will remain active unless the disable com-
mand sequence is issued. Power transitions do not dis-
able SDP and SDP will protect the AT28C010 during
power-up and power-down conditions. All command se-
quences must conform to the page write timing specifica-
tions. The data in the enable and disable command se-
quences is not written to the device and the memory ad-
dresses used in the sequence may be written with data in
either a byte or page write operation.
After setting SDP, any attempt to write to the device with-
out the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of t
WC
, read operations will effectively be
polling operations.
(continued)
AT28C010 Mil
2-245
Mode CE OE WE I/O
Read V
IL
V
IL
V
IH
D
OUT
Write
(2)
V
IL
V
IH
V
IL
D
IN
Standby/Write Inhibit V
IH
X
(1)
X High Z
Write Inhibit X X V
IH
Write Inhibit X V
IL
X
Output Disable X V
IH
X High Z
Notes: 1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
Operating Modes
Symbol Parameter Condition Min Max Units
I
LI
Input Load Current V
IN
= 0V to V
CC
+ 1V 10 µA
I
LO
Output Leakage Current V
I/O
= 0V to V
CC
10 µA
I
SB1
V
CC
Standby Current CMOS CE = V
CC
- 0.3V to V
CC
+ 1V 300 µA
I
SB2
V
CC
Standby Current TTL CE = 2.0V to V
CC
+ 1V 3 m A
I
CC
V
CC
Active Current f = 5 MHz; I
OUT
= 0 mA 80 mA
V
IL
Input Low Voltage 0.8 V
V
IH
Input High Voltage 2.0 V
V
OL
Output Low Voltage I
OL
= 2.1 mA .45 V
V
OH1
Output High Voltage I
OH
= -400 µA 2.4 V
V
OH2
Output High Voltage CMOS I
OH
= -100 µA; V
CC
= 4.5V 4.2 V
DC Characteristics
AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25
Operating
Temperature (Case)
Mil. -55°C - 125°C -55°C - 125°C -55°C - 125°C -55°C - 125°C
V
CC
Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%
DC and AC Operating Range
DEVICE IDENTIFICATION: An extra 128-bytes of
E
2
PROM memory are available to the user for device
identification. By raising A9 to 12V ± 0.5V and using ad-
dress locations 1FF80H to 1FFFFH the bytes may be writ-
ten to or read from in the same manner as the regular
memory array.
OPTIONAL CHIP ERASE MODE: The entire device can
be erased using a 6-byte software code. Please see Soft-
ware Chip Erase application note for details.
Device Operation (Continued)
2-246 AT28C010 Mil
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