ATMEL AT28BV64-30SC, AT28BV64-30PI, AT28BV64-30PC, AT28BV64-30JI, AT28BV64-30JC Datasheet

AT28BV64

Features

∙ 2.7V to 3.6V Supply

Full Read and Write Operation ∙ Low Power Dissipation

8 mA Active Current

μ

∙Read Access Time - 300 ns

∙Byte Write - 3 ms

∙Direct Microprocessor Control DATA Polling

READY/BUSY Open Drain Output

∙High Reliability CMOS Technology Endurance: 100,000 Cycles Data Retention: 10 Years

∙JEDEC Approved Byte-Wide Pinout

∙Commercial and Industrial Temperature Ranges50 A CMOS Standby Current

Description

The AT28BV64 is a low-voltage, low-power Electrically Erasable and Programmable Read Only Memory specifically designed for battery powered applications. Its 64K of memory is organized 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation less than 30 mW. When the device is deselected the standby current is less than 50 μA.

The AT28BV64 is accessed like a Static RAM for the read or write cycles without the need for external components. During a byte write, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Fol-

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Pin Configurations

PDIP, SOIC Top View

Pin Name

Function

A0 - A12

Addresses

CE

Chip Enable

OE

Output Enable

WE

Write Enable

I/O0 - I/O7

Data Inputs/Outputs

RDY/BUSY

Ready/Busy Output

NC

No Connect

DC

Don’t Connect

PLCC Top View

TSOP Top View

64K (8K x 8)

Battery-Voltage™

CMOS E2PROM

0493A

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Description (Continued)

lowing the initiation of a write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. The device includes two methods for detecting the end of a write cycle, level detection of RDY/BUSY and DATA polling of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin.

Atmel’s 28BV64 has additional features to ensure high quality and manufacturability. The device utilizes error correction internally for extended endurance and for improved data retention characteristics. An extra 32-bytes of E2PROM are available for device identification or tracking.

Block Diagram

Absolute Maximum Ratings*

Temperature Under Bias			................. -55°C to +125°C
Storage Temperature......................			-65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................			-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............			- 0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ...................			-0.6V to +13.5V

*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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Device Operation

READ: The AT28BV64 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in a high impedance state whenever CE or OE is high. This dual line control gives designers increased flexibility in preventing bus contention.

BYTE WRITE: Writing data into the AT28BV64 is similar to writing into a Static RAM. A low pulse on the WE or CE input with OE high and CE or WE low (respectively) initiates a byte write. The address location is latched on the falling edge of WE (or CE); the new data is latched on the rising edge. Internally, the device performs a self-clear before write. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation.

READY/BUSY: Pin 1 is an open drain READY/BUSY output that can be used to detect the end of a write cycle. RDY/BUSY is actively pulled low during the write cycle and is released at the completion of the write. The open drain connection allows for OR-tying of several devices to the same RDY/BUSY line.

AT28BV64

DATA POLLING: The AT28BV64 provides DATA POLLING to signal the completion of a write cycle. During a write cycle, an attempted read of the data being written results in the complement of that data for I/O7 (the other outputs are indeterminate). When the write cycle is finished, true data appears on all outputs.

WRITE PROTECTION: Inadvertent writes to the device are protected against in the following ways. (a) VCC sense— if V CC is below 1.8V (typical) the write function is inhibited. (b) VCC power on delay— once V CC h a s reached 2.0V the device will automatically time out 10 ms (typical) before allowing a byte write. (c) Write Inhibit— holding any one of OE low, CE high or WE high inhibits byte write cycles.

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