ATMEL AT27C4096-90JI, AT27C4096-90JC, AT27C4096-70VI, AT27C4096-70VC, AT27C4096-70PI Datasheet

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AT27C4096
1
Features
Fast Read Access Time - 55 ns
Low Power CMOS Operation
100
µ
40 mA Maximum Active at 5 MHz
JEDEC Standard Packages
40-Lead 600 mil PDIP
44-Lead PLCC
40-Lead TSOP (10 mm x 14 mm)
Direct Upgrade from 512K bit, 1M bit, and 2M bit
(AT27C516, AT27C1024, and AT27C2048) EPROMs
5V ± 10% Power Supply
High Reliability CMOS Technology
2,000V ESD Protection
200 mA Latchup Immunity
Rapid
Programming Algorithm - 50
µ
s/word (typical)
CMOS and TTL Compatible Inputs and Outputs
Integrated Product Identification Code
Commercial and Industrial Temperature Ranges
Description
The AT27C4096 is a low-power, high-performance 4,194,304-bit one-time program-
mable read only memor y (OTP EP ROM) organiz ed 256K by 16 bits . It requ ires a s in-
gle 5V power supply in nor mal read mode op eration. Any w ord can be acce ssed in
less than 55 ns , eliminatin g the need fo r speed-redu cing WAIT states. T he by-16
organization makes this part ideal for high-performance 16- and 32-bit microprocessor
systems.
TSOP Top View
Type 1
PDIP Top View
PLCC Top View
4-Megabit
(256K x 16)
OTP EPROM
AT27C4096
0311E-A–06/97
Pin Configurations
Note: Both GND pins must be
connected.
Pin Name Function
A0 - A17 Addresses
O0 - O15 Outputs
CE
Chip Enable
OE
Output Enable
NC No Connect
(continued)
AT27C4096
2
Description
In read mode, the AT27C4096 typically consumes 15 mA.
Standby mode supply current is typically less than 10
µ
A.
The AT27C4096 is ava ilable in industry standard
JEDEC-approved one -time programm able (OTP) plasti c
PDIP, PLCC, and TSOP pa ckages. The de vice features
two-line control (CE
, OE) to eliminate bus contention in
high-speed systems.
With high density 256K word storage capability, the
AT27C4096 allows firmware to be store d reliabl y and to be
accessed by the system without the delays of mass storage
media.
Atmel’s AT27C4096 has additional features that ensure
high quality and efficient production use. The Rapid
Pro-
gramming Algorithm reduces the time required to program
the part and guarantees reliable programming. Program-
ming time is typically only 50
µ
s/word. The Integrated Prod-
uct Identifi cation Co de elect ronicall y identi fies the d evice
and manufacturer. This feature is use d by industry stan-
dard programming equipment to select the proper program-
ming algorithms and voltages.
System Considerations
Switching between active and standby conditions via the
Chip Enable pin may produce tr ans ie nt v olta ge e xcur sion s.
Unless accommodated by the system design, these tran-
sients may exceed data sheet limits, resulting in device
non-conformance . At a minim um, a 0.1
µ
F high frequency,
low inherent inductance, ceramic capacitor should be uti-
lized for each device. This capacitor shoul d be connected
between the V
CC
and Ground terminals of the device, as
close to the device as possible. Additionally, to stabilize the
supply voltage level on printed circuit boards with large
EPROM arrays, a 4.7
µ
F bulk electrolytic capacitor should
be utilized, agai n connec ted betwe en the V
CC
and Ground
terminals. This capacitor should be positioned as close as
possible to the point where the power supply is connected
to the array.
AT27C4096
3
Block Diagram
Operating Modes
Notes: 1. X can be V
IL
or V
IH
.
2. Refer to the Programming characteristics.
3. V
H
= 12.0 ± 0.5V.
4. Two identifier words ma y be selec ted. All Ai input s are held low (V
IL
), except A9 , which is set to V
H
, and A0, wh ich i s to ggl ed
low (V
IL
) to select the Manufacturer’s Identification word and high (V
IH
) to select the Device Code word.
5. Standby V
CC
current (I
SB
) is specified with V
PP
= V
CC
. V
CC
> V
PP
will cause a slight increase in I
SB
.
Mode/Pin CE OE Ai V
PP
Outputs
Read V
IL
V
IL
Ai X
(1)
D
OUT
Output Disable X V
IH
X X High Z
Standby V
IH
XXX
(5)
High Z
Rapid Program
(2)
V
IL
V
IH
Ai V
PP
D
IN
PGM Verify V
IH
V
IL
Ai V
PP
D
OUT
PGM Inhibit V
IH
V
IH
XV
PP
High Z
Product Identification
(4)
V
IL
V
IL
A9 = V
H
(3)
A0 = V
IH
or V
IL
A1 - A17 = V
IL
V
CC
Identification Code
Absolute Maximum Ratings*
Temperature Under Bias ......................-55
°
C to +125
°
C
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the dev ice . This is a stress rating only an d
functional operati on of the de vi ce at these or an y
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or exten ded periods ma y affect d evice
reliability .
Note: Maximum voltage is -0.6V dc which may undershoot
to -2.0V for pulses of less than 20 ns. Maximum out-
put pin voltage is V
CC
+ 0.75V dc which may over-
shoot to +7.0V for pulses of less than 20 ns.
Storage Temperature............................-65
°
C to +150
°
C
Voltage on Any Pin with
Respect to Ground ...............................-2.0V to +7.0V
(1)
Voltage on A9 with
Respect to Ground ............................-2.0V to +14.0V
(1)
V
PP
Supply Voltage with
Respect to Ground .............................-2.0V to +14.0V
(1)
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