ATMEL AT25P1024W1-10SI-2.7, AT25P1024W1-10SI-1.8, AT25P1024W1-10SI, AT25P1024W1-10SC-2.7, AT25P1024W1-10SC-1.8 Datasheet

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Features

Serial Peripheral Interface (SPI) Compatible

Supports SPI Modes 0 (0,0) and 3 (1,1)

2.1 MHz Clock Rate

128-Byte Page Mode Only for Write Operations

Low Voltage and Standard Voltage Operation

5.0 (V CC = 4.5V to 5.5V)

2.7 (V CC = 2.7V to 5.5V)

1.8 (V CC = 1.8V to 3.6V)

Block Write Protection

Protect 1/4, 1/2, or Entire Array

Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection

Self-Timed Write Cycle (5 ms Typical)

High Reliability

Endurance: 100,000 Write Cycles

Data Retention: >40 Years

ESD Protection: >3000V

20-Pin JEDEC SOIC and 8-Pin Leadless Array Package

Description

The AT25P1024 provides 1,048,576 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT25P1024 is available in space saving 20-pin JEDEC SOIC and 8-pin leadless array (LAP) packages.

Pin Configurations

 

Pin Name

Function

 

 

 

 

 

 

 

 

 

 

 

Chip Select

 

CS

 

 

 

 

SCK

Serial Data Clock

 

 

 

 

SI

Serial Data Input

 

 

 

 

SO

Serial Data Output

 

 

 

 

GND

Ground

 

 

 

 

VCC

Power Supply

 

 

 

 

 

 

 

 

 

 

Write Protect

 

WP

 

 

 

 

 

 

 

 

 

Suspends Serial Input

 

HOLD

 

 

 

 

NC

No Connect

 

 

 

 

 

 

(continued)

20-Lead SOIC

 

 

 

 

 

 

 

 

 

 

CS

1

20

 

VCC

 

SO

2

19

 

 

 

 

HOLD

 

 

NC

3

18

 

NC

 

NC

4

17

 

NC

 

NC

5

16

 

NC

 

NC

6

15

 

NC

 

NC

7

14

 

NC

 

NC

8

13

 

NC

 

9

12

 

SCK

 

WP

 

 

GND

10

11

 

SI

 

 

 

 

 

 

 

 

 

8-Pin LAP

VCC 8

1

CS

HOLD 7

2

SO

SCK

6

3

WP

SI

5

4

GND

Bottom View

SPI Serial

EEPROMs

1M (131,072 x 8)

AT25P1024

Preliminary

Rev. 1082C–08/98

1

ATMEL AT25P1024W1-10SI-2.7, AT25P1024W1-10SI-1.8, AT25P1024W1-10SI, AT25P1024W1-10SC-2.7, AT25P1024W1-10SC-1.8 Datasheet

The AT25P1024 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely selftimed, and no separate ERASE cycle is required before WRITE.

BLOCK WRITE protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.

Absolute Maximum Ratings*

Operating Temperature ..................................

-55°C to +125°C

Storage Temperature .....................................

-65°C to +150°C

Voltage on Any Pin

 

with Respect to Ground ....................................

-1.0V to +7.0V

Maximum Operating Voltage...........................................

6.25V

DC Output Current ........................................................

5.0 mA

*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Block Diagram

131,072 x 8

2

AT25P1024

 

 

 

AT25P1024

Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).

 

 

Test Conditions

Max

Units

Conditions

 

 

 

 

 

 

COUT

 

Output Capacitance (SO)

8

pF

VOUT = 0V

CIN

 

Input Capacitance

 

SCK, SI,

 

 

 

 

6

pF

VIN = 0V

(CS,

WP,

HOLD)

Note:

1.

This parameter is characterized and is not 100% tested.

 

 

 

DC Characteristics

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).

Symbol

Parameter

Test Condition

Min

Typ

 

Max

Units

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC1

Supply Voltage

 

 

 

 

 

 

1.8

 

 

3.6

V

VCC2

Supply Voltage

 

 

 

 

 

 

2.7

 

 

5.5

V

VCC3

Supply Voltage

 

 

 

 

 

 

4.5

 

 

5.5

V

ICC1

Supply Current

VCC = 5.0V at 1 MHz, SO = Open Read

 

2.0

 

5.0

mA

ICC2

Supply Current

VCC = 5.0V at 2 MHz, SO = Open Write

 

4.0

 

7.0

mA

ISB1

Standby Current

VCC = 1.8V,

 

 

= VCC

 

0.1

 

3.0

μA

CS

 

ISB2

Standby Current

VCC = 2.7V,

 

 

= VCC

 

0.2

 

3.0

μA

CS

 

ISB3

Standby Current

VCC = 5.0V,

 

 

= VCC

 

2.0

 

7.0

μA

CS

 

IIL

Input Leakage

VIN = 0V to VCC

-3.0

 

 

3.0

μA

IOL

Output Leakage

VIN = 0V to VCC, TAC = 0°C to 70°C

-3.0

 

 

3.0

μA

VIL(1)

Input Low Voltage

 

 

 

 

 

 

-0.6

 

VCC x 0.3

V

V (1)

Input High Voltage

 

 

 

 

 

 

V x 0.7

 

V

CC

+ 0.5

V

IH

 

 

 

 

 

 

 

CC

 

 

 

 

VOL1

Output Low Voltage

4.5V VCC

5.5V

IOL = 3.0 mA

 

 

 

0.4

V

VOH1

Output High Voltage

IOH = -1.6 mA

VCC - 0.8

 

 

 

 

V

 

 

 

 

 

 

 

 

 

VOL2

Output Low Voltage

1.8V VCC

3.6V

IOL = 0.15 mA

 

 

 

0.2

V

VOH2

Output High Voltage

IOH = -100 μA

VCC - 0.2

 

 

 

 

V

 

 

 

 

 

 

 

 

 

Note: 1.

VIL and VIH max are reference only and are not tested.

 

 

 

 

 

 

3

AC Characteristics

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol

Parameter

Voltage

Min

Max

Units

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

0

2.1

 

fSCK

 

SCK Clock Frequency

2.7 - 5.5

0

1.0

MHz

 

 

 

 

 

1.8 - 3.6

0

0.5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

 

2

μs

tRI

 

Input Rise Time

2.7 - 5.5

 

2

 

 

 

 

 

1.8 - 3.6

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

 

2

μs

tFI

 

Input Fall Time

2.7 - 5.5

 

2

 

 

 

 

 

1.8 - 3.6

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

200

 

 

tWH

 

SCK High Time

2.7 - 5.5

400

 

ns

 

 

 

 

 

1.8 - 3.6

800

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

200

 

 

tWL

 

SCK Low Time

2.7 - 5.5

400

 

ns

 

 

 

 

 

1.8 - 3.6

800

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

250

 

 

tCS

 

CS

High Time

2.7 - 5.5

500

 

ns

 

 

 

 

 

1.8 - 3.6

1000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

100

 

 

tCSS

 

CS

Setup Time

2.7 - 5.5

250

 

ns

 

 

 

 

 

1.8 - 3.6

1000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

150

 

 

tCSH

 

CS

Hold Time

2.7 - 5.5

250

 

ns

 

 

 

 

 

1.8 - 3.6

1000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

30

 

 

tSU

 

Data In Setup Time

2.7 - 5.5

50

 

ns

 

 

 

 

 

1.8 - 3.6

100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

50

 

 

tH

 

Data In Hold Time

2.7 - 5.5

50

 

ns

 

 

 

 

 

1.8 - 3.6

100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

100

 

 

tHD

 

Hold

Setup Time

2.7 - 5.5

100

 

ns

 

 

 

 

 

1.8 - 3.6

400

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

200

 

 

tCD

 

Hold

Hold Time

2.7 - 5.5

300

 

ns

 

 

 

 

 

1.8 - 3.6

400

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

0

200

 

tV

 

Output Valid

2.7 - 5.5

0

400

ns

 

 

 

 

 

1.8 - 3.6

0

800

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

0

 

 

tHO

 

Output Hold Time

2.7 - 5.5

0

 

ns

 

 

 

 

 

1.8 - 3.6

0

 

 

 

 

 

 

 

 

 

 

 

4

AT25P1024

 

 

 

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