ATMEL AT25256W-10SI-2.7, AT25256W-10SI-1.8, AT25256W-10SI, AT25256W-10SC-2.7, AT25256W-10SC-1.8 Datasheet

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Features

Serial Peripheral Interface (SPI) Compatible

Supports SPI Modes 0 (0,0) and 3 (1,1)

Low Voltage and Standard Voltage Operation

5.0 (V CC = 4.5V to 5.5V)

2.7 (V CC = 2.7V to 5.5V)

1.8 (V CC = 1.8V to 3.6V)

3 MHz Clock Rate

64-Byte Page Mode and Byte Write Operation

Block Write Protection

Protect 1/4, 1/2, or Entire Array

Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection

Self-Timed Write Cycle (5 ms Typical)

High Reliability

Endurance: 100,000 Write Cycles

Data Retention: >200 Years

ESD Protection: >4000V

Automotive Grade and Extended Temperature Devices Available

8-Pin PDIP, 8-Pin EIAJ SOIC, 8-Pin and 16-Pin JEDEC SOIC, 14-Pin and 20-Pin TSSOP, and 8-Pin Leadless Array Packages

Description

The AT25128/256 provides 131,072/262,144 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The devices are available in

Pin Configurations

 

Pin Name

Function

 

 

 

 

 

 

 

 

 

 

 

Chip Select

 

 

 

 

 

 

CS

 

 

 

 

SCK

Serial Data Clock

 

 

 

 

SI

Serial Data Input

 

 

 

 

SO

Serial Data Output

 

 

 

 

GND

Ground

 

 

 

 

VCC

Power Supply

 

 

 

 

 

 

 

 

 

 

Write Protect

 

WP

 

 

 

 

 

 

 

 

 

Suspends Serial Input

 

HOLD

 

 

 

 

NC

No Connect

 

 

 

 

DC

Don't Connect

 

 

 

 

 

 

14-Lead TSSOP

 

 

 

 

 

 

 

 

 

 

 

 

CS

 

1

14

 

VCC

 

SO

 

2

13

 

 

 

 

 

 

 

HOLD

 

NC

 

3

12

 

NC

 

 

 

NC

 

4

11

 

NC

 

 

 

NC

 

5

10

 

NC

 

 

 

 

 

 

6

9

 

SCK

WP

 

 

GND

 

7

8

 

SI

 

 

 

 

 

 

 

 

 

 

 

 

 

16-Pin SOIC

 

 

 

 

 

 

 

 

 

 

 

 

CS

 

1

16

 

VCC

 

SO

 

2

15

 

 

 

 

 

 

 

HOLD

 

NC

 

3

14

 

NC

 

 

 

NC

 

4

13

 

NC

 

 

 

NC

 

5

12

 

NC

 

 

 

NC

 

6

11

 

NC

 

 

 

 

 

 

 

7

10

 

SCK

 

WP

 

 

GND

 

8

9

 

SI

 

 

 

 

 

 

 

 

 

 

 

(continued)

20-Lead TSSOP*

 

NC

1

20

 

NC

 

 

 

 

 

2

19

 

VCC

 

 

CS

 

SO

3

18

 

 

 

 

 

HOLD

 

SO

4

17

 

 

 

 

HOLD

 

NC

5

16

 

NC

 

NC

6

15

 

NC

 

 

 

7

14

 

SCK

WP

GND

8

13

 

SI

 

DC

9

12

 

DC

 

NC

10

11

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8-Pin PDIP

 

 

 

 

 

 

8-Pin SOIC

 

 

8-Pin Leadless Array

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CS

 

CS

 

1

8

 

VCC

 

CS

 

1

8

 

VCC

8

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HOLD

 

 

 

 

SO

 

SO

 

2

7

 

 

 

 

SO

 

2

7

 

 

 

7

2

 

 

 

HOLD

 

 

 

HOLD

 

 

 

 

 

 

 

SCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WP

 

 

 

 

 

 

3

6

 

SCK

 

 

 

 

 

3

6

 

SCK

6

3

WP

 

 

WP

 

 

 

 

 

 

 

SI

 

 

 

GND

GND

 

4

5

 

SI

GND

 

4

5

 

SI

 

5

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bottom View

*Note: Pins 3, 4 and 17, 18 are internally connected for 14-lead TSSOP socket compatibility.

SPI Serial

EEPROMs

128K (16,384 x 8)

256K (32,768 x 8)

AT25128

AT25256

Rev. 0872E–08/98

1

ATMEL AT25256W-10SI-2.7, AT25256W-10SI-1.8, AT25256W-10SI, AT25256W-10SC-2.7, AT25256W-10SC-1.8 Datasheet

space saving 8-pin PDIP (AT25128/256), 8-pin EIAJ SOIC (AT25128/256), 8-pin and 16-pin JEDEC SOIC (AT25128), 14-pin TSSOP (AT25128), 20-pin TSSOP (AT25128/256), and 8-pin Leadless Array (AT25128/256) packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

The AT25128/256 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely selftimed, and no separate ERASE cycle is required before WRITE.

BLOCK WRITE protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status regis-

ter. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.

Absolute Maximum Ratings*

Operating Temperature ..................................

-55°C to +125°C

Storage Temperature .....................................

-65°C to +150°C

Voltage on Any Pin

 

with Respect to Ground ....................................

-1.0V to +7.0V

Maximum Operating Voltage...........................................

6.25V

DC Output Current ........................................................

5.0 mA

*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Block Diagram

16384/32768 x 8

2 AT25128/256

AT25128/256

Pin Capacitance

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).

 

 

Test Conditions

Max

Units

Conditions

 

 

 

 

 

 

COUT

 

Output Capacitance (SO)

8

pF

VOUT = 0V

CIN

 

Input Capacitance

 

SCK, SI,

 

 

 

 

6

pF

VIN = 0V

(CS,

WP,

HOLD)

Note:

1. This parameter is characterized and is not 100% tested.

 

 

 

DC Characteristics

Applicable over recommended operating range from TAI = -40°C to +85°C, V CC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V(unless otherwise noted).

Symbol

Parameter

Test Condition

Min

Typ

 

Max

Units

 

 

 

 

 

 

 

 

 

 

 

VCC1

Supply Voltage

 

 

 

 

1.8

 

 

3.6

V

VCC2

Supply Voltage

 

 

 

 

2.7

 

 

5.5

V

VCC3

Supply Voltage

 

 

 

 

4.5

 

 

5.5

V

ICC1

Supply Current

VCC = 5.0V at 1 MHz, SO = Open, Read

 

2.0

 

3.0

mA

ICC2

Supply Current

VCC = 5.0V at 2 MHz, SO = Open, Read, Write

 

3.0

 

5.0

mA

ISB1

Standby Current

VCC = 1.8V,

 

= VCC

 

0.1

 

2.0

μA

CS

 

 

ISB2

Standby Current

VCC = 2.7V,

 

= VCC

 

0.2

 

2.0

μA

CS

 

 

ISB3

Standby Current

VCC = 5.0V,

 

= VCC

 

2.0

 

5.0

μA

CS

 

 

IIL

Input Leakage

VIN = 0V to VCC

-3.0

 

 

3.0

μA

IOL

Output Leakage

VIN = 0V to VCC, TAC = 0°C to 70°C

-3.0

 

 

3.0

μA

V (1)

Input Low Voltage

 

 

 

 

-1.0

 

V

CC

x 0.3

V

IL

 

 

 

 

 

 

 

 

 

 

VIH(1)

Input High Voltage

 

 

 

 

VCC x 0.7

 

VCC + 0.5

V

VOL1

Output Low Voltage

4.5 VCC 5.5V

IOL = 3.0 mA

 

 

 

0.4

V

VOH1

Output High Voltage

IOH = -1.6 mA

vCC - 0.8

 

 

 

 

V

 

 

 

 

 

 

 

VOL2

Output Low Voltage

1.8VVCC 3.6V

IOL = 0.15mA

 

 

 

0.2

V

VOH2

Output High Voltage

IOH = -100μA

VCC - 0.2

 

 

 

 

V

 

 

 

 

 

 

 

Note: 1.

VIL and VIH max are reference only and are not tested.

 

 

 

 

 

 

3

AC Characteristics

Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol

Parameter

Voltage

Min

Max

Units

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

0

3.0

 

fSCK

 

SCK Clock Frequency

2.7 - 5.5

0

2.1

MHz

 

 

 

 

 

1.8 - 3.6

0

0.5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

 

2

μs

tRI

 

Input Rise Time

2.7 - 5.5

 

2

 

 

 

 

 

1.8 - 3.6

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

 

2

μs

tFI

 

Input Fall Time

2.7 - 5.5

 

2

 

 

 

 

 

1.8 - 3.6

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

150

 

 

tWH

 

SCK High Time

2.7 - 5.5

200

 

ns

 

 

 

 

 

1.8 - 3.6

800

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

150

 

 

tWL

 

SCK Low Time

2.7 - 5.5

200

 

ns

 

 

 

 

 

1.8 - 3.6

800

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

250

 

 

tCS

 

CS

High Time

2.7 - 5.5

250

 

ns

 

 

 

 

 

1.8 - 3.6

1000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

100

 

 

tCSS

 

CS

Setup Time

2.7 - 5.5

250

 

ns

 

 

 

 

 

1.8 - 3.6

1000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

150

 

 

tCSH

 

CS

Hold Time

2.7 - 5.5

250

 

ns

 

 

 

 

 

1.8 - 3.6

1000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

30

 

 

tSU

 

Data In Setup Time

2.7 - 5.5

50

 

ns

 

 

 

 

 

1.8 - 3.6

100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

50

 

 

tH

 

Data In Hold Time

2.7 - 5.5

50

 

ns

 

 

 

 

 

1.8 - 3.6

100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

100

 

 

tHD

 

Hold

Setup Time

2.7 - 5.5

100

 

ns

 

 

 

 

 

1.8 - 3.6

400

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

200

 

 

tCD

 

Hold

Hold Time

2.7 - 5.5

300

 

ns

 

 

 

 

 

1.8 - 3.6

400

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

0

150

 

tV

 

Output Valid

2.7 - 5.5

0

200

ns

 

 

 

 

 

1.8 - 3.6

0

800

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

0

 

 

tHO

 

Output Hold Time

2.7 - 5.5

0

 

ns

 

 

 

 

 

1.8 - 3.6

0

 

 

 

 

 

 

 

 

 

 

 

4 AT25128/256

AT25128/256

AC Characteristics (Continued)

Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol

Parameter

Voltage

Min

Max

Units

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

0

100

 

tLZ

 

Hold

to Output Low Z

2.7 - 5.5

0

200

ns

 

 

 

 

1.8 - 3.6

0

300

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

 

100

 

tHZ

 

Hold

to Output High Z

2.7 - 5.5

 

200

ns

 

 

 

 

1.8 - 3.6

 

300

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

 

200

 

tDIS

 

Output Disable Time

2.7 - 5.5

 

250

ns

 

 

 

 

1.8 - 3.6

 

1000

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5 - 5.5

 

5

 

tWC

 

Write Cycle Time

2.7 - 5.5

 

10

ms

 

 

 

 

1.8 - 3.6

 

10

 

 

 

 

 

 

 

 

 

Endurance(1)

 

5.0V, 25°C, Page Mode

 

100K

 

Write

 

 

 

Cycles

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.

 

 

5

Serial Interface Description

MASTER: The device that generates the serial clock.

SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25128/256 always operates as a slave.

TRANSMITTER/RECEIVER: The AT25128/256 has separate pins designated for data transmission (SO) and reception (SI).

MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.

SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed.

INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25128/256, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication.

CHIP SELECT: The AT25128/256 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.

HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128/256. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.

WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the

WPEN bit in the status register is “0”. This will allow the user to install the AT25128/256 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”.

SPI Serial Interface

AT25128/256

6 AT25128/256

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