ATMEL AT24CS256W-10SI-2.7, AT24CS256W-10SI-1.8, AT24CS256W-10SI, AT24CS256W-10SC-2.7, AT24CS256W-10SC-1.8 Datasheet

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Features

One-Time Programmable (OTP) Feature

Low-Voltage and Standard-Voltage Operation

5.0 (V CC = 4.5V to 5.5V)

2.7 (V CC = 2.7V to 5.5V)

1.8 (V CC = 1.8V to 3.6V)

Internally Organized 16,384 x 8 and 32,768 x 8

2-Wire Serial Interface

Schmitt Trigger, Filtered Inputs for Noise Suppression

Bidirectional Data Transfer Protocol

1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility

Write Protect Pin for Hardware and Software Data Protection

64-Byte Page Write Mode (Partial Page Writes Allowed)

Self-Timed Write Cycle (5 ms typical)

High Reliability

Endurance: 100,000 Write Cycles

Data Retention: 40 Years

ESD Protection: >4000V

Automotive Grade and Extended Temperature Devices Available

8-Pin JEDEC PDIP and 8-Pin JEDEC and EIAJ SOIC Packages

Description

The AT24CS128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device’s cascadable feature allows up to 4 devices to share a common 2-wire bus. The device also features a one-time programmable 2048 bit array, which once enabled, becomes read-only and cannot be overwritten. If not enabled, the OTP section will function as part of the normal memory array. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The devices are available in space-saving 8-pin JEDEC PDIP (AT24CS128/256), 8-pin EIAJ (AT24CS128/256), 8-pin JEDEC SOIC (AT24CS128) packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Pin Configurations

 

 

 

 

 

8-Pin PDIP

 

 

 

 

 

 

 

 

 

 

 

Pin Name

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

 

 

1

8

 

 

VCC

 

 

 

 

 

 

 

A0 to A2

Address Inputs

 

 

 

 

 

 

A1

 

 

2

7

 

 

WP

 

 

 

 

 

 

 

SDA

Serial Data

 

 

A2

 

 

3

6

 

 

SCL

 

 

 

 

 

 

 

GND

 

 

4

5

 

 

SDA

SCL

Serial Clock Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WP

Write Protect

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8-Pin SOIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

 

 

1

8

 

 

 

VCC

 

 

 

 

 

 

 

 

 

A1

 

 

2

7

 

 

 

WP

 

 

 

 

 

 

 

 

 

A2

 

 

3

6

 

 

 

SCL

 

 

 

 

 

 

 

 

 

GND

 

 

4

5

 

 

 

SDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2-Wire Serial

EEPROMs

with Permanent

Software Write

Protect

128K (16,384 x 8)

256K (32,768 x 8)

AT24CS128

AT24CS256

with Permanent

Software Write

Protect

Advanced

Information

Rev. 1152A–09/98

1

ATMEL AT24CS256W-10SI-2.7, AT24CS256W-10SI-1.8, AT24CS256W-10SI, AT24CS256W-10SC-2.7, AT24CS256W-10SC-1.8 Datasheet

Absolute Maximum Ratings*

..................................Operating Temperature

-55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

 

 

Maximum Ratings” may cause permanent dam-

Storage Temperature .....................................

-65°C to +150°C

age to the device. This is a stress rating only and

 

 

functional operation of the device at these or any

Voltage on Any Pin

 

other conditions beyond those indicated in the

with Respect to Ground .....................................

-1.0V to +7.0V

operational sections of this specification is not

Maximum Operating Voltage

6.25V

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

DC Output Current

5.0 mA

reliability.

 

 

 

 

Block Diagram

A2

Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with AT24C32/64. When the pins are hardwired, as many as four 128K/256K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). When the pins are not hardwired, the

default A1 and A0 are zero. The A2 device address input is a “don’t care” input.

WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP to VCC prior to a write operation creates a software write protect function.

Memory Organization

AT24CS128/256, 128K/256K SERIAL EEPROM: The 128K/256K is internally organized as 256/512 pages of 64bytes each. Random word addressing requires a 14/15-bit data word address.

2 AT24CS128/256

AT24CS128/256

Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.

Symbol

Test Condition

Max

Units

Conditions

 

 

 

 

 

CI/O

Input/Output Capacitance (SDA)

8

pF

VI/O = 0V

CIN

Input Capacitance (A0, A1, SCL)

6

pF

VIN = 0V

Note: This parameter is characterized and is not 100% tested.

DC Characteristics

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).

Symbol

Parameter

 

Test Condition

 

Min

Typ

 

Max

Units

 

 

 

 

 

 

 

 

 

 

 

VCC1

 

Supply Voltage

 

 

 

1.8

 

 

3.6

V

VCC2

 

Supply Voltage

 

 

 

2.7

 

 

5.5

V

VCC3

 

Supply Voltage

 

 

 

4.5

 

 

5.5

V

ICC1

 

Supply Current

VCC = 5.0V

READ at 400 kHz

 

 

 

1.0

 

2.0

mA

ICC2

 

Supply Current

VCC = 5.0V

WRITE at 400 kHz

 

 

 

2.0

 

3.0

mA

ISB1

 

Standby Current

VCC = 1.8V

VIN = VCC or VSS

 

 

 

 

 

0.2

μA

 

(1.8V option)

VCC = 3.6V

 

 

 

 

 

2.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB2

 

Standby Current

VCC = 2.7V

VIN = VCC or VSS

 

 

 

 

 

0.5

μA

 

(2.7V option)

VCC = 5.5V

 

 

 

 

 

5.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB3

 

Standby Current

VCC = 4.5 - 5.5V

VIN = VCC or VSS

 

 

 

 

 

5.0

μA

 

(5.0V option)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ILI

 

Input Leakage Current

 

VIN = VCC or VSS

 

 

 

0.10

 

3.0

μA

ILO

 

Output Leakage Current

 

VOUT = VCC or VSS

 

 

 

0.05

 

3.0

μA

VIL

 

Input Low Level(Note:)

 

 

 

-0.6

 

VCC x 0.3

V

V

IH

 

Input High Level(Note:)

 

 

V

CC

x 0.7

 

V

+ 0.5

V

 

 

 

 

 

 

 

 

CC

 

VOL2

 

Output Low Level

VCC = 3.0V

IOL = 2.1 mA

 

 

 

 

 

0.4

V

VOL1

 

Output Low Level

VCC = 1.8V

IOL = 0.15 mA

 

 

 

 

 

0.2

V

Note:

VIL min and VIH max are reference only and are not tested

 

 

 

 

 

 

3

AC Characteristics

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.

 

 

 

1.8-volt

2.7-volt

5.0-volt

 

Symbol

Parameter

 

 

 

 

 

 

 

Units

 

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

fSCL

Clock Frequency, SCL

 

 

400

 

1000

 

1000

kHz

tLOW

Clock Pulse Width Low

 

1.3

 

0.6

 

0.6

 

μs

tHIGH

Clock Pulse Width High

 

1.0

 

0.4

 

0.4

 

μs

tAA

Clock Low to Data Out Valid

 

0.1

0.9

0.05

0.55

0.05

0.55

μs

tBUF

Time the bus must be free before a new

 

1.2

 

0.5

 

0.5

 

μs

transmission can start(1)

 

 

 

 

tHD.STA

Start Hold Time

 

0.6

 

0.25

 

0.25

 

μs

tSU.STA

Start Set-up Time

 

0.6

 

0.25

 

0.25

 

μs

tHD.DAT

Data In Hold Time

 

0

 

0

 

0

 

μs

tSU.DAT

Data In Set-up Time

 

100

 

100

 

100

 

ns

tR

Inputs Rise Time(1)

 

 

0.3

 

0.3

 

0.3

μs

tF

Inputs Fall Time(1)

 

 

300

 

100

 

100

ns

tSU.STO

Stop Set-up Time

 

0.6

 

0.25

 

0.25

 

μs

tDH

Data Out Hold Time

 

50

 

50

 

50

 

ns

tWR

Write Cycle Time

 

 

20

 

10

 

10

ms

Endurance(1)

5.0V, 25°C, Page Mode

 

100K

 

100K

 

100K

 

Write

 

 

 

 

Cycles

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes: 1. This parameter is characterized and is not 100% tested.

 

 

 

 

 

 

 

2.AC measurement conditions:

RL (connects to VCC): 1.3KΩ (2.7V, 5V), 10KΩ (1.8V)

Input pulse voltages: 0.3VCC to 0.7VCC Input rise and fall times: 50ns

Input and output timing reference voltages: 0.5VCC

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.

STANDBY MODE: The AT24CS128/256 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.

4 AT24CS128/256

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