ATMEL AT24C64W-10SI-2.7, AT24C64W-10SI-2.5, AT24C64W-10SI-1.8, AT24C64N-10SC-2.5, AT24C64N-10SC-1.8 Datasheet

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Features

Low-Voltage and Standard-Voltage Operation

5.0 (V CC = 4.5V to 5.5V)

2.7 (V CC = 2.7V to 5.5V)

2.5 (V CC = 2.5V to 5.5V)

1.8 (V CC = 1.8V to 5.5V)

Low-Power Devices (ISB = 2 μA @ 5.5V) Available

Internally Organized 4096 x 8, 8192 x 8

2-Wire Serial Interface

Schmitt Trigger, Filtered Inputs for Noise Suppression

Bidirectional Data Transfer Protocol

100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility

Write Protect Pin for Hardware Data Protection

32-Byte Page Write Mode (Partial Page Writes Allowed)

Self-Timed Write Cycle (10 ms max)

High Reliability

Endurance: 1 Million Write Cycles

Data Retention: 100 Years

ESD Protection: >3,000V

Automotive Grade and Extended Temperature Devices Available

8-Pin JEDEC PDIP, 8-Pin and 14-Pin JEDEC SOIC, 8-Pin EIAJ SOIC, and 8-pin TSSOP Packages

Description

The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device’s cascadable feature allows up to 8 devices to share a common 2- wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C32/64 is available in space saving 8-pin JEDEC PDIP, 8-pin and 14-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin TSSOP packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

8-Pin PDIP

Pin Configurations

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

 

 

1

8

 

 

VCC

Pin Name

Function

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

2

7

 

 

WP

 

 

 

 

 

 

 

 

 

 

 

 

 

A0 to A2

Address Inputs

 

 

 

 

 

 

A2

 

 

3

6

 

 

SCL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

4

5

 

 

SDA

SDA

 

Serial Data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCL

 

Serial Clock Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8-Pin TSSOP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WP

 

Write Protect

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

1

8

 

 

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

2

7

 

 

 

WP

 

 

14-Pin SOIC

 

 

A2

3

6

 

 

 

SCL

 

 

 

 

 

 

 

GND

4

5

 

 

 

SDA

NC

 

1

14

 

NC

 

 

 

 

 

 

 

 

8-Pin SOIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

 

2

13

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

3

12

 

WP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

4

11

 

NC

A0

 

 

 

 

1

8

 

 

 

 

VCC

 

 

 

 

 

 

 

 

 

 

A2

 

5

10

 

SCL

A1

 

 

 

 

2

7

 

 

 

 

WP

 

 

 

 

 

 

 

 

 

 

GND

 

6

9

 

SDA

A2

 

 

 

 

3

6

 

 

 

 

SCL

 

 

 

 

 

 

 

 

 

 

NC

 

7

8

 

NC

GND

 

 

 

 

4

5

 

 

 

 

SDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2-Wire

Serial EEPROM

32K (4096 x 8)

64K (8192 x 8)

AT24C32

AT24C64

Rev. 0336F–08/98

1

Absolute Maximum Ratings*

Operating Temperature

°

°

*NOTICE: Stresses beyond those listed under “Absolute

-55 C to +125 C

Maximum Ratings” may cause permanent dam-

 

 

 

Storage Temperature .....................................

-65°C to +150°C

age to the device. This is a stress rating only and

 

 

 

functional operation of the device at these or any

Voltage on Any Pin

 

 

other conditions beyond those indicated in the

with Respect to Ground .....................................

-1.0V to +7.0V

operational sections of this specification is not

Maximum Operating Voltage

 

6.25V

implied. Exposure to absolute maximum rating

 

conditions for extended periods may affect

DC Output Current

 

5.0 mA

device reliability.

 

 

 

 

 

 

Block Diagram

Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired or left not connected for hardware compatibility with AT24C16. When the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail under the

Device Addressing section). When the pins are not hardwired, the default A2, A1, and A0 are zero.

WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied high to VCC, all write operations to the upper quandrant (8/16K bits) of memory are inhibited. If left unconnected, WP is internally pulled down to GND.

Memory Organization

AT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as 256 pages of 32 bytes each. Random word addressing requires a 12/13 bit data word address.

2

AT24C32/64

 

 

 

AT24C32/64

Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.

Symbol

 

Test Condition

Max

Units

Conditions

 

 

 

 

 

 

CI/O

 

Input/Output Capacitance (SDA)

8

pF

VI/O = 0V

CIN

 

Input Capacitance (A0, A1, A2, SCL)

6

pF

VIN = 0V

Note: 1.

This parameter is characterized and is not 100% tested.

 

 

 

DC Characteristics

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).

Symbol

Parameter

 

 

Test Condition

Min

Typ

 

Max

Units

 

 

 

 

 

 

 

 

 

 

VCC1

Supply Voltage

 

 

 

1.8

 

 

5.5

V

VCC2

Supply Voltage

 

 

 

2.5

 

 

5.5

V

VCC3

Supply Voltage

 

 

 

2.7

 

 

5.5

V

VCC4

Supply Voltage

 

 

 

4.5

 

 

5.5

V

ICC1

Supply Current VCC = 5.0V

 

 

READ at 100 kHz

 

0.4

 

1.0

mA

ICC2

Supply Current VCC = 5.0V

 

 

WRITE at 100 kHz

 

2.0

 

3.0

mA

ISB1

Standby Current

VCC = 1.8V

VIN = VCC or VSS

 

 

 

0.1

μA

(1.8V option)

VCC

= 5.5V

 

 

 

2.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB2

Standby Current

VCC = 2.5V

VIN = VCC or VSS

 

 

 

0.5

μA

(2.5V option)

VCC

= 5.5V

 

 

 

2.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB3

Standby Current

VCC = 2.7V

VIN = VCC or VSS

 

 

 

0.5

μA

(2.7V option)

VCC

= 5.5V

 

 

 

2.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB4

Standby Current

VCC

= 4.5 - 5.5V

VIN = VCC or VSS

 

20

 

35

μA

(5V option)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ILI

Input Leakage Current

 

 

VIN = VCC or VSS

 

0.10

 

3.0

μA

ILO

Output Leakage Current

 

 

VOUT = VCC or VSS

 

0.05

 

3.0

μA

V

Input Low Level(1)

 

 

 

-0.6

 

V

CC

x 0.3

V

IL

 

 

 

 

 

 

 

 

 

VIH

Input High Level(1)

 

 

 

VCC x 0.7

 

VCC + 0.5

V

VOL2

Output Low Level VCC = 3.0V

 

 

IOL = 2.1 mA

 

 

 

0.4

V

VOL1

Output Low Level VCC = 1.8V

 

 

IOL = 0.15 mA

 

 

 

0.2

V

Notes: 1. VIL min and VIH max are reference only and are not tested.

3

AC Characteristics

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).

 

 

 

1.8-volt

2.7-, 2.5-volt

5.0-volt

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

 

Min

Max

Min

Max

Min

Max

Units

 

 

 

 

 

 

 

 

 

 

fSCL

Clock Frequency, SCL

 

 

100

 

100

 

400

kHz

tLOW

Clock Pulse Width Low

 

4.7

 

4.7

 

1.2

 

μs

tHIGH

Clock Pulse Width High

 

4.0

 

4.0

 

0.6

 

μs

tI

Noise Suppression Time(1)

 

 

100

 

100

 

50

ns

tAA

Clock Low to Data Out Valid

 

0.1

4.5

0.1

4.5

0.1

0.9

μs

tBUF

Time the bus must be free

(1)

4.7

 

4.7

 

1.2

 

μs

before a new transmission can start

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHD.STA

Start Hold Time

 

4.0

 

4.0

 

0.6

 

μs

tSU.STA

Start Set-up Time

 

4.7

 

4.7

 

0.6

 

μs

tHD.DAT

Data In Hold Time

 

0

 

0

 

0

 

μs

tSU.DAT

Data In Set-up Time

 

200

 

200

 

100

 

ns

tR

Inputs Rise Time(1)

 

 

1.0

 

1.0

 

0.3

μs

tF

Inputs Fall Time(1)

 

 

300

 

300

 

300

ns

tSU.STO

Stop Set-up Time

 

4.7

 

4.7

 

0.6

 

μs

tDH

Data Out Hold Time

 

100

 

100

 

50

 

ns

tWR

Write Cycle Time

 

 

20

 

10

 

10

ms

Endurance(1)

5.0V, 25°C, Page Mode

 

1M

 

1M

 

1M

 

Write Cycles

Note: 1. This parameter is characterized and is not 100% tested.

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.

STANDBY MODE: The AT24C32/64 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.

4

AT24C32/64

 

 

 

ATMEL AT24C64W-10SI-2.7, AT24C64W-10SI-2.5, AT24C64W-10SI-1.8, AT24C64N-10SC-2.5, AT24C64N-10SC-1.8 Datasheet

AT24C32/64

Bus Timing

SCL: Serial Clock, SDA: Serial Data I/O

Write Cycle Timing

SCL: Serial Clock, SDA: Serial Data I/O

tWR(1)

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

5

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