Features
•Low-Voltage and Standard-Voltage Operation
–5.0 (V CC = 4.5V to 5.5V)
–2.7 (V CC = 2.7V to 5.5V)
–2.5 (V CC = 2.5V to 5.5V)
–1.8 (V CC = 1.8V to 5.5V)
•Low-Power Devices (ISB = 2 μA @ 5.5V) Available
•Internally Organized 4096 x 8, 8192 x 8
•2-Wire Serial Interface
•Schmitt Trigger, Filtered Inputs for Noise Suppression
•Bidirectional Data Transfer Protocol
•100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
•Write Protect Pin for Hardware Data Protection
•32-Byte Page Write Mode (Partial Page Writes Allowed)
•Self-Timed Write Cycle (10 ms max)
•High Reliability
–Endurance: 1 Million Write Cycles
–Data Retention: 100 Years
–ESD Protection: >3,000V
•Automotive Grade and Extended Temperature Devices Available
•8-Pin JEDEC PDIP, 8-Pin and 14-Pin JEDEC SOIC, 8-Pin EIAJ SOIC, and 8-pin TSSOP Packages
Description
The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device’s cascadable feature allows up to 8 devices to share a common 2- wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C32/64 is available in space saving 8-pin JEDEC PDIP, 8-pin and 14-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin TSSOP packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
8-Pin PDIP
Pin Configurations |
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A0 |
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1 |
8 |
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VCC |
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Pin Name |
Function |
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A1 |
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2 |
7 |
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WP |
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A0 to A2 |
Address Inputs |
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A2 |
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3 |
6 |
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SCL |
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GND |
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4 |
5 |
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SDA |
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SDA |
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Serial Data |
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SCL |
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Serial Clock Input |
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8-Pin TSSOP |
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WP |
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Write Protect |
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A0 |
1 |
8 |
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VCC |
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A1 |
2 |
7 |
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WP |
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14-Pin SOIC |
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A2 |
3 |
6 |
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SCL |
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GND |
4 |
5 |
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SDA |
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NC |
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1 |
14 |
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NC |
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8-Pin SOIC |
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A0 |
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2 |
13 |
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VCC |
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A1 |
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3 |
12 |
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WP |
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NC |
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4 |
11 |
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NC |
A0 |
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1 |
8 |
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VCC |
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A2 |
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5 |
10 |
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SCL |
A1 |
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2 |
7 |
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WP |
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GND |
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6 |
9 |
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SDA |
A2 |
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3 |
6 |
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SCL |
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NC |
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7 |
8 |
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NC |
GND |
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4 |
5 |
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SDA |
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2-Wire |
Serial EEPROM |
32K (4096 x 8) |
64K (8192 x 8) |
AT24C32 |
AT24C64 |
Rev. 0336F–08/98 |
1 |
Absolute Maximum Ratings*
Operating Temperature |
° |
° |
*NOTICE: Stresses beyond those listed under “Absolute |
-55 C to +125 C |
Maximum Ratings” may cause permanent dam- |
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Storage Temperature ..................................... |
-65°C to +150°C |
age to the device. This is a stress rating only and |
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functional operation of the device at these or any |
Voltage on Any Pin |
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other conditions beyond those indicated in the |
with Respect to Ground ..................................... |
-1.0V to +7.0V |
operational sections of this specification is not |
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Maximum Operating Voltage |
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6.25V |
implied. Exposure to absolute maximum rating |
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conditions for extended periods may affect |
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DC Output Current |
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5.0 mA |
device reliability. |
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Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired or left not connected for hardware compatibility with AT24C16. When the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail under the
Device Addressing section). When the pins are not hardwired, the default A2, A1, and A0 are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied high to VCC, all write operations to the upper quandrant (8/16K bits) of memory are inhibited. If left unconnected, WP is internally pulled down to GND.
Memory Organization
AT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as 256 pages of 32 bytes each. Random word addressing requires a 12/13 bit data word address.
2 |
AT24C32/64 |
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AT24C32/64
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol |
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Test Condition |
Max |
Units |
Conditions |
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CI/O |
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Input/Output Capacitance (SDA) |
8 |
pF |
VI/O = 0V |
CIN |
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Input Capacitance (A0, A1, A2, SCL) |
6 |
pF |
VIN = 0V |
Note: 1. |
This parameter is characterized and is not 100% tested. |
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DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol |
Parameter |
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Test Condition |
Min |
Typ |
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Max |
Units |
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VCC1 |
Supply Voltage |
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1.8 |
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5.5 |
V |
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VCC2 |
Supply Voltage |
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2.5 |
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5.5 |
V |
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VCC3 |
Supply Voltage |
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2.7 |
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5.5 |
V |
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VCC4 |
Supply Voltage |
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4.5 |
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5.5 |
V |
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ICC1 |
Supply Current VCC = 5.0V |
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READ at 100 kHz |
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0.4 |
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1.0 |
mA |
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ICC2 |
Supply Current VCC = 5.0V |
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WRITE at 100 kHz |
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2.0 |
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3.0 |
mA |
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ISB1 |
Standby Current |
VCC = 1.8V |
VIN = VCC or VSS |
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0.1 |
μA |
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(1.8V option) |
VCC |
= 5.5V |
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2.0 |
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ISB2 |
Standby Current |
VCC = 2.5V |
VIN = VCC or VSS |
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0.5 |
μA |
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(2.5V option) |
VCC |
= 5.5V |
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2.0 |
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ISB3 |
Standby Current |
VCC = 2.7V |
VIN = VCC or VSS |
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0.5 |
μA |
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(2.7V option) |
VCC |
= 5.5V |
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2.0 |
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ISB4 |
Standby Current |
VCC |
= 4.5 - 5.5V |
VIN = VCC or VSS |
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20 |
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35 |
μA |
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(5V option) |
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ILI |
Input Leakage Current |
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VIN = VCC or VSS |
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0.10 |
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3.0 |
μA |
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ILO |
Output Leakage Current |
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VOUT = VCC or VSS |
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0.05 |
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3.0 |
μA |
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V |
Input Low Level(1) |
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-0.6 |
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V |
CC |
x 0.3 |
V |
IL |
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VIH |
Input High Level(1) |
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VCC x 0.7 |
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VCC + 0.5 |
V |
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VOL2 |
Output Low Level VCC = 3.0V |
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IOL = 2.1 mA |
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0.4 |
V |
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VOL1 |
Output Low Level VCC = 1.8V |
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IOL = 0.15 mA |
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0.2 |
V |
Notes: 1. VIL min and VIH max are reference only and are not tested.
3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
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1.8-volt |
2.7-, 2.5-volt |
5.0-volt |
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Symbol |
Parameter |
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Min |
Max |
Min |
Max |
Min |
Max |
Units |
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fSCL |
Clock Frequency, SCL |
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100 |
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100 |
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400 |
kHz |
tLOW |
Clock Pulse Width Low |
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4.7 |
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4.7 |
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1.2 |
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μs |
tHIGH |
Clock Pulse Width High |
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4.0 |
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4.0 |
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0.6 |
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μs |
tI |
Noise Suppression Time(1) |
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100 |
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100 |
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50 |
ns |
tAA |
Clock Low to Data Out Valid |
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0.1 |
4.5 |
0.1 |
4.5 |
0.1 |
0.9 |
μs |
tBUF |
Time the bus must be free |
(1) |
4.7 |
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4.7 |
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1.2 |
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μs |
before a new transmission can start |
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tHD.STA |
Start Hold Time |
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4.0 |
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4.0 |
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0.6 |
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μs |
tSU.STA |
Start Set-up Time |
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4.7 |
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4.7 |
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0.6 |
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μs |
tHD.DAT |
Data In Hold Time |
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0 |
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0 |
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0 |
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μs |
tSU.DAT |
Data In Set-up Time |
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200 |
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200 |
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100 |
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tR |
Inputs Rise Time(1) |
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1.0 |
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1.0 |
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0.3 |
μs |
tF |
Inputs Fall Time(1) |
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300 |
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300 |
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300 |
ns |
tSU.STO |
Stop Set-up Time |
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4.7 |
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4.7 |
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0.6 |
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μs |
tDH |
Data Out Hold Time |
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100 |
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100 |
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50 |
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ns |
tWR |
Write Cycle Time |
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20 |
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10 |
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10 |
ms |
Endurance(1) |
5.0V, 25°C, Page Mode |
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1M |
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1M |
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1M |
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Write Cycles |
Note: 1. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE: The AT24C32/64 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.
4 |
AT24C32/64 |
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AT24C32/64
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
tWR(1)
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
5