Features
•Low Voltage and Standard Voltage Operation
–5.0 (V CC = 4.5V to 5.5V)
–2.7 (V CC = 2.7V to 5.5V)
–2.5 (V CC = 2.5V to 5.5V)
–1.8 (V CC = 1.8V to 5.5V)
•Internally Organized 2048 x 8 (16K)
•2-Wire Serial Interface
•Schmitt Trigger, Filtered Inputs for Noise Suppression
•Bidirectional Data Transfer Protocol
•100 KHz (1.8V, 2.5V, 2.7V) and 400 KHz (5V) Compatibility
•Write Protect Pin for Hardware Data Protection
•Cascadable Feature Allows for Extended Densities
•16-Byte Page Write Mode
•Partial Page Writes Are Allowed
•Self-Timed Write Cycle (10 ms max)
•High Reliability
–Endurance: 1 Million Write Cycles
–Data Retention: 100 Years
–ESD Protection: >3,000V
•Automotive Grade and Extended Temperature Devices Available
•8-Pin JEDEC SOIC and 8-Pin PDIP Packages
Description
The AT24C164 provides 16,384 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 2048 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C164 is available in space saving 8-pin PDIP and 8-pin SOIC packages and is accessed via a 2-wire serial interface. In addition, this device is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
Pin Configurations
Pin Name |
Function |
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A0 to A2 |
Address Inputs |
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SDA |
Serial Data |
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SCL |
Serial Clock Input |
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WP |
Write Protect |
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8-Pin PDIP |
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A0 |
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1 |
8 |
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VCC |
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A1 |
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2 |
7 |
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WP |
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A2 |
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3 |
6 |
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SCL |
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GND |
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4 |
5 |
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SDA |
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8-Pin SOIC |
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A0 |
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1 |
8 |
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VCC |
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A1 |
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2 |
7 |
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WP |
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A2 |
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3 |
6 |
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SCL |
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GND |
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4 |
5 |
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SDA |
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2-Wire Serial |
EEPROM |
16K (2048 x 8) |
AT24C164 |
Rev. 0105D–07/98 |
1 |
Absolute Maximum Ratings*
Operating Temperature |
° |
° |
*NOTICE: Stresses beyond those listed under “Absolute |
-55 C to +125 C |
Maximum Ratings” may cause permanent dam- |
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Storage Temperature ..................................... |
-65°C to +150°C |
age to the device. This is a stress rating only and |
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functional operation of the device at these or any |
Voltage on Any Pin |
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other conditions beyond those indicated in the |
with Respect to Ground ..................................... |
-1.0V to +7.0V |
operational sections of this specification is not |
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Maximum Operating Voltage |
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6.25V |
implied. Exposure to absolute maximum rating |
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conditions for extended periods may affect device |
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DC Output Current |
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5.0 mA |
reliability. |
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Block Diagram
WP
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.
DEVICE SELECT (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that may be hardwired or actively driven to VDD or VSS. These inputs allow the selection for
one of eight possible devices sharing a common bus. The AT24C164 can be made compatible with the AT24C16 by tying A2, A1 and A0 to VSS. Device addressing is discussed in detail in the device addressing section.
WRITE PROTECT (WP): The write protect input, when tied low to GND, allows normal write operations.
Memory Organization
The AT24C164 is internally organized with 256 pages of 8 bytes each. Random word addressing requires an 11 bit data word address.
2 |
AT24C164 |
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AT24C164 |
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Pin Capacitance(1) |
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Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V. |
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Symbol |
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Test Condition |
Max |
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Units |
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Conditions |
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CI/O |
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Input/Output Capacitance (SDA) |
8 |
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pF |
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VI/O = 0V |
CIN |
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Input Capacitance (A0, A1, A2, SCL) |
6 |
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pF |
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VIN = 0V |
Note: 1. |
This parameter is characterized and is not 100% tested. |
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DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol |
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Parameter |
Test Condition |
Min |
Typ |
Max |
Units |
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VCC1 |
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Supply Voltage |
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1.8 |
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5.5 |
V |
VCC2 |
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Supply Voltage |
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2.5 |
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5.5 |
V |
VCC3 |
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Supply Voltage |
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2.7 |
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5.5 |
V |
VCC4 |
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Supply Voltage |
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4.5 |
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5.5 |
V |
ICC |
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Standby Current VCC = 5.0V |
READ at 100 KHz |
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0.4 |
1.0 |
mA |
ICC |
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Standby Current VCC = 5.0V |
WRITE at 100 KHz |
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2.0 |
3.0 |
mA |
ISB1 |
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Standby Current VCC = 1.8V |
VIN = VCC or VSS |
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0.6 |
3.0 |
μA |
ISB2 |
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Standby Current VCC = 2.5V |
VIN = VCC or VSS |
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1.4 |
4.0 |
μA |
ISB3 |
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Standby Current VCC = 2.7V |
VIN = VCC or VSS |
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1.6 |
4.0 |
μA |
ISB4 |
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Standby Current VCC = 5.0V |
VIN = VCC or VSS |
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8.0 |
18.0 |
μA |
ILI |
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Input Leakage Current |
VIN = VCC or VSS |
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0.10 |
3.0 |
μA |
ILO |
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Output Leakage Current |
VOUT = VCC or VSS |
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0.05 |
3.0 |
μA |
VIL |
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Input Low Level(1) |
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-0.6 |
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VCC x 0.3 |
V |
VIH |
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Input High Level(1) |
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VCC x 0.7 |
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VCC + 0.5 |
V |
VOL2 |
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Output Low Level VCC = 3.0V |
IOL = 2.1 mA |
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0.4 |
V |
VOL1 |
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Output Low Level VCC = 1.8V |
IOL = 0.15 mA |
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0.2 |
V |
Note: 1. |
VIL min and VIH max are reference only and are not tested. |
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3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
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2.7-, 2.5-, 1.8-volt |
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5.0-volt |
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Symbol |
Parameter |
Min |
Max |
Min |
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Max |
Units |
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fSCL |
Clock Frequency, SCL |
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100 |
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400 |
KHz |
tLOW |
Clock Pulse Width Low |
4.7 |
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1.2 |
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μs |
tHIGH |
Clock Pulse Width High |
4.0 |
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0.6 |
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μs |
tI |
Noise Suppression Time(1) |
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100 |
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50 |
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tAA |
Clock Low to Data Out Valid |
0.1 |
4.5 |
0.1 |
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0.9 |
μs |
tBUF |
Time the bus must be free before a new |
4.7 |
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1.2 |
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μs |
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transmission can start(1) |
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tHD.STA |
Start Hold Time |
4.0 |
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0.6 |
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μs |
tSU.STA |
Start Set-up Time |
4.7 |
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0.6 |
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μs |
tHD.DAT |
Data In Hold Time |
0 |
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0 |
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μs |
tSU.DAT |
Data In Set-up Time |
200 |
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100 |
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tR |
Inputs Rise Time(1) |
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1.0 |
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0.3 |
μs |
tF |
Inputs Fall Time(1) |
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300 |
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300 |
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tSU.STO |
Stop Set-up Time |
4.7 |
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0.6 |
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μs |
tDH |
Data Out Hold Time |
100 |
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50 |
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tWR |
Write Cycle Time |
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10 |
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10 |
ms |
Endurance(1) |
5.0V, 25°C, Page Mode |
1M |
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1M |
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Write |
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cycles |
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Notes: 1. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C164 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, the AT24C164 can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.
4 |
AT24C164 |
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