ATMEL AT24C08AN-10SI-2.7, AT24C08AN-10SI-2.5, AT24C08AN-10SI-1.8, AT24C08AN-10SI, AT24C08AN-10SC-2.7 Datasheet

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Features
Write Protect Pin for Hardware Data Protection
– Utilizes Different Array Protection Compared to the AT24C02/04/08
Low Voltage and Standard Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) – 2.5 (VCC = 2.5V to 5.5V) – 1.8 (VCC = 1.8V to 5.5V)
Internally Organized 256 x 8 (2K), 512 x 8 (4K) or 1024 x 8 (8K)
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Supperssion
Bidirectional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
8-Byte Page (2K), 16-Byte Page (4K, 8K) Write Modes
Partial Page Writes Are Allowed
Self-Timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles – Data Retention: 100 Years – ESD Protection: >3000V
Automotive Grade and Extended Temperature Devices Available
8-Pin and 14-Pin JEDEC SOIC, 8-Pin PDIP, and 8-Pin TSSOP Packages
Description
The AT24C02A/04A/08A provides 2048/4096/8192 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 256/512/1024 words of 8 bits each. The device is opti mized for use in many industrial and commer cial applications where low power and low voltage operation are essential. The AT24C02A/04A/08A is av ailable in spa ce sav ing 8-p in PDIP , 8-pin, 14 -pin SOIC, and 8-pin TSSOP package s and is acc essed v ia a 2 -wire ser ial interf ace. In a dditio n, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to
5.5V) and 1.8V (1.8V to 5.5V) versions.
2-Wire Serial EEPROM
2K (256 x 8) 4K (512 x 8) 8K (1024 x 8)
AT24C02A AT24C04A AT24C08A
Rev. 0976B–07/98
Pin Configurations
Pin Name Function
A
0
to A
2
Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NC No Connect
14-Pin SOIC
8-Pin PDIP
8-Pin SOIC
AT24C02A/04A/ 08A
8-Pin TSSOP
AT24C02A/04A/08A
2
Block Diagram
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A2 , A1, A0):
The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C02A. As many as eight 2K devices may be addressed on a single bus system (device address ing is discussed in detail under the Device Addressing section).
The AT24C04A uses the A2 and A1 in puts for hard wir e addressing and a total of four 4K devices may be addressed on a singl e b us sy st em . The A0 pi n is a no c on­nect.
The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects.
WRITE PROTECT (WP):
The AT24C 02A/0 4A/08A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to groun d (GND). Wh en the Write Pr otect
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam­age to the dev ice. Th is is a s tress rating only an d functional oper ati on of the devi ce at t hes e o r any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions f or e xtended periods ma y af fect dev ice reliability .
Storage Temperature..................................... -65°C to +150°C Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage........................................... 6.25V
DC Output Current........................................................5.0 mA
AT24C02A/04A/08A
3
pin is connec ted to V
CC
, the write protection feature is
enabled and operates as shown in the following table.
Memory Organization
AT24C02A, 2K SERIAL EEPROM:
Internally organized with 256 pages of 1-byte each, the 2K requires an 8 bit data word address for random word addressing.
AT24C04A, 4K SERIAL EEPROM:
The 4K is internally organized with 256 pages of 2-bytes each. Rand om word addressing requires a 9 bit data word address.
AT24C08A, 8K SERIAL EEPROM:
The 8K is internally organized with 4 blocks of 256 pages of 4-bytes each. Random word addressing requires a 10 bit data word address.
Note: 1. This parameter is characterized and is not 100% tested.
Note: 1. V
IL
min and VIH max are reference only and are not tested.
WP Pin Status
Part of the Array Protected
24C02A 24C04A 24C08A
At V
CC
Upper Half
(1K) Array
Upper Half
(2K) Array
Full (8K)
Array
At GND Normal Read/Write Operation s
Pin Capacitance
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol Test Condition Max Units Conditions
C
I/O
Input/Output Capacitance (SDA) 8 pF V
I/O
= 0V
C
IN
Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, V
CC
= +1.8V to +5.5V (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
V
CC1
Supply Voltage 1.8 5.5 V
V
CC2
Supply Voltage 2.5 5.5 V
V
CC3
Supply Voltage 2.7 5.5 V
V
CC4
Supply Voltage 4.5 5.5 V
I
Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA
I
Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA
I
SB1
Standby Current VCC = 1.8V VIN = VCC or V
SS
0.6 3.0
µ
A
I
SB2
Standby Current VCC = 2.5V VIN = VCC or V
SS
1.4 4.0
µ
A
I
SB3
Standby Current VCC = 2.7V VIN = VCC or V
SS
1.6 4.0
µ
A
I
SB4
Standby Current VCC = 5.0V VIN = VCC or V
SS
8.0 18.0
µ
A
I
LI
Input Leakage Current VIN = VCC or V
SS
0.10 3.0
µ
A
I
LO
Output Leakage Current V
OUT
= V
CC
or V
SS
0.05 3.0
µ
A
V
IL
Input Low Level
(1)
-0.6 VCC x 0.3 V
V
IH
Input High Level
(1)
VCC x 0.7 VCC + 0.5 V
V
OL2
Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
V
OL1
Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
AT24C02A/04A/08A
4
Note: 1. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is nor­mally pulled high wi th an ex terna l dev ic e. Dat a o n t he SDA pin may chan ge o nly d uri ng S CL l ow t ime per iods (refe r t o Data Validity timing diagram). Data changes during S CL high periods will indicate a start or stop condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing dia­gram).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPR OM in a standb y power mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE:
All address es an d data words a re se ri-
ally transmitted to and from the EEPROM in 8 bit words
.
The EEPROM sends a ze ro to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE:
The AT24C02A/04A/08A features a low power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.
MEMORY RESET:
After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by follow­ing these steps:(a ) Clock up to 9 cycle s, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol Parameter
2.7-, 2.5-, 1.8-volt 5.0-volt UnitsMinMaxMinMax
f
SCL
Clock Frequency, SCL 100 400 kHz
t
LOW
Clock Pulse Width Low 4.7 1.2
µ
s
t
HIGH
Clock Pulse Width High 4.0 0.6
µ
s
t
I
Noise Suppression Time
(1)
100 50 ns
t
AA
Clock Low to Data Out Valid 0.1 4.5 0.1 0.9
µ
s
t
BUF
Time the bus must be free before a new transmission can start
(1)
4.7 1.2
µ
s
t
HD.STA
Start Hold Time 4.0 0.6
µ
s
t
SU.STA
Start Set-up Time 4.7 0.6
µ
s
t
HD.DAT
Data In Hold Time 0 0
µ
s
t
SU.DAT
Data In Set-up Time 200 100 ns
t
R
Inputs Rise Time
(1)
1.0 0.3
µ
s
t
F
Inputs Fall Time
(1)
300 300 ns
t
SU.STO
Stop Set-up Time 4.7 0.6
µ
s
t
Data Out Hold Time 100 50 ns
t
WR
Write Cycle Time 10 10 ms
Endurance
(1)
5.0V, 25°C, Page Mode 1M 1M
Write
Cycles
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