Features
•E2 Programmable 65,536 x 1, 131,072 x 1, and 262,144 x 1 bit Serial Memories Designed To Store Configuration Programs For Programmable Gate Arrays
•Simple Interface to SRAM FPGAs Requires Only One User I/O Pin
•Compatible With AT6000 FPGAs, ATT3000 FPGA, EPF8000 FPGAs, ORCA FPGAs, XC2000, XC3000, XC4000, XC5000 FPGAs, MPA1000
•Cascadable To Support Additional Configurations or Future Higher-density Arrays (17C128 and 17C256 only)
•Low-power CMOS EEPROM Process
•Programmable Reset Polarity
•Available In the Space-efficient Plastic DIP or Surface-mount PLCC and SOIC Packages
•In-System Programmable Via 2-Wire Bus
•Emulation of 24CXX Serial EPROMs
•Available in 3.3V ± 10% LV Version
Description
The AT17C65/128/256 and AT17LV65/128/256 (AT17 Series) FPGA Configuration EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17 Series is packaged in the 8-pin DIP and the popular 20-pin PLCC and SOIC. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a special feature of the AT17 Series, the user can select the polarity of the reset function by programming a special EEPROM bit.
The AT17 Series can be programmed with industry standard programmers.
Pin Configurations
20-pin PLCC |
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20-Pin SOIC |
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8-Pin DIP
AT17 Series
FPGA Configuration E2PROM
65K, 128K and 256K
AT17C65
AT17C128
AT17C256
0391E-A–5/97
1
Controlling The AT17 Series Serial EEPROMs
Most connections between the FPGA device and the Serial EEPROM are simple and self-explanatory.
•The DATA output of the AT17 Series drives DIN of the FPGA devices.
•The master FPGA CCLK output drives the CLK input of the AT17 Series.
•The CEO output of any AT17C/LV128/256 drives the CE input of the next AT17C/LV128/256 in a cascade chain of PROMs.
•SER_EN must be connected to VCC.
There are, however, two different ways to use the inputs CE and OE, as shown in the AC Characteristics waveforms.
Condition 1
The simplest connection is to have the FPGA D/P output drive both CE and RESET/OE in parallel (Figure 1). Due to its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configura-
tion cycle. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the AT17 Series does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configuration cycle.
Condition 2
The FPGA D/P output drives only the CE input of the AT17 Series, while its OE input is driven by the inversion of the input to the FPGA RESET input pin. This connection works under all normal circumstances, even when the user aborts
a configuration before D/P has gone High. A High level on the RESET/OE input to the AT17C/LVxxx – during FPGA reset – clears the Configurator's internal address pointer, so that the reconfiguration starts at the beginning. The AT17 Series does not require an inverter since the RESET polarity is programmable.
Block Diagram
2 |
AT17 Series |
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AT17 Series |
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Pin Configurations |
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PLCC/ |
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SOIC |
DIP |
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Pin |
Pin |
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Name |
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I/O |
Description |
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2 |
1 |
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DATA |
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I/O |
Three-state DATA output for reading. Input/Output pin for programming. |
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4 |
2 |
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CLK |
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I |
Clock input. Used to increment the internal address and bit counter for reading |
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and programming. |
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RESET/Output Enable input (when |
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is High). A Low level on both the |
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SER_EN |
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inputs enables the data output driver. A High level on |
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6 |
3 |
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CE |
and RESET/OE |
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RESET/OE |
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RESET/OE resets both the addresss and bit counters. A logic polarity of this |
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input is programmable as either RESET/OE |
or RESET/OE. This document |
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describes the pin as RESET/OE. |
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8 |
4 |
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I |
Chip Enable input. Used for device selection. A Low level on both |
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and |
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CE |
CE |
OE |
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enables the data output driver. A High level on |
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disables both the address |
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CE |
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and bit counters and forces te device into a low power mode. Note this pin will |
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not enable/disable the device in 2-wire Serial mode (ie; when |
SER_EN |
is Low). |
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10 |
5 |
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GND |
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Ground Pin |
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14 |
6 |
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O |
Chip Enable Out output. This signal is asserted Low on the clock cycle following |
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CEO |
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the last bit read from the memory. It will stay Low as long as CE and |
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are |
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OE |
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both Low. It will then follow |
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until |
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goes High. Thereafter |
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will stay |
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CE |
OE |
CEO |
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High until the entire PROM is read again and senses the status of RESET |
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polarity. |
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A2 |
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I |
Device selection input, A2. This is used to enable (or select) the device during |
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programming and when |
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is Low (see Programming Guide for more |
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SER_EN |
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details). |
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Serial enable is normally high during FPGA loading operations. Bringing |
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17 |
7 |
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SER_EN |
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I |
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SER_EN low, enables the 2-wire serial interface for programming. |
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20 |
8 |
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VCC |
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+3.3V/+5V power supply pin. |
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Absolute Maximum Ratings* |
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*NOTICE: |
Stresses beyond those listed under “Absolute |
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Operating Temperature.........................-55°C to +125°C |
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Maximum Ratings” may cause permanent dam- |
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Storage Temperature............................-65°C to +150°C |
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age to the device. This is a stress rating only and |
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functional operation of the device at these or any |
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Voltage on Any Pin |
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other conditions beyond those indicated in the |
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with Respect to Ground.................... -0.1V to VCC + 0.5V |
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operational sections of this specification is not |
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implied. Exposure to absolute maximum rating |
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Supply Voltage (Vcc) .............................. -0.5 V to +7.0V |
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conditions for extended periods may affect device |
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reliability. |
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Maximum Soldering Temp. (10 sec. @ 1/16 in.)... 260°C |
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ESD (RZAP = 1.5K, CZAP = 100pF) ........................2000V |
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