ATMEL AT17C128A-10JI, AT17C128A-10JC, AT17LV256A-10JI, AT17LV256A-10JC, AT17LV128A-10JI Datasheet

Features

•EE Programmable 65,536 x 1, 131,072 x 1 and 262,144 x 1 bit Serial Memories Designed to Store Configuration Programs for Programmable Gate Arrays

•Simple Interface to SRAM FPGAs Requires Only One User I/O Pin

•Able to Configure with EPF6000 and EPF8000, Flex 10K FPGAs

•Cascadable To Support Additional Configurations or Future Higher-Density Arrays (17C128/256 only)

•Low-Power CMOS EEPROM Process

•Programmable Reset Polarity

•Available in Industry-Standard Pin-Compatible PLCC Package

•In-System Programmable via 2-Wire Bus

•Emulation of 24CXX Serial EEPROMs

•Available in 3.3V and 5V Versions

Description

The AT17C65/128/256A and AT17LV65/128/256A (AT17A Series) FPGA Configuration EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17A Series is packaged in the popular 20-pin PLCC. The AT17A Series family uses a simple serial-access provides to configure one or more FPGA devices. The AT17A Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a special feature of the AT17A Series, the user can select the polarity of the reset function by programming a special EEPROM bit.

The AT17A Series is pin compatible with the industry standard configurator, and can be programmed with industry standard programmers.

Pin Configurations

20-Pin PLCC

						NC	DATA	NC		VCC	NC
					3		2	1	20		19
		CLK (DCLK)			4						18	SER_EN
				NC	5						17	NC
				NC	6						16	NC
				NC	7						15	NC
					8						14	NC
RESET/OE		(RESET/OE)					10	11	12
					9						13
						CE (nCS)	GND	NC		(nCASC)	NC
										CEO

FPGA

Configuration

EEPROM

65K, 128K and 256K

AT17CxxxA

AT17LVxxxA

Rev. 0996A–07/98

1

Controlling The AT17A Series Serial EEPROMs

Most connections between the FPGA device and the serial EEPROM are simple and self-explanatory.

•The DATA output of the AT17A Series drives DIN of the FPGA devices.

•The master FPGA CCLK output drives the CLK input of the AT17A Series.

•The CEO output of any AT17C/LV128/256A drives the CE input of the next AT17C/LV65/128/256 in a cascade chain of PROMs.

•SER_EN must be connected to VCC.

There are, however, two different ways to use the inputs CE and OE, as shown in the AC Characteristics waveforms.

Condition 1

The simplest connection is to have the FPGA D/P output drive both CE and RESET/OE in parallel (Figure 1). Due to its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configura-

tion cycle. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the AT17A Series does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configuration cycle.

Condition 2

The FPGA D/P output drives only the CE input of the AT17A Series, while its OE input is driven by the inversion of the input to the FPGA RESET input pin. This connection works under all normal circumstances, even when the user aborts a configuration before D/P has gone high. A high level on the RESET/OE input to the AT17C/LVxxxA – during FPGA reset – clears the Configurator's internal address pointer, so that the reconfiguration starts at the beginning. The AT17A Series does not require an inverter since the RESET polarity is programmable.

Block Diagram

2	AT17A Series

AT17A Series

Pin Configurations

PLCC/S

OIC

DIP

Pin

Pin

Name

I/O

Description

2

1

DATA

I/O

Three-state DATA output for reading. Input/Output pin for programming.

4

2

CLK

I

Clock input. Used to increment the internal address and bit counter for reading and

programming.

8

3

RESET/OE

RESET/Output Enable input (when SER_EN is High). A low level on both the CE and

RESET/OE

inputs enables the data output driver. A high level on RESET/OE resets both

the address and bit counters. A logic polarity of this input is programmable as either

RESET/OE

or RESET/OE. This document describes the pin as RESET/OE.

9

4

I

Chip Enable input. Used for device selection. A low level on both

and

enables the

CE

CE

OE

data output driver. A high level on

CE

disables both the address and bit counters and

forces te device into a low-power mode. Note this pin will not enable/disable the device in

2-wire serial mode (ie; when

is low).

SER_EN

10

5

GND

Ground pin

12

6

CEO

O

Chip Enable Out output. This signal is asserted low on the clock cycle following the last

bit read from the memory. It will stay low as long as CE and

OE

are both low. It will then

follow

CE

until

OE

goes high. Thereafter,

CEO

will stay high until the entire PROM is

read again and senses the status of RESET polarity.

A2

I

Device selection input, A2. This is used to enable (or select) the device during

programming and when

SER_EN

is low (see Programming Guide for more details).

18

7

I

Serial enable is normally high during FPGA loading operations. Bringing

low,

SER_EN

SER_EN

enables the 2-wire serial interface for programming.

20

8

VCC

+3.3V/+5V power supply pin.

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Operating Temperature ..................................

-55°C to +125°C

Maximum Ratings” may cause permanent dam-

Storage Temperature

.....................................

-65°C to +150°C

age to the device. This is a stress rating only and

functional operation of the device at these or any

Voltage on Any Pin

other conditions beyond those indicated in the

with Respect to Ground .............................

-0.1V to VCC + 0.5V

operational sections of this specification is not

Supply Voltage (VCC)

-0.5 V to + 7.0V

implied. Exposure to absolute maximum rating

.......................................

conditions for extended periods may affect device

Maximum Soldering Temp. (10 sec. @ 1/16 in.)

260°C

reliability.

ESD (RZAP = 1.5K, CZAP = 100 pF).................................

2000V

3

FPGA Master Serial Mode Summary

The I/O and logic functions of the FPGA and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The Serial Configuration EEPROM has been designed for compatibility with the Master Serial Mode.

Cascading Serial Configuration

EEPROMs (AT17C/LV256A)

For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded Configurator s pr ov ide additional memory (17C/LV128/256A only).

After the last bit from the first Configurator is read, the next clock signal to the Configurator asserts its CEO output Low and disables its DATA line. The second Configurator recognizes the low level on its CE input and enables its DATA output.

Figure 1. Condition 1 Connection

	M2	REBOOT
	M1	FLEX 10K, FLEX 16K
	M0
		(CLK REQUIRED)
		SERIAL
	FPGA	EEPROM
	D0	DATA	VCC
	CCLK	CLK
	CS	CE	SER_EN
	CON	RESET/OE
	FLEX DEVICE	AT17CXX

After configuration is complete, the address counters of all cascaded Configurators are reset if the reset signal drives the RESET/OE on each Configurator Active.

If the address counters are not to be reset upon completion, then the RESET/OE inputs can be tied to ground. For more details, please reference the AT17C Series Programming Guide

Programming Mode

The programming mode is entered by bringing SER_EN low. In this mode the chip can be programmed by the 2- wire interface. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. See the Programming Specification for Atmel’s Configuration Memories Application Note for further information. The AT17C Series parts are read/write at 5V nominal. The AT17LV parts are read/write at 3.0V nominal.

AT17C/LVxxx Reset Polarity

The AT17C/LVxxxA lets the user choose the reset polarity as either RESET/OE or RESET/OE.

Standby Mode

The AT17C/LVxxxA enters a low-power standby mode

whenever CE is asserted high. In this mode, the Configurator consumes less than 1.0 mA of current. The output remains in a high-impedance state regardless of the state

of the OE input.

Operating Conditions

			AT17Cxxx	AT17LVxxx
Symbol	Description		Min/Max	Min/Max	Units
VCC	Commercial	Supply voltage relative to GND	4.75/5.25	3.0/3.6	V
		-0°C to +70°C
	Industrial	Supply voltage relative to GND	4.5/5.5	3.0/3.6	V
		-40°C to +85C°
	Military	Supply voltage relative to GND	4.5/5.5	3.0/3.6	V
		-55°C to +125C

4	AT17A Series