ATMEL AT17LV512A-10JI, AT17LV512A-10JC, AT17C010A-10JI, AT17C010A-10JC, AT17LV010A-10JI Datasheet

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Features

Serial EEPROM Family for Configuring Altera FLEXâ 10K Devices

Simple, Easy-to-use 4-pin Interface

E2 Programmable 1M Bit Serial Memories Designed To Store Configuration Programs For Programmable Gate Arrays

Cascadable To Support Additional Configurations or Future Higher-density Arrays

Low-power CMOS EEPROM Process

Programmable Reset Polarity

Available in the Space-efficient Surface-mount PLCC Package

In-System Programmable Via 2-Wire Bus

Emulation of 24CXX Serial EPROMs

Available in 3.3V ± 10% LV and 5V ± 5% C Versions

Description

The AT17C512/010A and AT17LV512/010A (AT17A Series) FPGA Configuration EEPROMs (Configurators) provide and easy-to-use, cost-effective configuration memory for programming Altera FLEX Field Programmable Gate Arrays, FPGA, (the “devices”). The AT17A Series is packaged in the popular 20-pin PLCC package. The AT17A Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17A Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a special feature of the AT17A Series, the user can select the polarity of the reset function by programming an EEPROM byte. The AT17C/LV512/010A parts generate their own internal clock and can be used as a system “master” for loading the FPGA devices.

The Atmel devices also supports a system friendly READY pin and a write protect mechanism. The READY pin is used to simplify system power-up considerations. The WP1 pin is used to protect part of the device memory during in-system programming.

The AT17A Series can be programmed with industry standard programmers.

Pin Configurations

 

 

 

20-Pin PLCC

 

 

 

 

 

 

 

NC

DATA

NC

VCC

NC

 

 

 

 

 

 

3

2

1

20

19

 

 

 

 

DCLK

4

 

 

SER_EN

 

 

 

 

18

 

WP1

5

 

 

 

17

NC

 

 

NC

6

 

 

 

16

NC

 

 

NC

7

 

 

 

15

READY

 

 

 

 

 

 

 

14

NC

RESET/OE

8

10

11

12

 

 

 

9

13

 

 

 

 

 

 

nCS

GND

NC

nCASC

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPGA Serial

Configuration

Memories

AT17C512A

AT17LV512A

AT17C010A

AT17LV010A

Rev. 0974A–04/98

1

ATMEL AT17LV512A-10JI, AT17LV512A-10JC, AT17C010A-10JI, AT17C010A-10JC, AT17LV010A-10JI Datasheet

Block Diagram

SER_EN

 

PROGRAMMING

PROGRAMMING

DATA SHIFT

MODE LOGIC

REGISTER

OSC

24/32

CONTROL

 

ROW

 

 

ADDRESS

 

 

COUNTER

11

EEPROM

 

ROW

 

CELL

 

DECODER

OSC

MATRIX

 

 

 

 

 

24/32

BIT

5

COLUMN

COUNTER

 

DECODER

 

 

 

TC

 

DCLK

OE

nCS

nCASC

DATA

Device Configuration

 

FPGA Device Configuration

The control signals for configuration EEPROMs–nCS, OE, and DCLK–interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent controller.

The configuration EEPROM device’s OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address counter and the oscillator. When OE is driven low, the configuration EEPROM device resets the address counter and tri-states its DATA pin. The nCS pin controls the output of the AT17A Series. If nCS is held high after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven low, the counter and the DATA output pin are enabled. When OE is driven low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS.

When the configurator has driven out all of its data and nCASC is driven low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset.

FPGA devices can be configured with an AT17A Series EEPROM. The AT17A Series device stores configuration data in its EEPROM array and clocks the data out serially with its internal oscillator. The OE, nCS, and DCLK pins supply the control signals for the address counter and the output tri-state buffer. The AT17A Series device sends a serial bitstream of configuration data to its DATA pin, which is connected to the DATA0 input pin on the FPGA device.

When configuration data for a FPGA device exceeds the capacity of a single AT17A Series device, multiple AT17A Series devices can be serially linked together. When multiple AT17A Series devices are required, the nCASC and nCS pins provide handshaking between the AT17A Series devices.

The position of an AT17A Series device in a chain determines its operation. The first AT17A Series device in a Configurator chain is powered up or reset with nCS low and is configured for FPGA devices protocol. This AT17A Series device supplies all clock pulses to one or more FPGA devices and to any downstream AT17A Series during configuration. The first AT17A Series device also provides the first stream of data to the FPGA devices during

2 AT17C/LV/512A/010A

AT17C/LV/512A/010A

multi-device configuration. Once the first AT17A Series device finishes sending configuration data, it drives its nCASC pin low, which drives the nCS pin of the second AT17A Series device low. This activates the second AT17A Series device to send configuration data to the FPGA device.

The first AT17A Series device clocks all subsequent AT17A Series devices until configuration is complete. Once all configuration data is transferred and nCS on the first

AT17A Series device is driven high by CONF_DONE on the FPGA devices, the first AT17A Series device clocks 16 additional cycles to initialize the FPGA device. Then the first AT17A Series device goes into zero-power (idle) state. If nCS on the first AT17A Series device is driven high before all configuration data is transferred–or if the nCS is not driven high after all configuration data is transferred– the nSTATUS is driven low, indicating a configuration error.

Figure 1. FPGA Device Configured with Two AT17A Series Devices

VCC

 

 

 

VCC

 

 

 

 

1KW

1KW

 

 

 

 

 

AT17C010A

AT17C010A

VCC

Device 1

Device 1

Device 2

 

nCONFIG

DCLK

DCLK

 

DCLK

 

 

DATA0

DATA

 

DATA

 

 

CONF_DONE

nCS

nCASC

nCS

 

MSEL0

nSTATUS

OE

 

OE

 

MSEL1

nCE

 

 

 

GND

 

GND

 

 

 

3

Pin Configurations

Pin Number

 

 

 

 

 

 

 

 

 

(20-Pin PLCC)

 

Pin Name

Pin Type

Description

 

 

 

 

 

 

2

 

 

DATA

Output

Serial data output.

 

 

 

 

 

 

4

 

 

DCLK

I/O

Clock output or clock input. Rising edges on DCLK increment the internal address

 

 

 

 

 

 

 

counter and present the next bit of data to the DATA pin. The counter is incremented

 

 

 

 

 

 

 

only if the OE input is held high, the nCS input is held low, and all configuration data

 

 

 

 

 

 

 

has not been transferred to the target device (otherwise, in FPGA 10K master mode,

 

 

 

 

 

 

 

the DCLK pin drives low).

 

 

 

 

 

 

5

 

 

WP1

Input

WRITE PROTECT (1). Used to protect portions of memory during programming. See

 

 

 

 

 

 

 

programming guide for details.

 

 

 

 

 

 

 

8

 

 

 

 

 

Input

Output enable (active high) and reset (active low). A low logic level resets the address

RESET/OE

 

 

 

 

 

 

 

counter. A high logic level enables DATA and permits the address counter to count. In

 

 

 

 

 

 

 

the mode, if this pin is low (reset), the internal oscillator becomes inactive and DCLK

 

 

 

 

 

 

 

drives low.

 

 

 

 

 

 

9

 

 

nCS

Input

Chip select input (active low). A low input allows DCLK to increment the address

 

 

 

 

 

 

 

counter and enables DATA to drive out. If the AT17A Series is reset with nCS low, the

 

 

 

 

 

 

 

device initializes as the first device in a daisy-chain. If the AT17A Series is reset with

 

 

 

 

 

 

 

nCS high, the device initializes as the next AT17A Series device in the chain

 

 

 

 

 

 

10

 

 

GND

Ground

A 0.2 μF decoupling capacitor should be placed between the VCC and GND pins.

 

 

 

 

 

 

12

 

 

nCASC

Output

Cascade select output (active low). This output goes low when the address counter

 

 

 

 

 

 

 

has reached its maximum value. In a daisy-chain of AT17A Series devices, the

 

 

 

 

 

 

 

nCASC pin of one device is usually connected to the nCS input pin of the next device

 

 

 

 

 

 

 

in the chain, which permits DCLK to clock data from the next AT17A Series device in

 

 

 

 

 

 

 

the chain.

 

 

 

 

 

 

 

 

 

A2

Input

Device selection input, A2. This is used to enable (or select) the device during

 

 

 

 

 

 

 

programming, when

SER_EN

is Low (see Programming Guide for more details)

 

 

 

 

 

 

15

 

 

READY

Output

Open collector reset state indicator. Driven Low during power-up reset, released when

 

 

 

 

 

 

 

power-up is complete. (Recommend a 4.7KΩ Pull-up on this pin if used).

 

 

 

 

 

 

 

18

 

 

 

 

 

Input

Serial enable is normally high during FPGA loading operations. Bringing SER_EN

 

SER_EN

 

 

 

 

 

 

 

Low, enables the two wire serial interface mode for programming.

 

 

 

 

 

 

20

 

 

VCC

Power

Power pin.

Absolute Maximum Ratings*

..................................Operating Temperature

 

- 55 ° C to +125°C

*NOTICE: Stresses beyond those listed under Absolute Maxi-

 

 

 

mum Ratings may cause permanent damage to the

Storage Temperature .....................................

 

- 65 ° C to +150°C

device. These are stress ratings only, and functional

 

 

 

operation of the device at these or any other condi-

Voltage on Any Pin

 

 

tions beyond those listed under Operating Conditions

with Respect to Ground .............................

-0.1V to VCC + 0.5V

is not implied. Exposure to Absolute Maximum Rat-

Supply Voltage (VCC)

 

- 0.5V to +7.0V

ings conditions for extended periods of time may

 

affect device reliability.

Maximum Soldering Temp. (10 s @ 1/16 in.)

..................260°C

 

ESD (RZAP = 1.5K, CZAP = 100 pF) ................................

 

2000V

 

 

 

 

 

4 AT17C/LV/512A/010A

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