ATMEL Corporation AT17LV512-10JI, AT17LV512-10JC, AT17C010-10JI, AT17C010-10JC, AT17LV010-10JI, AT17LV010-10JC, AT17C512-10JI, AT17C512-10JC Datasheet

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Features

E2 Programmable 524,288 x 1 and 1,048,576 x 1 bit Serial Memories Designed To Store Configuration Programs For Field Programmable Gate Arrays (FPGA)

Simple Interface to SRAM FPGAs

Compatible With Atmel AT6000, AT40K FPGAs, Altera EPF8K, EPF10K,

EPF6K FPGAs, ORCA FPGAs, Xilinx XC3000, XC4000, XC5200 FPGAs, Motorola MPA1000 FPGAs

Cascadable To Support Additional Configurations or Future Higher-density Arrays

Low-power CMOS EEPROM Process

Programmable Reset Polarity

Available In PLCC Package (Pin Compatable across Product Family)

In-System Programmable Via 2-Wire Bus

Emulation of 24CXX Serial EPROMs

Available in 3.3V ± 10% LV and 5V Versions

System Friendly READY Pin

Description

The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The high-density AT17 Series is packaged in the popular 20-pin PLCC. The high-density AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The high-density AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. The user can select the polarity of the reset function by programming one EEPROM byte. The devices also support a write protection mode and a system friendly READY pin, which signifies a “good” power level to the device and can be used to ensure reliable system power-up.

The high-density AT17 Series can be programmed with industry-standard programmers, and the Atmel ATDH2200 Programming board.

Pin Configurations

20-Pin PLCC

 

 

 

 

 

D

 

V

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

N

T

N

C

N

 

 

 

 

 

 

 

C

A

C

C

C

 

 

 

 

 

 

 

3

2

1

20

19

 

 

 

CLK

4

 

 

 

18

NC

 

5

 

 

 

17

 

 

WP1

 

 

 

SER_EN

 

 

 

 

6

 

 

 

16

NC

RESET/OE

 

 

 

 

WP2

7

 

 

 

15

READY

 

 

 

8

 

 

 

14

 

 

 

CE

 

 

 

CEO

 

 

 

 

9

10

11

12

13

 

 

 

 

 

 

 

N

G

N

N

N

 

 

 

 

 

 

 

C

N

C

C

C

 

 

 

 

 

 

 

 

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPGA

Configuration

E2PROM

Memory

512K and 1M

AT17C512

AT17LV512

AT17C010

AT17LV010

Rev. 0944A-A–12/97

1

ATMEL Corporation AT17LV512-10JI, AT17LV512-10JC, AT17C010-10JI, AT17C010-10JC, AT17LV010-10JI, AT17LV010-10JC, AT17C512-10JI, AT17C512-10JC Datasheet

Controlling The High-Density AT17 Series Serial EEPROMs

Most connections between the FPGA device and the Serial EEPROM are simple and self-explanatory:

The DATA output of the high-density AT17 Series drives DIN of the FPGA devices.

The master FPGA CCLK output drives the CLK input of the high-density AT17 Series.

The CEO output of any AT17C/LV512/010 drives the CE input of the next AT17C/LV512/010 in a cascade chain of PROMs.

SER_EN must be connected to VCC, (except during ISP).

READY is available as an open-collector indicator of the device’s RESET status; it is driven Low while the device is in its POWER-ON RESET cycle and released (tri-stated) when the cycle is complete.

There are two different ways to use the inputs CE and OE, as shown in the AC Characteristics waveforms.

Condition 1

The simplest connection is to have the FPGA D/P output drive both CE and RESET/OE in parallel (Figure 1). Due to

its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configuration cycle. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the high-density AT17 Series does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configuration cycle.

Condition 2

The FPGA D/P output drives only the CE input of the highdensity AT17 Series, while its OE input is driven by the inversion of the input to the FPGA RESET input pin. This connection works under all normal circumstances, even when the user aborts a configuration before D/P has gone High. A High level on the RESET/OE input to the AT17C/LVxxx – during FPGA reset – clears the Configurator’s internal address pointer, so that the reconfiguration starts at the beginning. The high-density AT17 Series does not require an inverter since the RESET polarity is programmable.

Block Diagram

2 AT17C/LV512/010

AT17C/LV512/010

Pin Configurations

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLCC

 

Name

I/O

 

Description

 

 

 

 

 

2

 

DATA

I/O

Three-state DATA output for reading. Input/Output pin for programming.

 

 

 

 

 

 

4

 

 

CLK

I

Clock input. Used to increment the internal address and bit counter for reading and

 

 

 

 

 

 

 

 

 

 

 

programming.

 

 

 

 

 

 

 

5

 

 

WP1

I

 

WRITE PROTECT (1). Used to protect portions of memory during programming. See

 

 

 

 

 

 

 

 

 

 

 

programming guide for details.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET/OE

 

 

RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET/OE

 

inputs enables the data output driver. A High level on RESET/OE resets both the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

address and bit counters. The logic polarity of this input is programmable as either RESET/OE

 

 

 

 

 

 

 

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET/OE. This document describes the pin as RESET/OE.

 

 

 

 

 

 

 

7

 

 

WP2

I

 

WRITE PROTECT (2). Used to protect portions of memory during programming. See

 

 

 

 

 

 

 

 

 

 

programming guide for details.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

I

 

Chip Enable input. Used for device selection. A Low level on both

 

and

 

 

enables the data

 

 

 

CE

CE

OE

 

 

 

 

 

 

 

 

 

 

 

output driver. A High level on

CE

disables both the address and bit counters and forces the

 

 

 

 

 

 

 

 

 

 

 

device into a low power mode. Note this pin will not enable/disable the device in 2-wire Serial

 

 

 

 

 

 

 

 

 

 

 

Programming mode (i.e., when

SER_EN

 

is Low).

 

 

 

 

 

10

 

GND

 

Ground pin.

 

 

 

 

 

 

 

 

 

14

 

 

 

 

 

 

 

O

 

Chip Enable Out output. This signal is asserted Low on the clock cycle following the last bit

 

 

CEO

 

 

 

 

 

 

 

 

 

 

 

read from the memory. It will stay Low as long as CE and

OE

are both Low. It will then follow

 

 

 

 

 

 

 

 

 

 

 

CE

until

OE

goes High. Thereafter,

CEO

will stay High until the entire PROM is read again and

 

 

 

 

 

 

 

 

 

 

 

senses the status of RESET polarity.

 

 

 

 

 

 

 

 

 

 

 

 

A2

I

 

Device selection input, A2. This is used to enable (or select) the device during programming,

 

 

 

 

 

 

 

 

 

 

 

when

SER_EN

is Low (see Programming Guide for more details)

 

 

 

 

 

15

 

READY

O

Open collector reset state indicator. Driven Low during power-up reset, released when power-

 

 

 

 

 

 

 

 

 

 

up is complete. (Recommend a 4.7KΩ Pull-up on this pin if used).

 

 

 

 

 

 

 

17

 

 

 

 

 

 

 

I

 

Serial enable is normally high during FPGA loading operations. Bringing SER_EN Low,

SER_EN

 

 

 

 

 

 

 

 

 

 

 

 

enables the two wire serial interface mode for programming.

 

 

 

 

 

 

 

20

 

 

VCC

 

 

+3.3V/+5V power supply pin.

Absolute Maximum Ratings*

..................................Operating Temperature

 

- 55°C to +125°C

*NOTICE: Stresses beyond those listed under Absolute Maxi-

 

 

 

mum Ratings may cause permanent damage to the

Storage Temperature .....................................

 

- 65°C to +150°C

device. These are stress ratings only, and functional

 

 

 

operation of the device at these or any other condi-

Voltage on Any Pin

 

 

tions beyond those listed under Operating Conditions

with Respect to Ground ............................

-0.1V to VCC + 0.5V

is not implied. Exposure to Absolute Maximum Rat-

Supply Voltage (VCC)

 

- 0.5V to +7.0V

ings conditions for extended periods of time may

 

affect device reliability.

Maximum Soldering Temp. (10 s @ 1/16 in.)

..................260°C

 

ESD (RZAP = 1.5K, CZAP = 100 pF)...............................

 

2000V

 

 

 

 

 

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