Features
•Advanced, High-Speed Programmable Logic Device-Superset of 22V10
–Improved Performance - 7.5 ns tPD, 95 MHz External Operation
–Enhanced Logic Flexibility
–Backward Compatible with ATV750/L Software and Hardware
•New Flip-Flop Features
–D- or T-Type
–Product Term or Direct Input Pin Clocking
•High-Speed Erasable Programmable Logic Devices
–7.5 ns Maximum Pin-to-Pin Delay
Device |
ICC, Stand-By |
ATV750B |
125 mA |
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ATV750BL |
15 mA |
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•Highest Density Programmable Logic Available in a 24-Pin Package
•Increased Logic Flexibility
–42 Array Inputs, 20 Sum Terms and 20 Flip-Flops
•Enhanced Output Logic Flexibility
–All 20 Flip-Flops Feed Back Internally
–10 Flip-Flops are Also Available as Outputs
•Full Military, Commercial and Industrial Temperature Ranges
Logic Diagram
Description
The ATV750Bs are twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform, predictable delays guarantee fast in-system performance.
(continued)
Pin Configurations
Pin Name |
Function |
DIP/SOIC |
PLCC/LCC |
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CLK |
Clock |
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IN |
Logic Inputs |
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I/O |
Bidirectional Buffers |
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* |
No Internal Connection |
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VCC |
+5V Supply |
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Top View
High-Speed |
UV-Erasable |
Programmable |
Logic Device |
ATV750B |
Rev. 0301D–05/98 |
1 |
Each of the ATV750B’s 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bidirectional I/O pins. Each flip-flop is individually configurable as either D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops.
There are 171 total product terms available. A variable format is used to assign between four to eight product terms per sum term. There are two sum terms per output, providing added flexibility. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare.
Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop may also be individually configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flipflops. Register preload functions are provided to simplify testing. All registers automatically reset upon power up.
The ATV750BL is a low power device with speeds as fast as 15 ns. The ATV750BL provides the optimum low power PLD solution, with full CMOS output levels. This device significantly reduces total system power, thereby allowing bat- tery-powered operation.
Abosute Maximum Rating*
................................Temperature Under Bias |
-55°C to +125°C |
Storage Temperature ..................................... |
-65°C to +150°C |
Voltage on Any Pin with |
-2.0V to +7.0V(1) |
Respect to Ground ......................................... |
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Voltage on Input Pins |
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with Respect to Ground |
-2.0V to +14.0V(1) |
During Programming..................................... |
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Programming Voltage with |
-2.0V to +14.0V(1) |
Respect to Ground ....................................... |
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Integrated UV Erase Dose.............................. |
7258 W•sec/cm2 |
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Logic Options
Combinatorial Output
Combined Terms |
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Separate Terms |
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*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note: 1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns.Maximum output pin voltage is VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns.
Registered Output
Combined Terms |
Separate Terms |
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2 |
ATV750B |
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ATV750B
Clock MUX
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CKMUX |
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CKi |
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TO |
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CLK |
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LOGIC |
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CLOCK |
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CELL |
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PRODUCT |
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SELECT |
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TERM |
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Output Options
DC and AC Operating Conditions(1)
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Commercial |
Commercial |
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-7, -10, -15 |
-25 |
Industrial |
Military |
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Operating Temperature (Case) |
0°C - 70°C |
0°C - 70°C |
-40°C - 85°C |
-55°C - 125°C |
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VCC Power Supply |
5V ± 5% |
5V ± 10% |
5V ± 10% |
5V ± 10% |
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Note: 1. See ordering information for valid speed and temperature combination.
3
DC Characteristics
Symbol |
Parameter |
Condition |
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Min |
Typ |
Max |
Units |
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ILI |
Input Load Current |
VIN = -0.1V to VCC + 1V |
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10 |
μA |
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ILO |
Output Leakage |
VOUT = -0.1V to VCC + 0.1V |
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10 |
μA |
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Current |
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B-7, -10 |
Com. |
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125 |
180 |
mA |
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Ind.,Mil. |
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125 |
190 |
mA |
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VCC = MAX, |
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Power Supply |
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Com. |
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125 |
180 |
mA |
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ICC |
VIN = MAX, |
B-15, -25 |
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Current, Standby |
Ind.,Mil. |
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125 |
190 |
mA |
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Outputs Open |
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BL-15 |
Com. |
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15 |
30 |
mA |
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Ind.,Mil. |
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15 |
30 |
mA |
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(1) |
Output Short |
VOUT = 0.5V |
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-120 |
mA |
IOS |
Circuit Current |
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VIL |
Input Low Voltage |
4.5 ≤ VCC ≤ 5.5V |
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-0.6 |
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0.8 |
V |
VIH |
Input High Voltage |
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2.0 |
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VCC + 0.75 |
V |
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Output Low |
VIN = VIH or VIL, |
IOL = 16 mA |
Com.,Ind. |
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0.5 |
V |
VOL |
IOL = 12 mA |
Mil. |
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0.5 |
V |
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Voltage |
VCC = MIN |
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IOL = 24 mA |
Com. |
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0.8 |
V |
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VOH |
Output High |
VIN = VIH or VIL, |
IOH = -100 μA |
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VCC - 0.3 |
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V |
Voltage |
VCC = MIN |
IOH = -4.0 mA |
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2.4 |
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V |
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Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Input Test Waveforms and |
Output Test Load |
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Measurement Levels |
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tR, tF < 3 ns (10% to 90%)
4 |
ATV750B |
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ATV750B
AC Waveforms, Product Term Clock(1)
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Product Term Clock(1)
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-7 |
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-10 |
B/BL-15 |
B/BL-25 |
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Symbol |
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Parameter |
Min |
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Max |
Min |
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Max |
Min |
Max |
Min |
Max |
Units |
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tPD |
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Input or Feedback to |
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7.5 |
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10 |
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15 |
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25 |
ns |
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Non-Registered Output |
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tEA |
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Input to Output Enable |
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7.5 |
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10 |
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15 |
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25 |
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tER |
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Input to Output Disable |
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7.5 |
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10 |
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15 |
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25 |
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tCO |
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Clock to Output |
3 |
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7.5 |
4 |
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10 |
5 |
12 |
6 |
20 |
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tCF |
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Clock to Feedback |
1 |
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5 |
4 |
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7.5 |
5 |
9 |
5 |
10 |
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tS |
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Input Setup Time |
3 |
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4 |
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8/12 |
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14 |
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tSF |
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Feedback Setup Time |
3 |
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4 |
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7 |
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7 |
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tH |
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Hold Time |
1 |
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2 |
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5/7 |
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5/7 |
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tP |
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Clock Period |
7 |
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11 |
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14 |
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17 |
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tW |
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Clock Width |
3.5 |
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5.5 |
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7 |
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8.5 |
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External Feedback 1/(tS+tCO) |
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95 |
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71 |
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50/41 |
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29 |
MHz |
FMAX |
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Internal Feedback 1/(tSF+tCF) |
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125 |
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86 |
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62 |
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58 |
MHz |
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No Feedback 1/(tP) |
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142 |
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90 |
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71 |
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58 |
MHz |
tAW |
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Asynchronous Reset Width |
5 |
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10 |
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15 |
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20 |
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tAR |
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Asynchronous Reset |
3 |
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10 |
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15 |
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20 |
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Recovery Time |
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tAP |
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Asynchronous Reset to |
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8 |
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12 |
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15 |
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25 |
ns |
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Registered Output Reset |
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tSP |
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Setup Time, Synchronous Preset |
4 |
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7 |
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8 |
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15 |
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ns |
Note: 1. |
See ordering information for valid part numbers. |
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5