ATMEL TS80C51RA2, TS80C51RD2, TS83C51RB2, TS83C51RC2, TS83C51RD2 User Manual

TS80C51RA2

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

High Performance 8-bit Microcontrollers

1. Description

Atmel Wireless & Microcontrollers TS80C51Rx2 is high performance CMOS ROM, OTP, EPROM and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller.

The TS80C51Rx2 retains all features of the 80C51 with extended ROM/EPROM capacity (16/32/64 Kbytes), 256 bytes of internal RAM, a 7-source , 4-level interrupt system, an on-chip oscilator and three timer/counters.

In addition, the TS80C51Rx2 has a Programmable Counter Array, an XRAM of 256 or 768 bytes, a Hardware Watchdog Timer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism.

The fully static design of the TS80C51Rx2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.

The TS80C51Rx2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative.

2. Features

∙80C52 Compatible

∙8051 pin and instruction compatible

∙Four 8-bit I/O ports

∙Three 16-bit timer/counters

∙256 bytes scratchpad RAM

∙High-Speed Architecture

∙40 MHz @ 5V, 30MHz @ 3V

∙X2 Speed Improvement capability (6 clocks/ machine cycle)

30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V)

∙Dual Data Pointer

∙On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64Kbytes)

∙On-chip eXpanded RAM (XRAM) (256 or 768 bytes)

∙Programmable Clock Out and Up/Down Timer/ Counter 2

∙Programmable Counter Array with

∙High Speed Output,

∙Compare / Capture,

∙Pulse Width Modulator,

∙Watchdog Timer Capabilities

∙Hardware Watchdog Timer (One-time enabled with Reset-Out)

∙2 extra 8-bit I/O ports available on RD2 with high pin count packages

∙Asynchronous port reset

∙Interrupt Structure with

∙7 Interrupt sources,

∙4 level priority interrupt system

∙Full duplex Enhanced UART

∙Framing error detection

∙Automatic address recognition

∙Low EMI (inhibit ALE)

∙Power Control modes

∙Idle mode

∙Power-down mode

∙Power-off Flag

∙Once mode (On-chip Emulation)

∙Power supply: 4.5-5V, 2.7-5.5V

∙Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC)

∙Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44 (window), CDIL40 (window), PLCC68, VQFP64 1.4, JLCC68 (window)

Rev. C - 06 March, 2001

1

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

	PDIL40
	PLCC44	ROM (bytes)	EPROM (bytes)	XRAM (bytes)	TOTAL RAM	I/O
					(bytes)
	VQFP44 1.4
	TS80C51RA2	0	0	256	512	32
	TS80C51RD2	0	0	768	1024	32
	TS83C51RB2	16k	0	256	512	32
	TS83C51RC2	32k	0	256	512	32
	TS83C51RD2	64k	0	768	1024	32
	TS87C51RB2	0	16k	256	512	32
	TS87C51RC2	0	32k	256	512	32
	TS87C51RD2	0	64k	768	1024	32
	PLCC68	ROM (bytes)	EPROM (bytes)	XRAM (bytes)	TOTAL RAM	I/O
	VQFP64 1.4				(bytes)
	TS80C51RD2	0	0	768	1024	48
	TS83C51RD2	64k	0	768	1024	48
	TS87C51RD2	0	64k	768	1024	48

3. Block Diagram

RxD

TxD

Vcc Vss

ECI

PCA

T2EX

T2

(3)

(3)

(1)

(1)

(1)

(1)

XTAL1

RAM

ROM

XRAM

XTAL2

EUART

/EPROM

PCA

Timer2

256x8

256/768x8

0/16/32/64Kx8

ALE/ PROG	C51
PSEN	CORE	IB-bus
	CPU

EA/VPP

(3)

Timer 0

INT

Parallel I/O Ports & Ext. Bus

Watch

RD

Timer 1

Ctrl

Dog

(3)

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

WR

(2)

(2)

(3)

(3)

(3)

(3)

P1

P2

P3

P4

P5

RESET

T0

T1

INT0

INT1

P0

(1): Alternate function of Port 1

(2): Only available on high pin count packages

(3): Alternate function of Port 3

2	Rev. C - 06 March, 2001

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

4. SFR Mapping

The Special Function Registers (SFRs) of the TS80C51Rx2 fall into the following categories:

∙C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1

∙I/O port registers: P0, P1, P2, P3, P4, P5

∙Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H

∙Serial I/O port registers: SADDR, SADEN, SBUF, SCON

∙Power and clock control registers: PCON

∙HDW Watchdog Timer Reset: WDTRST, WDTPRG

∙PCA registers: CL, CH, CCAPiL, CCAPiH, CCON, CMOD, CCAPMi

∙Interrupt system registers: IE, IP, IPH

∙Others: AUXR, CKCON

Table 1. All SFRs with their address and their reset value

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

A8h

A0h

98h

90h

88h

80h

	Bit			Non Bit addressable
	addressable
	0/8	1/9	2/A	3/B	4/C	5/D	6/E	7/F
		CH	CCAP0H	CCAP1H	CCAPL2H	CCAPL3H	CCAPL4H		FFh
		0000 0000	XXXX XXXX	XXXX XXXX	XXXX XXXX	XXXX XXXX	XXXX XXXX
	B								F7h
	0000 0000
	P5 bit	CL	CCAP0L	CCAP1L	CCAPL2L	CCAPL3L	CCAPL4L		EFh
	addressable
		0000 0000	XXXX XXXX	XXXX XXXX	XXXX XXXX	XXXX XXXX	XXXX XXXX
	1111 1111
	ACC								E7h
	0000 0000
	CCON	CMOD	CCAPM0	CCAPM1	CCAPM2	CCAPM3	CCAPM4		DFh
	00X0 0000	00XX X000	X000 0000	X000 0000	X000 0000	X000 0000	X000 0000
	PSW								D7h
	0000 0000
	T2CON	T2MOD	RCAP2L	RCAP2H	TL2	TH2			CFh
	0000 0000	XXXX XX00	0000 0000	0000 0000	0000 0000	0000 0000
	P4 bit							P5 byte	C7h
	addressable							addressable
	1111 1111							1111 1111
	IP	SADEN							BFh
	X000 000	0000 0000
	P3							IPH	B7h
	1111 1111							X000 0000
	IE	SADDR							AFh
	0000 0000	0000 0000
	P2		AUXR1				WDTRST	WDTPRG	A7h
	1111 1111		XXXX0XX0				XXXX XXXX	XXXX X000
	SCON	SBUF							9Fh
	0000 0000	XXXX XXXX
	P1								97h
	1111 1111
	TCON	TMOD	TL0	TL1	TH0	TH1	AUXR	CKCON	8Fh
	0000 0000	0000 0000	0000 0000	0000 0000	0000 0000	0000 0000	XXXXXX00	XXXX XXX0
	P0	SP	DPL	DPH				PCON	87h
	1111 1111	0000 0111	0000 0000	0000 0000				00X1 0000
	0/8	1/9	2/A	3/B	4/C	5/D	6/E	7/F

reserved

Rev. C - 06 March, 2001

3

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

5. Pin Configuration

P1.0 / T2

1

40

VCC

P1.1 / T2EX

2

39

P0.0

/ A0

P1.2

3

38

P0.1

/ A1

P1.3

4

37

P0.2 / A2

P1.4

5

36

P0.3 / A3

P1.5

6

35

P0.4

/ A4

P0.5

/ A5

P1.6

7

34

P1.7

8

33

P0.6

/ A6

P1.5

RST

9

32

P0.7

/ A7

P1.6

P3.0/RxD

10

PDIL/

31

EA/VPP

P1.7

P3.1/TxD

11

30

ALE/PROG

RST

12 CDIL40

PSEN

P3.2/INT0

29

P3.0/RxD

P2.7

/ A15

P3.3/INT1

13

28

NIC*

P3.4/T0

14

27

P2.6

/ A14

P2.5

/ A13

P3.1/TxD

P3.5/T1

15

26

P2.4

/ A12

P3.2/INT0

P3.6/WR

16

25

P2.3

/ A11

P3.3/INT1

17

24

P3.7/RD

P2.2

/ A10

P3.4/T0

XTAL2

18

23

P3.5/T1

XTAL1

19

22

P2.1

/ A9

VSS

20

21

P2.0

/ A8

							P1.4		P1.3 P1.2				P1.1/T2EX		P1.0/T2		VSS1/NIC*			VCC		P0.0/AD0		P0.1/AD1		P0.2/AD2		P0.3/AD3
						44 43 42						41		40		39 38					37		36		35		34
		P1.5				1
	P1.6					2
	P1.7					3
		RST				4
P3.0/RxD						5							VQFP44 1.4
		NIC*				6
P3.1/TxD						7
						8
P3.2/INT0
P3.3/INT1						9

P3.4/T0 10

P3.5/T1 11

12 13 14 15 16 17 18 19 20 21 22

P3.6/WR		P3.7/RD	XTAL2	XTAL1	VSS	NIC*	P2.0/A8	P2.1/A9	P2.2/A10	P2.3/A11	P2.4/A12

7

8

9

10

11

12

13

14

15

16

17

33

32

31

30

29

28

27

26

25

24

23

		P1.4		P1.3	P1.2	P1.1/T2EX	P1.0/T2	VSS1/NIC*	VCC	P0.0/AD0	P0.1/AD1	P0.2/AD2	P0.3/AD3
								1
6			5		4	3	2		44	43	42	41	40
													39
													38
													37
													36
													35
					PLCC/CQPJ 44								34
													33
													32
													31
													30
													29
18 19 20 21 22 23 24 25 26 27 28
		P3.6/WR		P3.7/RD	XTAL2	XTAL1	VSS	NIC*	P2.0/A8	P2.1/A9	P2.2/A10	P2.3/A11	P2.4/A12

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP

NIC*

ALE/PROG

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP

NIC*

ALE/PROG

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

*NIC: No Internal Connection

4	Rev. C - 06 March, 2001

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

P0.4/AD4

P5.4

P5.3

P0.5/AD5

P0.6/AD6

NIC

P0.7/AD7

EA/VPP

NIC

ALE/PROG

PSEN

NIC

P2.7/A15

P2.6/A14

P5.2

P5.1

P2.5/A13

9

8

7

6

5

4

3

2

1

68 67 66 65 64

63 62 61

P5.5

10

60

P5.0

P0.3/AD3

11

59

P2.4/A12

P0.2/AD2

12

58

P2.3/A11

P5.6

13

57

P4.7

P0.1/AD1

14

56

P2.2/A10

P0.0/AD0

15

55

P2.1/A9

P5.7

16

54

P2.0/A8

VCC

17

PLCC 68

53

P4.6

NIC

18

52

NIC

P1.0/T2

19

51

VSS

P4.0

20

50

P4.5

P1.1/T2EX

21

49

XTAL1

P1.2

22

48

XTAL2

P1.3

23

47

P3.7/RD

P4.1

24

46

P4.4

P1.4

25

45

P3.6/WR

P4.2

26

44

P4.3

27 28

29 30 31 32 33 34 35 36 37 38 39 40

41 42 43

P1.5

P1.6

P1.7

RST

NIC

NIC

NIC

P3.0/RxD

NIC

NIC

NIC

NIC

P3.1/TxD

P3.3/INT1

P3.4/T0

P3.5/T1

P3.2/INT0

P0.4/AD4

P5.4

P5.3 P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP NIC

ALE/PROG

PSEN

P2.7/A15 P2.6/A14

P5.2

P5.1 P2.5/A13

P5.0

P5.5

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

P2.4/A12

1

48

P0.3/AD3

2

47

P2.3/A11

P0.2/AD2

3

46

P4.7

P5.6

4

45

P2.2/A10

P0.1/AD1

5

44

P2.1/A9

P0.0/AD0

6

43

P2.0/A8

P5.7

7

42

P4.6

VCC

8

VQFP64 1.4

41

NIC

VSS

9

40

VSS

P1.0/T2

10

39

P4.5

P4.0

11

38

XTAL1

P1.1/T2EX

12

37

XTAL2

P1.2

13

36

P3.7/RD

P1.3

14

35

P4.4

P4.1

15

34

P3.6/WR

P1.4

16

33

P4.3

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

P4.2

P1.5

P1.6 P1.7

RST

NIC

NIC NIC

P3.0/RxD

NIC

NIC P3.1/TxD

P3.2/INT0

P3.3/INT1 P3.4/T0

P3.5/T1

NIC: No InternalConnection

Rev. C - 06 March, 2001

5

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

Mnemonic		Pin Number		Type					Name And Function
	DIL	LCC	VQFP 1.4
VSS	20	22	16	I		Ground: 0V reference
Vss1		1	39	I		Optional Ground: Contact the Sales Office for ground connection.
VCC	40	44	38	I		Power Supply: This is the power supply voltage for normal, idle and power-
						down operation
P0.0-P0.7	39-32	43-36	37-30	I/O		Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
						written to them float and can be used as high impedance inputs. Port 0 pins must
						be polarized to Vcc or Vss in order to prevent any parasitic current consumption.
						Port 0 is also the multiplexed low-order address and data bus during access to
						external program and data memory. In this application, it uses strong internal
						pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM
						programming. External pull-ups are required during program verification during
						which P0 outputs the code bytes.
P1.0-P1.7	1-8	2-9	40-44	I/O		Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
			1-3			pins that have 1s written to them are pulled high by the internal pull-ups and
						can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
						source current because of the internal pull-ups. Port 1 also receives the low-order
						address byte during memory programming and verification.
						Alternate functions for Port 1 include:
	1	2	40	I/O		T2 (P1.0): Timer/Counter 2 external count input/Clockout
	2	3	41	I		T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
	3	4	42	I		ECI (P1.2): External Clock for the PCA
	4	5	43	I/O		CEX0 (P1.3): Capture/Compare External I/O for PCA module 0
	5	6	44	I/O		CEX1 (P1.4): Capture/Compare External I/O for PCA module 1
	6	7	45	I/O		CEX0 (P1.5): Capture/Compare External I/O for PCA module 2
	7	8	46	I/O		CEX0 (P1.6): Capture/Compare External I/O for PCA module 3
	8	9	47	I/O		CEX0 (P1.7): Capture/Compare External I/O for PCA module 4
P2.0-P2.7	21-28	24-31	18-25	I/O		Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
						pins that have 1s written to them are pulled high by the internal pull-ups and
						can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
						source current because of the internal pull-ups. Port 2 emits the high-order address
						byte during fetches from external program memory and during accesses to external
						data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
						uses strong internal pull-ups emitting 1s. During accesses to external data memory
						that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
						Some Port 2 pins (P2.0 to P2.5) receive the high order address bits during
						EPROM programming and verification:
P3.0-P3.7	10-17	11,	5,	I/O		Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
		13-19	7-13			pins that have 1s written to them are pulled high by the internal pull-ups and
						can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
						source current because of the internal pull-ups. Some Port 3 pins (P3.4 to P3.5)
						receive the high order address bits during EPROM programming and verification.
						Port 3 also serves the special features of the 80C51 family, as listed below.
	10	11	5	I		RXD (P3.0): Serial input port
	11	13	7	O		TXD (P3.1): Serial output port
	12	14	8	I					(P3.2): External interrupt 0
						INT0
	13	15	9	I					(P3.3): External interrupt 1
						INT1
	14	16	10	I		T0 (P3.4): Timer 0 external input
	15	17	11	I		T1 (P3.5): Timer 1 external input
	16	18	12	O				(P3.6): External data memory write strobe
						WR
	17	19	13	O			(P3.7): External data memory read strobe
						RD

6	Rev. C - 06 March, 2001

						TS80C51RA2/RD2
						TS83C51RB2/RC2/RD2
						TS87C51RB2/RC2/RD2
	Reset	9	10	4	I	Reset: A high on this pin for two machine cycles while the oscillator is running,
						resets the device. An internal diffused resistor to VSS permits a power-on reset
						using only an external capacitor to VCC. If the hardware watchdog reaches its
						time-out, the reset pin becomes an output during the time the internal reset is
						activated.

Rev. C - 06 March, 2001

7

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

Mnemonic

Pin Number

Type

Name And Function

ALE/PROG

30

33

27

O (I)

Address Latch Enable/Program Pulse: Output pulse for latching the low byte

of the address during an access to external memory. In normal operation, ALE

is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,

and can be used for external timing or clocking. Note that one ALE pulse is

skipped during each access to external data memory. This pin is also the program

pulse input

during EPROM programming. ALE can be disabled by

(PROG)

setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal

fetches.

29

32

26

O

Program Store ENable: The read strobe to external program memory. When

PSEN

executing code from the external program memory,

PSEN

is activated twice each

machine cycle, except that two

activations are skipped during each access

PSEN

to external data memory.

is not activated during fetches from internal

PSEN

program memory.

31

35

29

I

External Access Enable/Programming Supply Voltage:

must be externally

EA/VPP

EA

held low to enable the device to fetch code from external program memory

locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is

held high, the device executes from internal program memory unless the program

counter contains an address greater than 3FFFH (RB) or 7FFFH (RC)

must

EA

be held low for ROMless devices. This pin also receives the 12.75V programming

supply voltage (VPP) during EPROM programming. If security level 1 is

programmed,

EA

will be internally latched on Reset.

XTAL1

19

21

15

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal

clock generator circuits.

XTAL2

18

20

14

O

Crystal 2: Output from the inverting oscillator amplifier

8	Rev. C - 06 March, 2001

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

5.1. Pin Description for 64/68 pin Packages

Port 4 and Port 5 are 8-bit bidirectional I/O ports with internal pull-ups. Pins that have 1 written to them are pulled high by the internal pull ups and can be used as inputs.

As inputs, pins that are externally pulled low will source current because of the internal pull-ups.

Refer to the previous pin description for other pins.

Table 2. 64/68 Pin Packages Configuration

	PLCC68	SQUARE VQFP64
		1.4
VSS	51	9/40
VCC	17	8
P0.0	15	6
P0.1	14	5
P0.2	12	3
P0.3	11	2
P0.4	9	64
P0.5	6	61
P0.6	5	60
P0.7	3	59
P1.0	19	10
P1.1	21	12
P1.2	22	13
P1.3	23	14
P1.4	25	16
P1.5	27	18
P1.6	28	19
P1.7	29	20
P2.0	54	43
P2.1	55	44
P2.2	56	45
P2.3	58	47
P2.4	59	48
P2.5	61	50
P2.6	64	53
P2.7	65	54
P3.0	34	25
P3.1	39	28

Rev. C - 06 March, 2001

9

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

						PLCC68	SQUARE VQFP64
							1.4
	P3.2					40	29
	P3.3					41	30
	P3.4					42	31
	P3.5					43	32
	P3.6					45	34
	P3.7					47	36
	RESET					30	21
	ALE/PROG					68	56
	PSEN					67	55
	EA/VPP					2	58
	XTAL1					49	38
	XTAL2					48	37
	P4.0					20	11
	P4.1					24	15
	P4.2					26	17
	P4.3					44	33
	P4.4					46	35
	P4.5					50	39
	P4.6					53	42
	P4.7					57	46
	P5.0					60	49
	P5.1					62	51
	P5.2					63	52
	P5.3					7	62
	P5.4					8	63
	P5.5					10	1
	P5.6					13	4
	P5.7					16	7

10	Rev. C - 06 March, 2001

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

6. TS80C51Rx2 Enhanced Features

In comparison to the original 80C52, the TS80C51Rx2 implements some new features, which are:

∙The X2 option.

∙The Dual Data Pointer.

∙The extended RAM.

∙The Programmable Counter Array (PCA).

∙The Watchdog.

∙The 4 level interrupt priority system.

∙The power-off flag.

∙The ONCE mode.

∙The ALE disabling.

∙Some enhanced features are also located in the UART and the timer 2.

6.1.X2 Feature

The TS80C51Rx2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages:

∙Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

∙Save power consumption while keeping same CPU power (oscillator power saving).

∙Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.

∙Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software.

6.1.1. Description

The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,

the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.

Figure 2. shows the mode switching waveforms.

						XTAL1:2
XTAL1					2	0			state machine: 6 clock cycles.
	FXTAL						1		CPU control

FOSC

X2

CKCON reg

Figure 1. Clock Generation Diagram

Rev. C - 06 March, 2001

11

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

XTAL1

XTAL1:2

X2 bit

CPU clock

STD Mode X2 Mode STD Mode

Figure 2. Mode Switching Waveforms

The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode).

CAUTION

In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (UART, timers, PCA...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.

12	Rev. C - 06 March, 2001

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

Table 3. CKCON Register

CKCON - Clock Control Register (8Fh)

7		6		5	4	3		2		1	0
-		-		-	-	-		-		-	X2
Bit Number		Bit				Description
	Mnemonic
7	-		Reserved
				The value read from this bit is indeterminate. Do not set this bit.
6	-		Reserved
				The value read from this bit is indeterminate. Do not set this bit.
5	-		Reserved
				The value read from this bit is indeterminate. Do not set this bit.
4	-		Reserved
				The value read from this bit is indeterminate. Do not set this bit.
3	-		Reserved
				The value read from this bit is indeterminate. Do not set this bit.
2	-		Reserved
				The value read from this bit is indeterminate. Do not set this bit.
1	-		Reserved
				The value read from this bit is indeterminate. Do not set this bit.
			CPU and peripheral clock bit
0		X2		Clear to select 12 clock periods per machine cycle (STD mode, FOSC=FXTAL/2).
				Set to select 6 clock periods per machine cycle (X2 mode, FOSC=FXTAL).

Reset Value = XXXX XXX0b

Not bit addressable

For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel-wm.com)

Rev. C - 06 March, 2001

13

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

6.2. Dual Data Pointer Register Ddptr

The additional data pointer can be used to speed up code execution and reduce code size in a number of ways.

The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (See Table 4.) that allows the program code to switch between them (Refer to Figure 3).

External Data Memory

7		0
		DPS	DPTR1
	AUXR1(A2H)		DPTR0
			DPH(83H) DPL(82H)

Figure 3. Use of Dual Pointer

Table 4. AUXR1: Auxiliary Register 1

AUXR1		-	-	-	-	GF3	-	-	DPS
Address 0A2H
	Reset value	X	X	X	X	0	X	X	0

Symbol Function

-Not implemented, reserved for future use.a

DPS	Data Pointer Selection.
	DPS	Operating Mode
	0	DPTR0 Selected
	1	DPTR1 Selected
GF3	This bit is a general purpose user flagb.

a.User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

b.GF3 will not be available on first version of the RC devices.

Application

Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer.

14	Rev. C - 06 March, 2001

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

ASSEMBLY LANGUAGE

;Block move using dual data pointers

;Destroys DPTR0, DPTR1, A and PSW

;note: DPS exits opposite of entry state

;unless an extra INC AUXR1 is added

00A2		AUXR1 EQU 0A2H
;
0000	909000	MOV DPTR,#SOURCE		; address of SOURCE
0003	05A2	INC	AUXR1	; switch data pointers
0005	90A000	MOV DPTR,#DEST		; address of DEST
0008		LOOP:
0008	05A2	INC	AUXR1	; switch data pointers
000A	E0	MOVX A,@DPTR		; get a byte from SOURCE
000B	A3	INC	DPTR	; increment SOURCE address
000C	05A2	INC	AUXR1	; switch data pointers
000E	F0	MOVX @DPTR,A		; write the byte to DEST
000F	A3	INC	DPTR	; increment DEST address
0010	70F6	JNZ	LOOP	; check for 0 terminator
0012	05A2	INC	AUXR1	; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.

Rev. C - 06 March, 2001

15

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

6.3. Expanded RAM (XRAM)

The TS80C51Rx2 provide additional Bytes of ramdom access memory (RAM) space for increased data parameter handling and high level language usage.

RA2, RB2 and RC2 devices have 256 bytes of expanded RAM, from 00H to FFH in external data space; RD2 devices have 768 bytes of expanded RAM, from 00H to 2FFH in external data space.

The TS80C51Rx2 has internal data memory that is mapped into four separate segments.

The four segments are:

•1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable.

•2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.

•3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only.

•4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit cleared in the AUXR register. (See Table 5.)

The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space.

When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction.

∙Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data ,accesses the SFR at location 0A0H (which is P2).

∙Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0,

# data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

∙The 256 or 768 XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first 256 or 768 bytes of external data memory.

∙With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations higher than FFH (i.e. 0100H to FFFFH) (higher than 2FFH (i.e. 0300H to FFFFH for RD devices) will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals. Refer to Figure . For RD devices, accesses to expanded RAM from 100H to 2FFH can only be done thanks to the use of DPTR.

∙With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM.

16	Rev. C - 06 March, 2001

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

FF(RA, RB, RC)/2FF (RD)	FF	FF	FFFF
	Upper		Special	External
	128 bytes
			Function
	Internal			Data
			Register
	Ram			Memory
			direct accesses
	indirect accesses
XRAM	80	80
256 bytes
	Lower
	128 bytes
	Internal
	Ram
	direct or indirect
	accesses		0100 (RA, RB, RC) or 0300 (RD)
00	00		0000

Figure 4. Internal and External Data Memory Address

Table 5. Auxiliary Register AUXR

AUXR

-

-

-

-

-

-

EXTRA

AO

Address 08EH

M

Reset value

X

X

X

X

X

X

0

0

Symbol

Function

-

Not implemented, reserved for future use.a

AO

Disable/Enable ALE

AO

Operating Mode

0

ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if

X2 mode is used)

1

ALE is active only during a MOVX or MOVC instruction

EXTRAM

Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR

EXTRAM

Operating Mode

0

Internal XRAM access using MOVX @ Ri/ @ DPTR

1

External data memory access

a.User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

Rev. C - 06 March, 2001

17

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

6.4. Timer 2

The timer 2 in the TS80C51RX2 is compatible with the timer 2 in the 80C52.

It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade. It is controlled by T2CON register (See Table 6) and T2MOD register (See Table 7). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the Atmel Wireless & Microcontrollers 8- bit Microcontroller Hardware description.

Refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes.

In TS80C51RX2 Timer 2 includes the following enhancements:

∙Auto-reload mode with up or down counter

∙Programmable clock-output

6.4.1. Auto-Reload Mode

The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 5. In this mode the T2EX pin controls the direction of count.

When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.

When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.

18	Rev. C - 06 March, 2001

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

				(:6 in X2 mode)
XTAL1					:12		0
			FOSC
FXTAL							1

T2

C/T2 TR2

T2CONreg T2CONreg

	(DOWN COUNTING RELOAD VALUE)		T2EX:
	FFh	FFh	if DCEN=1, 1=UP
	(8-bit)	(8-bit)	if DCEN=1, 0=DOWN
			if DCEN = 0, up counting
			TOGGLE	T2CONreg
				EXF2
	TL2	TH2	TF2	TIMER 2
	(8-bit)	(8-bit)		INTERRUPT
			T2CONreg

RCAP2L		RCAP2H
(8-bit)		(8-bit)

(UP COUNTING RELOAD VALUE)

Figure 5. Auto-Reload Mode Up/Down Counter (DCEN = 1)

6.4.2. Programmable Clock-Output

In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 6) . The input clock increments TL2 at frequency FOSC/2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers :

Fosc

Clock –OutFrequency = --------------------------------------------------------------------------------------

4 ´ (65536 –RCAP2H ¤ RCAP2L)

For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz (FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0).

Timer 2 is programmed for the clock-out mode as follows:

∙Set T2OE bit in T2MOD register.

∙Clear C/T2 bit in T2CON register.

∙Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.

∙Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application.

∙To start the timer, set TR2 run control bit in T2CON register.

Rev. C - 06 March, 2001

19

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers.

XTAL1 :2

(:1 in X2 mode)

TR2

T2CON reg TL2 TH2 (8-bit) (8-bit)

OVERFLOW

RCAP2L RCAP2H (8-bit) (8-bit)

Toggle

T2

Q D

T2OE

T2MOD reg

	T2EX	EXF2	TIMER 2
			INTERRUPT

T2CON reg

EXEN2

T2CON reg

Figure 6. Clock-Out Mode C/T2 = 0

20	Rev. C - 06 March, 2001

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

Table 6. T2CON Register

T2CON - Timer 2 Control Register (C8h)

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit Number

Bit

Description

Mnemonic

7

TF2

Timer 2 overflow Flag

Must be cleared by software.

Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

6

EXF2

Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.

When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)

Receive Clock bit

5

RCLK

Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.

Transmit Clock bit

4

TCLK

Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

3

EXEN2

Clear to ignore events on T2EX pin for timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to

clock the serial port.

Timer 2 Run control bit

2

TR2

Clear to turn off timer 2.

Set to turn on timer 2.

Timer/Counter 2 select bit

1

C/T2#

Clear for timer operation (input from internal clock system: FOSC).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.

Timer 2 Capture/Reload bit

0

CP/RL2#

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow.

Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.

Set to capture on negative transitions on T2EX pin if EXEN2=1.

Reset Value = 0000 0000b

Bit addressable

Rev. C - 06 March, 2001

21

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

Table 7. T2MOD Register

T2MOD - Timer 2 Mode Control Register (C9h)

7		6		5		4		3		2	1	0
-		-		-		-		-		-	T2OE	DCEN
Bit Number		Bit						Description
	Mnemonic
7	-		Reserved
				The value read from this bit is indeterminate. Do not set this bit.
6	-		Reserved
				The value read from this bit is indeterminate. Do not set this bit.
5	-		Reserved
				The value read from this bit is indeterminate. Do not set this bit.
4	-		Reserved
				The value read from this bit is indeterminate. Do not set this bit.
3	-		Reserved
				The value read from this bit is indeterminate. Do not set this bit.
2	-		Reserved
				The value read from this bit is indeterminate. Do not set this bit.
			Timer 2 Output Enable bit
1		T2OE		Clear to program P1.0/T2 as clock input or I/O port.
				Set to program P1.0/T2 as clock output.
			Down Counter Enable bit
0		DCEN		Clear to disable timer 2 as up/down counter.
				Set to enable timer 2 as up/down counter.

Reset Value = XXXX XX00b

Not bit addressable

22	Rev. C - 06 March, 2001

TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

6.5. Programmable Counter Array PCA

The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated

timer/counter which serves as the time base for an array of five compare/ capture modules. Its clock input
can be programmed to count any one of the following signals:
•	Oscillator frequency ÷ 12 (÷ 6 in X2 mode)
•	Oscillator frequency ÷ 4 (÷ 2 in X2 mode)

•Timer 0 overflow

•External input on ECI (P1.2)

Each compare/capture modules can be programmed in any one of the following modes:

•rising and/or falling edge capture,

•software timer,

•high-speed output, or

•pulse width modulator.

Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer", page 33).

When the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector.

The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O.

PCA component	External I/O Pin
16-bit Counter	P1.2	/ ECI
16-bit Module 0	P1.3	/ CEX0
16-bit Module 1	P1.4	/ CEX1
16-bit Module 2	P1.5	/ CEX2
16-bit Module 3	P1.6	/ CEX3
16-bit Module 4	P1.7	/ CEX4

The PCA timer is a common time base for all five modules (See Figure 7). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (See Table 8) and can be programmed to run at:

∙1/12 the oscillator frequency. (Or 1/6 in X2 Mode)

∙1/4 the oscillator frequency. (Or 1/2 in X2 Mode)

∙The Timer 0 overflow

∙The input on the ECI pin (P1.2)

Rev. C - 06 March, 2001

23