Artesyn MVME51005E Installation

Download

Page 1

MVME51005E Single Board Computer

Installation and Use

P/N: 6806800A38D July 2014

Page 2

Trademarks

Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc.© 2014 Artesyn Embedded Technologies, Inc. All other product or service names are the property of their respective owners.

Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

Java™ and all other Java-based marks are trademarks or registered trademarks of Oracle America, Inc. in the U.S. and other countries.

Microsoft®, Windows® and Windows Me® are registered trademarks of Microsoft Corporation; and Windows XP™ is a trademark of Microsoft Corporation.

PICMG®, CompactPCI®, AdvancedTCA™ and the PICMG, CompactPCI and AdvancedTCA logos are registered trademarks of the PCI Industrial Computer Manufacturers Group.

UNIX® is a registered trademark of The Open Group in the United States and other countries.

Notice

While reasonable efforts have been made to assure the accuracy of this document, Artesyn assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Artesyn reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes.

Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to an Artesyn website. The text itself may not be published commercially in print or electronic form, edited, translated, or otherwise altered without the permission of Artesyn.

It is possible that this publication may contain reference to or information about Artesyn products (machines and programs), programming, or services that are not available in your country. Such references or information must not be construed to mean that Artesyn intends to announce such Artesyn products, programming, or services in your country.

Limited and Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Artesyn.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov. 1995) and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252.227-7014 (Jun. 1995).

Contact Address

Artesyn Embedded Technologies Artesyn Embedded Technologies

Marketing Communications

2900 S. Diablo Way, Suite 190

Tempe, Arizona 85282

Lilienthalstr. 17-19

85579 Neubiberg/Munich

Germany

Page 3

Contents

About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1 Hardware Preparation and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.1.1 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.1.2 Overview and Equipment Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.1.3 Unpacking Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.2 Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.2.1 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.2.2 Jumper Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.2.2.1 PMC/SBC (761/IPMC) Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.2.3 Installation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.3 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.3.1 PMC Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.3.2 Primary PMCspan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.3.3 Secondary PMCspan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.3.4 MVME5100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2 Switches and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.1 ABT/RST Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.1.1 Abort Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.1.2 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.2 Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.2.1 RST Indicator (DS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.2.2 CPU Indicator (DS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.3 Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.3.1 10/100BASE T Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.3.2 DEBUG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.3 System Powerup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.3.1 Initialization Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 4

Contents

3 PPCBug Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2 PPCBug Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2.1 Implementation and Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.3 Using PPCBug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.3.1 Hardware and Firmware Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.4 Default Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.4.1 CNFG - Configure Board Information Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.4.2 ENV - Set Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.4.2.1 Configuring the PPCBug Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.4.3 LED/Serial Startup Diagnostic Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.4.4 Configuring the VMEbus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.4.5 Firmware Command Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.5 Standard Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.5.1 Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.2 Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.3 Features Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.3.2 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.3.3 System Memory Controller and PCI Host Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.3.4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.3.4.1 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.3.4.2 ECC SDRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.3.5 P2 Input/Output (I/O) Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.3.6 Input/Output Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.3.6.1 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.3.6.2 VMEbus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.3.6.3 Asynchronous Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.3.6.4 Real-Time Clock & NVRAM & Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.3.6.5 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.3.6.6 Interrupt Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.3.6.7 IDSEL Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 5

Contents

5 RAM500 Memory Expansion Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.3.1 RAM500 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.3.2 SROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.4 RAM500 Module Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.5 RAM500 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.5.1 Bottom Side Memory Expansion Connector (P1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.6 RAM500 Programming Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.6.1 Serial Presence Detect (SPD) Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.1.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.2 Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.3 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6.3.1 IPMC761 Connector (J3) Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6.3.2 Memory Expansion Connector (J8) Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.3.3 PCI Expansion Connector (J25) Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

6.3.4 PCI Mezzanine Card (PMC) Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6.3.5 VMEbus Connectors P1 & P2 Pin Assignments (PMC mode). . . . . . . . . . . . . . . . . . . . . . . 109

6.3.6 VMEbus P1 & P2 Connector Pin Assignments (SBC Mode) . . . . . . . . . . . . . . . . . . . . . . . . 111

6.3.7 10 BaseT/100 BaseTx Connector Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.3.8 COM1 and COM2 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

7 Programming the MVME5100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

7.2 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

7.2.1 Processor Bus Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

7.2.1.1 Default Processor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

7.2.1.2 Processor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7.2.1.3 PCI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.2.1.4 VME Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 6

Contents

7.2.2 PCI Local Bus Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.2.3 VMEbus Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.3 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

7.3.1 PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

7.3.2 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

7.3.3 DMA Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

7.3.4 Sources of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

7.3.5 Endian Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.3.5.1 Processor/Memory Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.3.5.2 PCI Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

7.3.5.3 VMEbus Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

A Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

A.1 General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

A.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

A.3 Cooling Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

A.4 EMC Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

B Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

B.1 Solving Startup Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

C Thermal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

C.1 Thermally Significant Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

C.2 Component Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

C.2.1 Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

C.2.2 Measuring Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

C.2.3 Measuring Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

C.2.4 Measuring Local Air Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

D Related Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

D.1 Artesyn Embedded Technologies - Embedded Computing Documentation . . . . . . . . . . . . . . .147

D.2 Manufacturer’s Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

D.3 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 7

List of Figures

Figure 1-1 MVME5100-Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 1-2 MVME5100 Installation and Removal From a VMEbus Chassis . . . . . . . . . . . . . . . . . 29

Figure 1-3 Typical PMC Module Placement on an MVME5100 . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 1-4 PMCspan16E-010 Installation on a PMCspan16E-002 . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 2-1 Boot-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 4-1 MVME5100 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 5-1 RAM500 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 7-1 VMEbus Master Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 7-2 MVME5100 Interrupt Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure C-1 Thermally Significant Components on the MVME5100 SBC - Primary Side . . . . . 142

Figure C-2 Thermally Significant Components on the IPMC761 Module - Primary Side . . . . 143

Figure C-3 Mounting a Thermocouple Under a Heatsin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure C-4 Measuring Local Air Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 8

List of Figures

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 9

List of Tables

Table 1-1 Manually Configured Headers/Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 3-1 Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 3-2 Diagnostic Test Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 4-1 MVME5100 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 5-1 RAM500 Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 5-2 RAM500 SDRAM Memory Size Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 5-3 RAM500 Bottom Side Connector (P1)Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 6-1 IPMC761 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 6-2 RAM500 Bottom Side Connector (P1)Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 6-3 RAM500 Bottom Side Connector (P1)Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 6-4 PMC Slot 1 Connector (J11) Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 6-5 PMC Slot 1 Connector (J12) Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 6-6 PMC Slot 1 Connector (J14) Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 6-7 Pin Assignments for Connector P2 in PMC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 7-1 Default Processor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 7-2 Suggested CHRP Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 7-3 Hawk PPC Register Values for Suggested Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 7-4 PCI Arbitration Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 7-5 Devices Affected by Various Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table A-1 MVME5100 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table A-2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table B-1 Troubleshooting Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table C-1 Thermally Significant Components on the MVME5100 Single Board Computer . . . . . . .139

Table C-2 Thermally Significant Components on the IPMC761 Module . . . . . . . . . . . . . . . . . . . . . . . . 140

Table D-1 Artesyn Embedded Technologies - Embedded Computing Publications . . . . . . . . . . . . . 147

Table D-2 Manufacturers’ Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table D-3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 10

List of Tables

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 11

About this Manual

Overview of Contents

The MVME51005E Single Board Computer Installation and Use provides the information you will need to install and configure your MVME51005E Single Board Computer. It provides specific preparation and installation information and data applicable to the board will hereafter be referred to as the MVME5100.

The MVME5100 is a high-performance VME single board computer featuring the PowerPlus II architecture with a choice of processors—either the MPC7410 with AltiVec™ technology for algorithmic intensive computations or the low-power MPC750.

As of the printing date of this manual, the MVME5100 is available in the configurations shown below. Note: all models of the MVME5100 are available with either VME Scanbe front panel or IEEE 1101 compatible front panel handles.

Model Number Description

450MHz MCP750 Commercial Models

. The MVME51005E

MVME51005E-016x 450MHz MCP750, 512MB ECC SDRAM, 17MB Flash and

1MB L2 cache.

400 and 500 MHz MPC7410 Commercial Models

MVME51105E-216x 400MHz MPC7410, 512MB ECC SDRAM, 17MB Flash and

2MB L2 cache.

MVME51105E-226x 500 MHz MPC7410, 512MB ECC SDRAM, 17MB Flash and

2MB L2 cache

MVME712M Compatible I/O

IPMC7126E-002 Multifunction rear I/O PMC module; 8-bit SCSI, Ultra

Wide SCSI, one parallel port, three async and one sync/async serial port.

MVME712M6E Transition module connectors: One DB-25 sync/async

serial port, three DB-25 async serial ports, one AUI connector, one D-36 parallel port, and one 50-pin 8-bit SCSI; includes 3-row DIN P2 adapter module and cable.

MVME761 Compatible I/O

IPMC7616E-002 Multifunction rear I/O PMC module; 8-bit SCSI, one

parallel port, two async and two sync/async serial ports.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 12

About this Manual

MVME7616E-001 Transition module: Two DB-9 async serial port

MVME7616E-011 Transition module: Two DB-9 async serial port

SIM232DCE5E or DTE EIA-232 DCE or DTE Serial Interface Module.

Abbreviations

This document uses the following abbreviations:

Term Meaning

AAmpere

ANSI American National Standard Institute

BLT Block Transfer

CFM Cubic Feet per Minute

CMC Common Mezzanine Card

COM Communications

COP Common On-chip Processor

CPU Central Processing Unit

DDR Double Data Rate

About this Manual

°C Degree Celsius

DMA Direct Memory Access

DRAM Dynamic Random Access Memory

DUART Dual Universal Asynchronous Receiver/Transmitter

ECC Error Correction Code

EEPROM Electrically Erasable Programmable Read-Only Memory

FCC Federal Communications Commission

FIFO First In First Out

GB Gigabytes

Gbit Gigabit

Gbps Gigabits Per Second

GPCM General Purpose Chip select Machine

H/W Hardware

IEEE Institute of Electrical and Electronics Engineers

I2C Inter IC

JTAG Joint Test Access Group

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 15

Term Meaning

KB Kilobytes

KBAUD Kilo Baud

LBC Local Bus Controller

LED Light Emitting Diode

MB Megabytes

Mbps Megabits Per Second

MHz Megahertz

NAND (Not and) Flash that is used for storage

NOR (Not or) Flash that is used for executing code

OS Operating System

PCI Peripheral Component Interconnect

About this Manual

PCI-X Peripheral Component Interconnect -X

PIC Programmable Interrupt Controller

PIM PCI Mezzanine Card Input/Output Module

PMC PCI Mezzanine Card (IEEE P1386.1)

PLD Programmable Logic Device

QUART Quad Universal Asynchronous Receiver/Transmitter

RAM Random Access Memory

RGMII Reduced Gigabit Media Independent Interface

RTC Real-Time Clock

RTM Rear Transition Module

SBC Single Board Computer

SDRAM Synchronous Dynamic Random Access Memory

SMT Surface Mount Technology

SODIMM Small-Outline Dual In-line Memory Module

SPD Serial Presence Detect

SoC System-on-Chip

SRAM Static Random Access Memory

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 16

About this Manual

Term Meaning

S/W Software

TSEC Three-Speed Ethernet Controller

2eSST Two edge Source Synchronous Transfer

UART Universal Asynchronous Receiver/Transmitter

V Volts

VIO Input/Output Voltage

VITA VMEbus International Trade Association

VME Versa Module Eurocard

VPD Vital Product Data

W Watts

About this Manual

Conventions

The following table describes the conventions used throughout this manual.

Notation Description

0x00000000 Typical notation for hexadecimal numbers (digits are

0b0000 Same for binary numbers (digits are 0 and 1)

bold Used to emphasize a word Screen Used for on-screen output and code related elements

Courier + Bold Used to characterize user input and to separate it

Reference Used for references and for table and figure

File > Exit Notation for selecting a submenu

<text> Notation for variables and keys

[text] Notation for software buttons to click on the screen

0 through F), for example used for addresses and offsets

or commands in body text

from system output

descriptions

and parameter description

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 17

About this Manual

Notation Description

... Repeated item for example node 1, node 2, ..., node

.. Ranges, for example: 0..4 means one of the integers

| Logical OR

Omission of information from example/command that is not necessary at the time being

0,1,2,3, and 4 (used in registers)

Indicates a hazardous situation which, if not avoided, could result in death or serious injury

Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury

Indicates a property damage message

No danger encountered. Pay attention to important information

Summary of Changes

Part Number Publication Date Description

6806800A38D July 2014 Re- branded to Artesyn template.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 18

About this Manual

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 19

Hardware Preparation and Installation

1.1 Introduction

This chapter provides information on hardware preparation and installation for the MVME5100 Series of Single Board Computers.

Note: Unless otherwise specified, the designation “MVME5100” refers to all models of the MVME5100-series Single Board Computers.

1.1.1 Getting Started

The following subsections include information helpful in preparing your equipment. It includes and overview of the MVME5100, any equipment needed to complete the installation, and unpacking instructions.

Chapter 1

1.1.2 Overview and Equipment Requirements

The MVME5100 interfaces to a VMEbus system via its P1 and P2 connectors and contains two IEEE 1386.1 PCI Mezzanine Card (PMC) Slots. The PMC Slots are 64-bit and support both front and rear I/O.

Additionally, the MVME5100 is user configurable by setting on-board jumpers. Two I/O modes are possible: PMC mode or SBC mode (also called 761 or IPMC mode). The SBC mode uses the IPMC712 I/O PMC and the MVME712M Transition Module, or the IPMC761 I/O PMC and the MVME761 Transition Module. The SBC mode is backwards compatible with the MVME761 transition card and the P2 adapter card (excluding PMC I/O routing) used on the MVME2600/2700 product. This mode is accomplished by configuring the on-board jumpers and by attaching an IPMC761 PMC in PMC slot 1. Secondary Ethernet is configured to the rear.

PMC mode is backwards compatible with the MVME2300/MVME2400 and is accomplished by simply configuring the on-board jumpers.

The following equipment list is appropriate for use in an MVME5100 system:

1. PMCspan PCI expansion mezzanine module (mates with MVME5100)

2. Peripheral Component Interconnect (PCI) Mezzanine Cards (PMCs) (installed on an MVME5100 board)

3. RAM500 memory mezzanine modules (installed on an MVME5100 board)

4. VME system enclosure

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 20

Hardware Preparation and Installation

5. System console terminal

6. Disk drives (and/or other I/O) and controllers

7. Operating system (and/or application software)

1.1.3 Unpacking Instructions

Avoid touching areas of integrated circuitry; static discharge can damage these circuits.

Artesyn strongly recommends that you use an antistatic wrist strap and conductive foam pad when installing or upgrading a system. Electronic components, such as disk drives, computer boards and memory modules, can be extremely sensitive to electrostatic discharge (ESD). After removing the component from its protective wrapper or from the system, place the component on a grounded, static-free, and adequately protected working surface. Do not slide the component over any surface. In the case of a Printed Circuit Board (PCB), place the board with the component side facing up. If an ESD station is not available, you can avoid damage resulting from ESD by wearing an anti-static wrist strap (available locally) that is attached to an active electrical ground.

Note: A system chassis may not be a suitable grounding source if it is unplugged.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 21

1.2 Preparation

This section includes subsections on hardware configuration that may need to be performed immediately before and after board installation. It includes a brief reminder on setting bits in control registers, setting jumpers for the appropriate configuration, and other VME data considerations.

1.2.1 Hardware Configuration

To produce the desired board configuration and to ensure proper operation of the MVME5100, it may be necessary to perform certain modifications before and after installation. The following paragraphs discuss the preparation of the MVME5100 hardware components prior to installing them into a chassis and connecting them.

A software readable header/ switch register (S1) is available on the MVME5100. This switch is not defined by the hardware and it is shipped in the OFF position, as are all the switches on this board. This S1 switch is available for user-specific configuration needs via the control registers.

Hardware Preparation and Installation

The MVME5100 provides software control over most of its options by setting bits in control registers. After installing it in a system, you can modify its configuration. For additional information on the board’s control registers, refer to the MVME5100 Single Board Computer Programmer's Reference Guide listed in Appendix D, Related Documentation, on page 147

It is important to note that some options are not software-programmable. These specific options are controlled through manual installation or removal of jumpers, and in some cases, the addition of other interface modules on the MVME5100. The following table lists the manually configured jumpers on the MVME5100, and their default settings.

If you are resetting the board jumpers from their default settings, it is important to verify that all settings are reset properly. For example, the SBC mode requires setting jumpers 4, 10 and 17 for rear Ethernet functions, but it also requires resetting jumpers J6 and J20. Neglecting to reset J6 and J20 could damage or destroy subsequent PMCs or PrPMCs installed on the base board at power-up.

Table 1-1 Manually Configured Headers/Jumpers

Jumper Description Setting Default

J1 RISCWatch Header None (Factory Use

Only)

MVME51005E Single Board Computer Installation and Use (6806800A38D)

N/A

Page 22

Hardware Preparation and Installation

Table 1-1 Manually Configured Headers/Jumpers

Jumper Description Setting Default

J2 PAL Programming

Header

None (Lab Use Only) N/A

J4 Ethernet Port 2

Selection

(see also J10/J17)

J6, J20 Operation Mode

(Set Both Jumpers)

J7 Flash Memory

Selection

J15 System Controller

(VME)

J16 Soldered Flash

Protection

For P2 Ethernet Port 2:

Pins 1,2; 3,4; 5,6; 7,8 (set when in SBC mode, also called 761 mode)

For Front Panel Ethernet Port 2:

No Jumpers Installed

Pins 1, 2 for PMC Mode PMC

Pins 2, 3 for SBC Mode*

Pins 1, 2 for Soldered Bank A

Pins 2, 3 for Socketed Bank B

Pins 1, 2 for No SCON

Pins 2, 3 for Auto SCON

No Jumper for ALWAYS SCON

Pins 1, 2 Enables Programming of Flash

Programming of the upper 64KB of Flash

Jumper

Installed

(front panel)

Mode

Socketed

Bank B

Auto

SCON

Flash

Prog.

Enabled1Pins 2, 3 Disables

Refer to the section titled Jumper Settings on the next page for additional information.

Note: Write protects only outer two 8K boot sectors. Refer to on Flash Memory on page 71 for an complete explanation.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 23

1.2.2 Jumper Settings

Prior to performing the installation instructions, you must ensure that the jumpers are set properly for your particular configuration. For example, if you are using an IPMC761/MVME761 or IPMC712/MVME712 combination in conjunction with the MVME5100, you must reset the jumpers for the SBC mode (jumpers J4, J6, J10, J17 and J20). These are factory configured for the PMC mode. Verify all settings according to the previous table and follow the instructions below if applicable.

Hardware Preparation and Installation

1.2.2.1 PMC/SBC (761/IPMC) Mode Selection

There are five headers associated with the selection of the PMC or SBC mode: J4, J6 J10, J17 and J20. Three of these headers are responsible for secondary Ethernet I/O (J4, J10 and J17) to either the front panel (PMC mode), or to the P2 connector via J4 (SBC mode). The other two headers (J6 and J20) ensure proper routing of +/- 12V signal routing. The MVME5100 is set at the factory for front panel I/O: PMC mode (see Table 1-1). The SBC mode should only be selected when using one of the IPMC-7xx modules in conjunction with the corresponding MVME7xx transition module.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 24

Hardware Preparation and Installation

1.2.3 Installation Considerations

The MVME5100 draws power from the VMEbus backplane connectors P1 and P2. Connector P2 is also used for the upper 16 bits of data in 32-bit transfers, and for the upper 8 address lines in extended addressing mode. The MVME5100 will not function properly without its main board connected to VMEbus backplane connectors P1 and P2.

Whether the MVME5100 operates as a VMEbus master or as a VMEbus slave, it is configured for 32 bits of address and 32 bits of data (A32/D32). However, it handles A16 or A24 devices in the appropriate address ranges. D8 and/or D16 devices in the system must be handled by the processor software.

If the MVME5100 tries to access off-board resources in a nonexistent location and if the system does not have a global bus time-out, the MVME5100 waits indefinitely for the VMEbus cycle to complete. This will cause the system to lock up. There is only one situation in which the system might lack this global bus time-out; that is when the MVME5100 is not the system controller and there is no global bus time-out elsewhere in the system.

Note: Software can also disable the bus timer by setting the appropriate bits in the Universe II VMEbus interface.

Multiple MVME5100 boards may be installed in a single VME chassis; however, each must have a unique VMEbus address. Other MPUs on the VMEbus can interrupt, disable, communicate with, and determine the operational status of the processor(s).

1.3 Installation

This section discusses the installation of PMCs onto the MVME5100, installation of PMCspan modules onto the MVME5100, and the installation of the MVME5100 into a VME chassis.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 25

Hardware Preparation and Installation

Note: If you have ordered one or more of the optional RAM500 memory mezzanine boards for the MVME5100, ensure that they are installed on the board prior to proceeding. If they have not been installed by the factory, and you are installing them yourself, please refer to Chapter

5, RAM500 Memory Expansion Module, for installation instructions. It is recommended that the

memory mezzanine modules be installed prior to installing other board accessories, such as PMCs, IPMCs or transition modules.

Figure 1-1 MVME5100-Layout

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 26

Hardware Preparation and Installation

1.3.1 PMC Modules

PMC modules mount on top of the MVME5100. Perform the following steps to install a PMC module on your MVME5100.

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing and adjusting.

Inserting or removing modules with power applied may result in damage to module components. Avoid touching areas of integrated circuitry, static discharge can damage these circuits.

Note: This procedure assumes that you have read the user’s manual that came with your PMCs.

1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to an electrical ground. Note that the system chassis may not be grounded if it is unplugged. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2. Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the VME modules.

3. If the MVME5100 has already been installed in a VMEbus card slot, carefully remove it as shown in and place it with connectors P1 and P2 facing you.

4. Remove the filler plate(s) from the front panel of the MVME5100.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 27

Hardware Preparation and Installation

5. Align the PMC module’s mating connectors to the MVME5100’s mating connectors and press firmly into place.

6. Insert the appropriate number of Phillips screws (typically 4) from the bottom of the MVME5100 into the standoffs on the PMC module and tighten the screws (refer toFigure

1-2)

Figure 1-2 MVME5100 Installation and Removal From a VMEbus Chassis

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 28

Hardware Preparation and Installation

Figure 1-3 Typical PMC Module Placement on an MVME5100

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 29

1.3.2 Primary PMCspan

To install a PMCspan16E-002 PCI expansion module on your MVME5100, perform the following steps while referring to the figure on the next page:

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing and adjusting.

Inserting or removing modules with power applied may result in damage to module components. Avoid touching areas of integrated circuitry, static discharge can damage these circuits.

Hardware Preparation and Installation

Note: This procedure assumes that you have read the user’s manual that was furnished with your PMCspan and that you have installed the selected PMC modules on to your PMCspan according to the instructions provided in the PMCspan and PMC manuals.

3. If the MVME5100 has already been installed in a VMEbus card slot, carefully remove it as shown inFigure 1-3 and place it with connectors P1 and P2 facing you.

4. Attach the four standoffs to the MVME5100. For each standoff:

 Insert the threaded end into the standoff hole at each corner of the MVME5100.

 Thread the locking nuts into the standoff tips and tighten.

5. Place the PMCspan on top of the MVME5100. Align the mounting holes in each corner to the standoffs and align PMCspan connector P4 with MVME5100 connector J25.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 30

Hardware Preparation and Installation

1.3.3 Secondary PMCspan

The PMCspan16E-010 PCI expansion module mounts on top of a PMCspan16E-002 PCI expansion module. To install a PMCspan-010 on your MVME5100, perform the following steps while referring to the figure on the next page:

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing and adjusting.

Inserting or removing modules with power applied may result in damage to module components. Avoid touching areas of integrated circuitry, static discharge can damage these circuits.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 31

Hardware Preparation and Installation

Note: This procedure assumes that you have read the user’s manual that was furnished with the PMCspan, and that you have installed the selected PMC modules on your PMCspan according to the instructions provided in the PMCspan and PMC manuals.

Figure 1-4 PMCspan16E-010 Installation on a PMCspan16E-002

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 32

Hardware Preparation and Installation

3. If the Primary PMC Carrier Module and MVME5100 assembly is already installed in the VME chassis, carefully remove it as shown in Figure Figure 1-3 and place it with connectors P1 and P2 facing you.

4. Remove four screws (Phillips type) from the standoffs in each corner of the primary PCI expansion module.

5. Attach the four standoffs from the PMCspan-010 mounting kit to the PMCspan-002 by screwing the threaded male portion of the standoffs in the locations where the screws were removed in the previous step.

6. Place the PMCspan-010 on top of the PMCspan-002. Align the mounting holes in each corner to the standoffs and align PMCspan-010 connector P3 with PMCspan-002 connector J3.

7. Gently press the two PMCspan modules together and verify that P3 is fully seated in J3.

8. Insert the four screws (Phillips type) through the holes at the corners of PMCspan-010 and into the standoffs on the primary PMCspan-002. Tighten screws securely.

Note: The screws have two different head diameters. Use the screws with the smaller heads on the standoffs next to VMEbus connectors P1 and P2.

1.3.4 MVME5100

Before installing the MVME5100 into your VME chassis, ensure that the jumpers are configured properly. This procedure assumes that you have already installed the PMCspan(s) and any PMCs that you have selected.

Perform the following steps to install the MVME5100 in your VME chassis:

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing and adjusting.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 33

Hardware Preparation and Installation

Inserting or removing modules with power applied may result in damage to module components. Avoid touching areas of integrated circuitry, static discharge can damage these circuits.

3. Remove the filler panel from the VMEbus chassis card slot where you are going to install the MVME5100. If you have installed one or more PMCspan PCI expansion modules onto your MVME5100, you will need to remove filler panels from one additional card slot for each PMCspan, above the card slot for the MVME5100.

 If you intend to use the MVME5100 as system controller, it must occupy the left-most

card slot (slot 1). The system controller must be in slot 1 to correctly initiate the busgrant daisy-chain and to ensure proper operation of the IACK daisy-chain driver.

 If you do not intend to use the MVME5100 as system controller, it can occupy any

unused card slot.

4. Slide the MVME5100 (and PMCspans if used) into the selected card slot(s). Verify that the module or module(s) seated properly in the P1 and P2 connectors on the chassis backplane. Do not damage or bend connector pins.

5. Secure the MVME5100 (and PMCspans if used) in the chassis with the screws in the top and bottom of its front panel and verify proper contact with the transverse mounting rails to minimize RF emissions.

Note: Some VME backplanes (such as those used in Artesyn Modular Chassis systems) have an auto-jumpering feature for automatic propagation of the IACK and BG signals. The step immediately below does not apply to such backplane designs.

6. On the chassis backplane, remove the INTERRUPT ACKNOWLEDGE (IACK) and BUS GRANT (BG) jumpers from the header for the card slots occupied by the MVME5100 and any PMCspan modules.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 34

Hardware Preparation and Installation

7. If you intend to use PPCbug interactively, connect the terminal that is to be used as the PPCbug system console to the DEBUG port on the front panel of the MVME5100.

Note: In normal operation, the host CPU controls MVME5100 operation via the VMEbus Universe registers.

8. Replace the chassis or system cover(s) and cable peripherals to the panel connectors as required.

9. Reconnect the system to the AC or DC power source and turn the system power on.

10. The MVME5100’s green CPU LED indicates activity as a set of confidence tests is run, and the debugger prompt PPC6-Bug> appears.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 35

Operation

2.1 Introduction

This chapter provides operating instructions for the MVME5100 Single Board Computer. It includes necessary information about powering up the system along with the functionality of the switches, status indicators and I/O ports on the front panels of the board.

2.2 Switches and Indicators

The front panel of the MVME5100, as shown in Figure 1-1, incorporates one dual function toggle switch (ABT/RST) and two Light-Emitting Diode (LED) status indicators (BFL, CPU) located on the front panel.

2.2.1 ABT/RST Switch

Chapter 2

The ABT/RST switch operates in the following manner: if pressed for less than 5 seconds, the ABORT function is selected, if pressed for more than 5 seconds, the RESET function is selected. Each function is described below.

2.2.1.1 Abort Function

When toggled to ABT, the switch generates an interrupt signal to the processor. The interrupt is normally used to abort program execution and return control to the debugger firmware located in the processor and flash memory.

The interrupt signal reaches the processor via ISA bus interrupt line IRQ8. The interrupter connected to the ABORT switch is an edge-sensitive circuit, filtered to remove switch bounce.

2.2.1.2 Reset Function

When toggled to RST, the switch resets all onboard devices. To generate a reset, the switch must be depressed for more than five seconds.

The on-board Universe ASIC includes both a global and a local reset driver. When the ASIC operates as the System Controller, the reset driver provides a global system reset by asserting the SYSRESET# signal.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 36

Operation

Additionaly, when the MVME5100 is configured as a System Controller (SCON), a SYSRESET# signal may be generated by toggling the ABT/RST switch to RST, or by a power-up reset, or by a watchdog timeout, or by a control bit in the Miscellaneous Control Register (MISC_CTL) in the Universe ASIC.

Note: SYSRESET# remains asserted for at least 200 ms, as required by the VMEbus specification.

2.2.2 Status Indicators

There are two Light-Emitting Diode (LED) status indicators located on the MVME5100 front panel. They are labeled BFL and CPU.

2.2.2.1 RST Indicator (DS1)

The yellow BFL LED indicates board failure; this indicator is also illuminated during reset as an LED test. The BFL is set if the MODFAIL Register or FUSE Register is set. Refer to the MVME5100 Single Board Computer Programmer’s Reference Guide (V5100A/PG) for information on these registers.

2.2.2.2 CPU Indicator (DS2)

The green CPU LED indicates CPU activity.

2.2.3 Connectors

There are three connectors on the front panel of the MVME5100. Two are bottom-labeled 10/100BASE T and one is labeled DEBUG.

2.2.3.1 10/100BASE T Ports

The two RJ-45 ports labeled 10/100BASE T provide the 10BASE T/100BASE TX Ethernet LAN interface. These connectors are top-labeled with the designation LAN1 and LAN2.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 37

2.2.3.2 DEBUG Port

The RJ-45 port labeled DEBUG provides an RS232 serial communications interface, based on TL16C550 Universal Asynchronous Receiver/Transmitter (UART) controller chip. It is asynchronous only. For additional information on pin assignments, refer to Chapter 6, Pin

Assignments.

The DEBUG port may be used for connecting a terminal to the MVME5100 to serve as the firmware console for the factory installed debugger, PPCBug. The port is configured as follows:

 8 bits per character

 1 stop bit per character

 Parity disabled (no parity)

 Baud rate = 9600 baud (default baud rate at power-up)

After power-up, the baud rate of the DEBUG port can be reconfigured by using the debugger’s Port Format (PF) command.

Operation

2.3 System Powerup

After you have verified that all necessary hardware preparation is done, that all connections were made correctly and that the installation is complete, you can power up the system.

2.3.1 Initialization Process

The MPU, hardware and firmware initialization process is performed by the PPCBug firmware upon system powerup or system reset. The firmware initializes the devices on the MVME5100 in preparation for booting an operating system.

The firmware is shipped from the factory with an appropriate set of defaults. Depending on your system and specific application, there may or may not be a need to modify the firmware configuration before you boot the operating system. If it is necessary, refer toChapter 3,

PPCBug Firmware for additional information on modifying firmware default parameters.

The following flowchart in Figure 2-1 shows the basic initialization process that takes place during MVME5100 system start-ups.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 38

Operation

For further information on PPCBug, refer to the following:

 Chapter 3, PPCBug Firmware

 Appendix B, Troubleshooting

 Appendix D, Related Documentation

Figure 2-1 Boot-Up Sequence

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 39

PPCBug Firmware

3.1 Introduction

The PPCBug firmware is the layer of software just above the hardware. The firmware provides the proper initialization for the devices on the MVME5100 upon powerup or reset.

This chapter describes the basics of the PPCBug and its architecture. It also describes the monitor (interactive command portion of the firmware), and provides information on using the PPCBug debugger and the special commands. A complete list of PPCBug commands is also provided.

For full user information about PPCBug, refer to the PPCBug Firmware Package User’s Manual and the PPCBug Diagnostics Manual, listed inAppendix D, Related Documentation.

3.2 PPCBug Overview

Chapter 3

The PPCBug debugger firmware is a powerful evaluation and debugging tool for systems built around Motorola microprocessor. Facilities are available for loading and executing user programs under complete operator control for system evaluation. The PPCBug provides a high degree of functionality, user friendliness, portability and ease of maintenance.

The PPCBug also achieves its portability because it was written entirely in the C programming language, except where necessary to use assembler functions.

PPCBug includes commands for:

 Display and modification of memory

 Breakpoint and tracing capabilities

 A powerful assembler and disassembler useful for patching programs

 A self-test at powerup feature which verifies the integrity of the system

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 40

PPCBug Firmware

PPCBug consists of three parts:

 A command-driven, user-interactive software debugger, described in the PPCBug

Firmware Package User’s Manual, listed in Appendix D, Related Documentation (hereafter referred to as “debugger” or “PPCBug”).

 A command-driven diagnostics package for the MVME5100 hardware (hereafter referred

to as “diagnostics”). The diagnostics package is described in the PPCBug Diagnostics Manual, listed in Appendix D, Related Documentation.

 A user interface or debug/diagnostics monitor that accepts commands from the system

console terminal.

When using PPCBug, you operate out of either the debugger directory or the diagnostic directory.

 If you are in the debugger directory, the debugger prompt PPC6-Bug> is displayed and you

have all of the debugger commands at your disposal.

 If you are in the diagnostic directory, the diagnostic prompt PPC6-Diag> is displayed and

you have all of the diagnostic commands at your disposal as well as all of the debugger commands.

Because PPCBug is command-driven, it performs its various operations in response to user commands entered at the keyboard. When you enter a command, PPCBug executes the command and the prompt reappears. However, if you enter a command that causes execution of user target code (for example, GO), then control may or may not return to PPCBug, depending on the outcome of the user program.

3.2.1 Implementation and Memory Requirements

PPCBug is written largely in the C programming language, providing benefits of portability and maintainability. Where necessary, assembly language has been used in the form of separately compiled program modules containing only assembler code.

Physically, PPCBug is contained in two socketed 32-pin PLCC Flash devices that together provide 1MB of storage. The executable code is checksummed at every power-on or reset firmware entry. The result (which includes a precalculated checksum contained in the flash devices), is verified against the expected checksum.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 41

PPCBug requires a maximum of 768KB of read/write memory. The debugger allocates this space from the top of memory. For example, a system containing 64MB (0x04000000) of read/write memory will place the PPCBug memory locations 0x03F40000 to 0x3FFFFFF. Additionally, the first 1MB of DRAM is reserved for the exception vector table and stack.

3.3 Using PPCBug

PPCBug is command-driven; it performs its various operations in response to commands that you enter at the keyboard. When the PPC6-Bug> prompt appears on the screen, the debugger is ready to accept debugger commands. When the PPC6-Diag> prompt appears on the screen, the debugger is ready to accept diagnostics commands. To switch from one mode to the other, enter SD.

What you enter is stored in an internal buffer. Execution begins only after you press the Return or Enter key. This allows you to correct entry errors, if necessary, with the control characters described in the PPCBug Firmware Package User’s Manual, listed in Appendix D, Related

Documentation.

PPCBug Firmware

After the debugger executes the command, the prompt reappears. However, depending on what the user program does, if the command causes execution of a user target code (that is, GO), then control may or may not return to the debugger.

For example, if a breakpoint has been specified, then control returns to the debugger when the breakpoint is encountered during execution of the user program. Alternately, the user program could return to the debugger by means of the System Call Handler routine RETURN (described in the PPCBug Firmware Package User’s Manual). For more about this, refer to the GD, GO and GT command descriptions in the PPCBug Firmware Package User’s Manual, listed in Appendix

D, Related Documentation.

A debugger command is made up of the following parts:

 The command name, either uppercase or lowercase (for example, MD or md)

 Any required arguments, as specified by command

 At least one space before the first argument. Precede all other arguments with either a

space or comma

 One or more options. Precede an option or a string of options with a semicolon (;). If no

option is entered, the command’s default option conditions are used.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 42

PPCBug Firmware

3.3.1 Hardware and Firmware Initialization

The debugger performs the hardware and firmware initialization process. This process occurs each time the MVME5100 is reset or powered up. The steps listed below are a high-level outline; be aware that not all of the detailed steps are listed.

1. Sets MPU.MSR to known value.

2. Invalidates the MPU's data/instruction caches.

3. Clears all segment registers of the MPU.

4. Clears all block address translation registers of the MPU.

5. Initializes the MPU-bus-to-PCI-bus bridge device.

6. Initializes the PCI-bus-to-ISA-bus bridge device.

7. Calculates the external bus clock speed of the MPU.

8. Delays for 750 milliseconds.

9. Determines the CPU base board type.

10. Sizes the local read/write memory (that is, DRAM).

11. Initializes the read/write memory controller. Sets base address of memory to 0x00000000.

12. Retrieves the speed of read/write memory. Initializes the read/write memory controller with the speed of read/write memory.

13. Initializes the read/write memory controller with the speed of read/write memory.

14. Retrieves the speed of read only memory (that is, Flash).

15. Initializes the read only memory controller with the speed of read only memory.

16. Enables the MPU's instruction cache.

17. Copies the MPU's exception vector table from 0xFFF00000 to 0x00000000.

18. Verifies MPU type.

19. Enables the superscalar feature of the MPU (superscalar processor boards only).

20. Verifies the external bus clock speed of the MPU.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 43

PPCBug Firmware

21. Determines the debugger's console/host ports and initializes the PC16550A.

22. Displays the debugger's copyright message.

23. Displays any hardware initialization errors that may have occurred.

24. Checksums the debugger object and displays a warning message if the checksum failed to verify.

25. Displays the amount of local read/write memory found.

26. Verifies the configuration data that is resident in NVRAM and displays a warning message if the verification failed.

27. Calculates and displays the MPU clock speed, verifies that the MPU clock speed matches the configuration data, and displays a warning message if the verification fails.

28. Displays the BUS clock speed, verifies that the BUS clock speed matches the configuration data, and displays a warning message if the verification fails.

29. Probes PCI bus for supported network devices.

30. Probes PCI bus for supported mass storage devices.

31. Initializes the memory/IO addresses for the supported PCI bus devices.

32. Executes Self-Test, if so configured. (Default is no Self-Test).

33. Extinguishes the board fail LED, if Self-Test passed and outputs any warning messages.

34. Executes boot program, if so configured. (Default is no boot).

35. Executes the debugger monitor (that is, issues the PPC6-Bug> prompt).

3.4 Default Settings

The following sections provide information pertaining to the firmware settings of the MVME5100. Default (factory set) Environment (ENV) commands are provided to inform you on how the MVME5100 was configured at the time it left the factory.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 44

PPCBug Firmware

3.4.1 CNFG - Configure Board Information Block

Use this command to display and configure the Board Information Block, which is resident within the NVRAM. This data block contains various elements detailing specific operational parameters of the MVME5100. The structure for the board is shown in the following example.

Board (PWA) Serial Number = MOT00xxxxxxx

Board Identifier = MVME5100

Artwork (PWA) Identifier = 01-W3518FxxB

MPU Clock Speed = 450

Bus Clock Speed = 100

Ethernet Address = 0001AF2A0A57

Primary SCSI Identifier = 07

System Serial Number = nnnnnnnn

System Identifier = Artesyn MVME5100

License Identifier = nnnnnnnn

The Board Information Block parameters shown above are left-justified character (ASCII) strings padded with space characters.

The Board Information Block is factory-configured before shipment. There is no need to modify block parameters unless the NVRAM is corrupted.

Refer to the PPCBug Firmware Package User's Manual, listed in Appendix D, Related Documentation for a description of CNFG and examples.

3.4.2 ENV - Set Environment

Use the ENV command to view and/or configure interactively all PPCBug operational parameters that are kept in Non-Volatile RAM (NVRAM).

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 45

Refer to the PPCBug Firmware Package User's Manual for a description of the use of ENV. Additional information on registers in the Universe ASIC that affect these parameters is contained in your MVME5100 Programmer’s Reference Guide, listed in Appendix D, Related

Documentation.

Listed and described below are the parameters that you can configure using ENV. The default values shown were those in effect when this publication went to print.

3.4.2.1 Configuring the PPCBug Parameters

The parameters that can be configured using ENV are:

Bug or System environment [B/S] = B?

B Bug is the mode where no system type of support is

displayed. However, system-related items are still available. (Default)

PPCBug Firmware

S System is the standard mode of operation, and is

the default mode if NVRAM should fail. System mode is defined in the PPCBug Firmware Package User's Manual listed in Appendix D, Related

Documentation.

Maximum Memory Usage (MB,0=AUTO) = 1?

This parameter specifies the maximum number of megabytes the bug is allowed to use. Allocation begins at the top of physical memory and expands downward as more memory is required until the maximum value is reached.

If a value of zero is specified, memory will continue to be increased as needed until half of the available memory is consumed (that is, 32MB in a 64MB system). This mode is useful for determining the full memory required for a specific configuration. Once this is determined, a hard value may be given to the parameter and it is guaranteed that no memory will be used over this amount.

The default value for this parameter is one.

Note: The bug does not automatically acquire all of the memory it is allowed. It accumulates memory as necessary in one megabyte blocks.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 46

PPCBug Firmware

Field Service Menu Enable [Y/N] = N?

Y Display the field service menu.

N Do not display the field service menu. (Default)

Remote Start Method Switch [G/M/B/N] = B?

The Remote Start Method Switch is used when the MVME5100 is cross-loaded from another VME-based CPU in order to start execution of the cross-loaded program.

G Use the Global Control and Status Register to pass and start

M Use the Multiprocessor Control Register (MPCR) in shared RAM to

B Use both the GCSR and the MPCR methods to pass and start

execution of the cross-loaded program.

pass and start execution of the cross-loaded program.

execution of the cross-loaded program. (Default)

N Do not use any Remote Start Method.

Probe System for Supported I/O Controllers [Y/N] = Y?

Y Accesses will be made to the appropriate system buses (for

example, VMEbus, local MPU bus) to determine the presence of supported controllers. (Default)

N Accesses will not be made to the VMEbus to determine the

presence of supported controllers.

Auto-Initialize of NVRAM Header Enable [Y/N] = Y?

Y NVRAM (PReP partition) header space will be initialized

automatically during board initialization, but only if the PReP partition fails a sanity check. (Default)

N NVRAM header space will not be initialized automatically during

board initialization.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 47

PPCBug Firmware

Network PReP-Boot Mode Enable [Y/N] = N?

Y Enable PReP-style network booting (same boot image from a

network interface as from a mass storage device).

N Do not enable PReP-style network booting. (Default)

Negate VMEbus SYSFAIL* Always [Y/N] = N?

Y Negate the VMEbus SYSFAIL* signal during board initialization.

N Negate the VMEbus SYSFAIL* signal after successful completion

or entrance into the bug command monitor. (Default)

SCSI Bus Reset on Debugger Startup [Y/N] = N?

Y Local SCSI bus is reset on debugger setup.

N Local SCSI bus is not reset on debugger setup. (Default)

Primary SCSI Bus Negotiations Type [A/S/N] = A?

Y Asynchronous SCSI bus negotiation. (Default)

S Synchronous SCSI bus negotiation.

N None.

Primary SCSI Data Bus Width [W/N] = N?

Y Wide SCSI (16-bit bus).

N Narrow SCSI (8-bit bus). (Default)

Secondary SCSI identifier = 07?

Select the identifier. (Default = 07.)

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 48

PPCBug Firmware

NVRAM Bootlist (GEV.fw-boot-path) Boot Enable [Y/N] = N?

Y Give boot priority to devices defined in the fw-boot-path global

N Do not give boot priority to devices listed in the fw-boot-path

Note: When enabled, the GEV boot takes priority over all other boots, including Autoboot and Network Boot.

NVRAM Bootlist (GEV.fw-boot-path) Boot at power-up only [Y/N] = N?

Y Give boot priority to devices defined in the fw-boot-path GEV at

N Give powerup boot priority to devices listed in the fw-boot-path

environment variable (GEV).

GEV. (Default)

powerup reset only.

GEV at any reset. (Default)

NVRAM Bootlist (GEV.fw-boot-path) Boot Abort Delay = 5?

The time (in seconds) that a boot from the NVRAM boot list will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the BREAK key. The time value is from 0-255 seconds. (Default = 5 seconds)

Auto Boot Enable [Y/N] = N?

Y The Autoboot function is enabled.

N The Autoboot function is disabled. (Default)

Auto Boot at powerup only [Y/N] = N?

Y Autoboot is attempted at powerup reset only.

N Autoboot is attempted at any reset. (Default)

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 49

PPCBug Firmware

Auto Boot Scan Enable [Y/N] = Y?

Y If Autoboot is enabled, the Autoboot process attempts to boot

from devices specified in the scan list (for example, FDISK/CDROM/TAPE/HDISK). (Default)

N If Autoboot is enabled, the Autoboot process uses the Controller

LUN and Device LUN to boot.

Auto Boot Scan Device Type List = FDISK/CDROM/TAPE/HDISK?

This is the listing of boot devices displayed if the Autoboot Scan option is enabled. If you modify the list, follow the format shown above (uppercase letters, using forward slash as separator).

Auto Boot Controller LUN = 00?

Refer to the PPCBug Firmware Package User's Manual for a listing of disk/tape controller modules currently supported by PPCBug. (Default = 0x00)

Auto Boot Device LUN = 00?

Refer to the PPCBug Firmware Package User's Manual listed in Appendix D, Related

Documentation for a listing of disk/tape devices currently supported by PPCBug. (Default =

0x00)

Auto Boot Partition Number = 00?

Identifies which disk “partition” is to be booted, as specified in the PowerPC Reference Platform (PReP) specification. If set to zero, the firmware will search the partitions in order (1, 2, 3, 4) until it finds the first “bootable” partition. That is then the partition that will be booted. Other acceptable values are 1, 2, 3 or 4. In these four cases, the partition specified will be booted without searching.

Auto Boot Abort Delay = 7?

The time in seconds that the Autoboot sequence will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the BREAK key. The time value is from 0-255 seconds. (Default = 7 seconds)

Auto Boot Default String [NULL for an empty string] = ?

You may specify a string (filename) which is passed on to the code being booted. The maximum length of this string is 16 characters. (Default = null string)

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 50

PPCBug Firmware

ROM Boot Enable [Y/N] = N?

Y The ROMboot function is enabled.

N The ROMboot function is disabled. (Default)

ROM Boot at power-up only [Y/N] = Y?

Y ROMboot is attempted at power-up only. (Default).

N ROMboot is attempted at any reset.

ROM Boot Enable search of VMEbus [Y/N] = N?

Y VMEbus address space, in addition to the usual areas of memory,

N VMEbus address space will not be accessed by ROMboot.

will be searched for a ROMboot module.

(Default)

ROM Boot Abort Delay = 5?

The time (in seconds) that the ROMboot sequence will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the BREAK key. The time value is from 0-255 seconds. (Default = 5 seconds)

ROM Boot Direct Starting Address = FFF00000?

The first location tested when PPCBug searches for a ROMboot module. (Default = 0xFFF00000)

ROM Boot Direct Ending Address = FFFFFFFC?

The last location tested when PPCBug searches for a ROMboot module. (Default = 0xFFFFFFFC)

Network Auto Boot Enable [Y/N] = N?

Y The Network Auto Boot (NETboot) function is enabled.

N The NETboot function is disabled. (Default)

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 51

PPCBug Firmware

Network Auto Boot at power-up only [Y/N] = N?

Y NETboot is attempted at powerup reset only.

N NETboot is attempted at any reset. (Default)

Network Auto Boot Controller LUN = 00?

Refer to the PPCBug Firmware Package User's Manual, listed in Appendix D, Related

Documentation for a listing of network controller modules currently supported by PPCBug.

(Default = 0x00)

Network Auto Boot Device LUN = 00?

Refer to the PPCBug Firmware Package User's Manual, listed in Appendix D, Related

Documentation for a listing of network controller modules currently supported by PPCBug.

(Default = 0x00)

Network Auto Boot Abort Delay = 5?

The time in seconds that the NETboot sequence will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the BREAK key. The time value is from 0-255 seconds. (Default = 5 seconds)

Network Auto Boot Configuration Parameters Offset (NVRAM) = 00001000?

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 52

PPCBug Firmware

The address where the network interface configuration parameters are to be saved/retained in NVRAM; these parameters are the necessary parameters to perform an unattended network boot. A typical offset might be 0x1000, but this value is application-specific. (Default = 0x00001000)

If you use the NIOT debugger command, these parameters need to be saved somewhere in the offset range 0x00001000 through 0x000016F7. The NIOT parameters do not exceed 128 bytes in size. The setting of this ENV pointer determines their location. If you have used the same space for your own program information or commands, they will be overwritten and lost.

You can relocate the network interface configuration parameters in this space by using the ENV command to change the Network Auto Boot Configuration Parameters Offset from its default of 0x00001000 to the value you need to be clear of your data within NVRAM.

Memory Size Enable [Y/N] = Y?

Y Memory will be sized for SelfTest diagnostics. (Default)

N Memory will not be sized for SelfTest diagnostics.

Memory Size Starting Address = 00000000?

The default Starting Address is 0x00000000.

Memory Size Ending Address = 02000000?

The default Ending Address is the calculated size of local memory. If the memory start is changed from 0x0x00000000, this value will also need to be adjusted.

DRAM Speed in NANO Seconds = 15?

The default setting for this parameter will vary depending on the speed of the DRAM memory parts installed on the board. The default is set to the slowest speed found on the available banks of DRAM memory.

ROM Bank A Access Speed (ns) = 80?

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 53

PPCBug Firmware

This defines the minimum access speed for the Bank A Flash Device(s) in nanoseconds.

ROM Bank B Access Speed (ns) = 70?

This defines the minimum access speed for the Bank B Flash Device(s) in nanoseconds.

DRAM Parity Enable [On-Detection/Always/Never - O/A/N] = O?

O DRAM parity is enabled upon detection. (Default)

A DRAM parity is always enabled.

N DRAM parity is never enabled.

Note: This parameter also applies to enabling ECC for DRAM.

L2 Cache Parity Enable [On-Detection/Always/Never - O/A/N] = O?

O L2 Cache parity is enabled upon detection. (Default)

A L2 Cache parity is always enabled.

N L2 Cache parity is never enabled.

PCI Interrupts Route Control Registers (PIRQ0/1/2/3) = 0A0B0E0F?

Initializes the PIRQx (PCI Interrupts) route control registers in the IBC (PCI/ISA bus bridge controller). The ENV parameter is a 32-bit value that is divided by 4 fields to specify the values for route control registers PIRQ0/1/2/3. The default is determined by system type as shown: PIRQ0=0A, PIRQ1=0B, PIRQ2=0E, PIRQ3=0F.

3.4.3 LED/Serial Startup Diagnostic Codes

These codes can be displayed at key points in the initialization of the hardware devices. The codes are enabled by an ENV parameter.

Serial Startup Code Master Enable [Y/N]=N?

Should the debugger fail to come up to a prompt, the last code displayed will indicate how far the initialization sequence had progressed before stalling.

Serial Startup Code LF Enable [Y/N]=N?

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 54

PPCBug Firmware

A line feed can be inserted after each code is displayed to prevent it from being overwritten by the next code. This is also enabled by an ENV parameter:

The list of LED/serial codes is included in the section on MPU, Hardware, and Firmware Initialization found in Chapter 1 of the PPCBug Firmware Package User’s Manual, listed in

Appendix D, Related Documentation.

3.4.4 Configuring the VMEbus Interface

ENV asks the following series of questions to set up the VMEbus interface for the MVME5100. To perform this configuration, you should have a working knowledge of the Universe ASIC as described in your MVME5100 Programmer’s Reference Guide. Also, refer to the Tundra Universe II Users Manual, as listed in Appendix D, Related Documentation for a detailed description of VMEbus addressing. In general, the PCI slave images describe the VME master addresses, while the VMEbus slave describes the VME slave addresses.

VME3PCI Master Master Enable [Y/N] = Y?

Y Set up and enable the VMEbus Interface. (Default)

N Do not set up or enable the VMEbus Interface.

PCI Slave Image 0 Control = 00000000?

The configured value is written into the LSI0_CTL register of the Universe chip.

PCI Slave Image 0 Base Address Register = 00000000?

The configured value is written into the LSI0_BS register of the Universe chip.

PCI Slave Image 0 Bound Address Register = 00000000?

The configured value is written into the LSI0_BD register of the Universe chip.

PCI Slave Image 0 Translation Offset = 00000000?

The configured value is written into the LSI0_TO register of the Universe chip.

PCI Slave Image 1 Control = C0820000?

The configured value is written into the LSI1_CTL register of the Universe chip.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 55

PPCBug Firmware

PCI Slave Image 1 Base Address Register = 81000000?

The configured value is written into the LSI1_BS register of the Universe chip.

PCI Slave Image 1 Bound Address Register = A0000000?

The configured value is written into the LSI1_BD register of the Universe chip.

PCI Slave Image 1 Translation Offset = 80000000?

The configured value is written into the LSI1_TO register of the Universe chip.

PCI Slave Image 2 Control = C0410000?

The configured value is written into the LSI2_CTL register of the Universe chip.

PCI Slave Image 2 Base Address Register = A0000000?

The configured value is written into the LSI2_BS register of the Universe chip.

PCI Slave Image 2 Bound Address Register = A2000000?

The configured value is written into the LSI2_BD register of the Universe chip.

PCI Slave Image 2 Translation Offset = 500000000?

The configured value is written into the LSI2_TO register of the Universe chip.

PCI Slave Image 3 Control = C0400000?

The configured value is written into the LSI3_CTL register of the Universe chip.

PCI Slave Image 3 Base Address Register = AFFF0000?

The configured value is written into the LSI3_BS register of the Universe chip.

PCI Slave Image 3 Bound Address Register = B0000000?

The configured value is written into the LSI3_BD register of the Universe chip.

PCI Slave Image 3 Translation Offset = 50000000?

The configured value is written into the LSI3_TO register of the Universe chip.

VMEbus Slave Image 0 Control = E0F20000?

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 56

PPCBug Firmware

The configured value is written into the VSI0_CTL register of the Universe chip.

VMEbus Slave Image 0 Base Address Register = 00000000?

The configured value is written into the VSI0_BS register of the Universe chip.

VMEbus Slave Image 0 Bound Address Register = (Local DRAM Size)?

The configured value is written into the VSI0_BD register of the Universe chip. The value is the same as the Local Memory Found number already displayed.

VMEbus Slave Image 0 Translation Offset = 00000000?

The configured value is written into the VSI0_TO register of the Universe chip.

VMEbus Slave Image 1 Control = 00000000?

The configured value is written into the VSI1_CTL register of the Universe chip.

VMEbus Slave Image 1 Base Address Register = 00000000?

The configured value is written into the VSI1_BS register of the Universe chip.

VMEbus Slave Image 1 Bound Address Register = 00000000?

The configured value is written into the VSI1_BD register of the Universe chip.

VMEbus Slave Image 1 Translation Offset = 00000000?

The configured value is written into the VSI1_TO register of the Universe chip.

VMEbus Slave Image 2 Control = 00000000?

The configured value is written into the VSI2_CTL register of the Universe chip.

VMEbus Slave Image 2 Base Address Register = 00000000?

The configured value is written into the VSI2_BS register of the Universe chip.

VMEbus Slave Image 2 Bound Address Register = 00000000?

The configured value is written into the VSI2_BD register of the Universe chip.

VMEbus Slave Image 2 Translation Offset = 00000000?

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 57

PPCBug Firmware

The configured value is written into the VSI2_TO register of the Universe chip.

VMEbus Slave Image 3 Control = 00000000?

The configured value is written into the VSI3_CTL register of the Universe chip.

VMEbus Slave Image 3 Base Address Register = 00000000?

The configured value is written into the VSI3_BS register of the Universe chip.

VMEbus Slave Image 3 Bound Address Register = 00000000?

The configured value is written into the VSI3_BD register of the Universe chip.

VMEbus Slave Image 3 Translation Offset = 00000000?

The configured value is written into the VSI3_TO register of the Universe chip.

PCI Miscellaneous Register = 10000000?

The configured value is written into the LMISC register of the Universe chip.

Special PCI Slave Image Register = 00000000?

The configured value is written into the SLSI register of the Universe chip.

Master Control Register = 80C00000?

The configured value is written into the MAST_CTL register of the Universe chip.

Miscellaneous Control Register = 52060000?

The configured value is written into the MISC_CTL register of the Universe chip.

User AM Codes = 00000000?

The configured value is written into the USER_AM register of the Universe chip.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 58

PPCBug Firmware

3.4.5 Firmware Command Buffer

Firmware Command Buffer Enable = N?

Y Enables Firmware Command Buffer execution.

N Disables Firmware Command Buffer execution (Default).

Firmware Command Buffer Delay = 5?

Defines the number of seconds to wait before firmware begins executing the startup commands in the startup command buffer. During this delay, you may press any key to prevent the execution of the startup command buffer.

The default value of this parameter causes a startup delay of 5 seconds.

Firmware Command Buffer:

['NULL' terminates entry]?

The Firmware Command Buffer contents contain the BUG commands which are executed upon firmware startup.

BUG commands you place into the command buffer should be typed just as you enter the commands from the command line.

The string 'NULL' on a new line terminates the command line entries.

All PPCBug commands, except for the following, may be used within the command buffer: DU, ECHO, LO, TA, VE.

Note: Interactive editing of the startup command buffer is not supported. If changes are needed to an existing set of startup commands, a new set of commands with changes must be reentered.

3.5 Standard Commands

The individual debugger commands are listed in the following table. The commands are described in detail in the PPCBug Firmware Package User’s Manual, listed inAppendix D,

3.5.1 Diagnostics

The PPCBug hardware diagnostics are intended for testing and troubleshooting the MVME5100.

In order to use the diagnostics, you must switch to the diagnostic directory. You may switch between directories by using the SD (Switch Directories) command. You may view a list of the commands in the directory that you are currently in by using the HE (Help) command.

If you are in the debugger directory, the debugger prompt PPC6-Bug> is displayed, and all of the debugger commands are available. Diagnostics commands cannot be entered at the PPC6Bug> prompt.

If you are in the diagnostic directory, the diagnostic prompt PPC6-Diag> is displayed, and all of the debugger and diagnostic commands are available.

PPCBug’s diagnostic test groups are listed in Table 3-2. Note that not all tests are performed on the MVME5100. Using the HE command, you can list the diagnostic routines available in each test group. Refer to the PPCBug Diagnostics Manual, listed in Appendix D, Related

Documentation for complete descriptions of the diagnostic routines and instructions on how to

invoke them.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 64

PPCBug Firmware

Table 3-2 Diagnostic Test Groups

Test Group Description

EPIC EPIC Timers Test

PHB PCI Bridge Revision Test

RAM RAM Tests (various)

HOSTDMA DMA Transfer Test

RTC MK48Txx Real Time Clock Tests

UART Serial Input/Output Tests (Register, IRQ, Baud, & Loopback)

Z8536 Z8536 Counter/Timer Tests*

SCC Serial Communications Controller (Z85C230) Tests*

PAR8730x Parallel Interface (PC8730x) Test*

KBD8730x PC8730x Keyboard/Mouse Tests*

ISABRDGE PCI/ISA Bridge Tests (Register Access & IRQ)

VME3 VME3 Tests (Register Read & Register Walking Bit)

DEC DEC21x43 Ethernet Controller Tests

CL1283 Parallel Interface (CL1283) Tests*

Note:

1. You may enter command names in either uppercase or lowercase.

2. Some diagnostics depend on restart defaults that are set up only in a particular restart mode. Refer to the documentation on a particular diagnostic for the correct mode.

3. Test Sets marked with an asterisk (*) are not available on the MVME5100 (unless an IPMC712 or IPMC761 is mounted). The ISABRDGE test is only performed if an IPMC761 is mounted on the MVME5100. If the MVME5100 is operating in PMC mode (IPMC761 is not mounted), then the test suite is bypassed.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 65

Functional Description

4.1 Introduction

This chapter provides a functional description for the MVME5100 Single Board Computer. The MVME5100 is a high-performance product featuring PowerPlus II architecture with a choice of PowerPC processors—either the MPC7410 with AltiVec™ technology for algorithmic intensive computations or the low-power MPC750.

The MVME5100 incorporates a highly optimized PCI interface and memory controller enabling up to 582MB memory read bandwidth and 640MB burst write bandwidth.

The optimization of the memory bus is as important as optimization of the system bus in order to achieve maximum system performance. The MVME5100’s advanced PowerPlus II Architecture supports full PCI throughput of 264MB without starving the CPU of its memory.

Additional features of the MVME5100 include dual Ethernet ports, dual serial ports and up to 17MB of Flash.

Chapter 4

4.2 Features Summary

The table below lists the general features for the MVME5100. Refer to Appendix A,

Specifications, for additional product specifications and information.

Table 4-1 MVME5100 General Features

Feature Specification

Microprocessors and

Bus Clock Frequency

L2 Cache (Optional) 1MB (MPC750) or 2MB (MPC7410) using burst-mode SRAM

Memory EEPROM, on-board programmable

Main Memory

(SDRAM)

MPC7410 @400 or 500 MHz Internal Clock Frequency

MPC750 @450 MHz Internal Clock Frequency

Bus Clock Frequency up to 100 MHz

modules.

1MB via two 32-pin PLCC/CLCC sockets;

16MB Surface Mount

PC100 ECC SDRAM with 100 MHz bus

32MB to 512MB on board, expandable to

1.5GB via RAM500 memory mezzanine

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 66

Functional Description

Table 4-1 MVME5100 General Features

Feature Specification

NVRAM 32KB (4KB available for users)

Memory Controller Hawk System Memory Controller (SMC)

PCI Host Bridge Hawk PCI Host Bridge (PHB)

Interrupt Controller Hawk Multi-Processor Interrupt Controller (MPIC)

Peripheral Support Dual 16550-Compatible Asynchronous Serial Port’s Routed to the

VMEbus Tundra Universe Controller, 64-bit PCI

Front Panel RJ45 Connector (COM1) and On-Board Header (COM2)

Dual Ethernet Interfaces, one routed to the Front Panel RJ45, One Routed to the Front Panel RJ45 or Optionally Routed to P2, RJ45 on MVME761

Programmable Interrupter & Interrupt Handler

Programmable DMA Controller With Link List Support

Full System Controller Functions

PCI/PMC/Expansion Two 32/64-bit PMC Slots With Front-Panel I/O,

P2 Rear I/O (MVME2300 Routing)

One PCI Expansion Connector (for the PMCSpan)

Miscellaneous Combined RESET and ABORT Switch

Status LEDs

Form Factor 6U VME

4.3 Features Descriptions

4.3.1 General

As stated earlier, the MVME5100 is a high-performance VME based Single Board Computer featuring PowerPlus II architecture with a choice of processors. The board can be equipped with either the MPC7410 processor with AltiVec™ technology for algorithmic intensive computations or with the low-power MPC750 for low-power or field applications.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 67

Functional Description

Designed to meet the needs of OEMs servicing the military and aerospace, industrial automation and semiconductor process equipment market segments, the MVME5100 is available in both commercial grade (0° to 55° C) and industrial grade (–20° to 71° C) temperatures.

The MVME5100 has two Input/Output (I/O) modes of operation: PMC and SBC (also called 761 mode or IPMC mode). In PMC mode, it is fully backwards compatible with previous generation dual PMC products such as the MVME2300 and MVME2400.

In the SBC mode, the MVME5100 is backwards compatible with the corresponding Artesyn MVME712 or MVME761 transition board originated for use with previous generation singleboard computer products, such as the MVME2600 and MVME2700.

It is important to note that MVME712 and MVME761 compatibility is accomplished with the addition of the corresponding IPMC712 or IPMC761 (an optional add-on PMC card). The IPMC712 and IPMC761 provides rear I/O support for one single-ended ultra-wide SCSI device, one parallel port, four serial ports (two synchronous for 761 and one for 712, and two asynchronous/synchronous for 761 and three for 712) and I2C functionality through the Hawk ASIC. This multi-function PMC card is offered with the MVME5100 as a factory bundled configuration.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 68

Functional Description

The following diagram illustrates the architecture of the MVME5100 Single Board Computer.

Figure 4-1 MVME5100 Block Diagram

L2 Cache

1M,2M

Processor

MPC7410

MPC750

Clock

Generator

System Memory Controller (SMC)

100 MHz MPC604 Processor Bus

and PCI Host Bridge (PHB)

33MHz 32/64-bit PCI Local Bus

Mezzanine SDRAM

32MB to 512MB

SDRAM

32MB to 512MB

Hawk Asic

Hawk X-bus

System

Registers

TL16C550

UART/9pin

planar

FLASH

1MB to 17MB

RTC/NVRAM/WD

M48T37V

2,64-bit PMC Slots

RJ45

DEBUG

RJ45

10/100TX

RJ45

10/100TX

Slot2

PMC FrontI/O

SLot1

PMC Front I/O

TL16C550

UART

Front Panel

Ethernet 1

10/100TX

VME P2

Ethernet 2

10/100TX

HDR

712/761 or PMC

VME Bridge

Universe 2

Buffers

PCI Expansion

IPMC761 RECEPTACLE

VME P1

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 69

Functional Description

4.3.2 Processor

The MVME5100 incorporates a BGA foot print that supports both the MCP7410 and the MCP75x processors. The maximum external processor bus speed is 100 MHz.

Note: The MCP7410 is configured to operate only with the PowerPC 60xbus interface.

4.3.3 System Memory Controller and PCI Host Bridge

The on-board Hawk ASIC provides the bridge function between the processor’s bus and the PCI bus. It provides 32-bit addressing and 64-bit data; however, 64-bit addressing (dual address cycle) is not supported. The ASIC also supports various processor external bus frequencies up to100 MHz.

There are four programmable map decoders for each direction to provide flexible address mappings between the processor and the PCI bus. The ASIC also provides an Multi-Processor Interrupt Controller (MPIC) to handle various interrupt sources. They are: four MPIC timer interrupts, interrupts from all PCI devices and two software interrupts.

4.3.4 Memory

The following subsections describe various memory capabilities on the MVME5100 including Flash memory and ECC SDRAM memory.

4.3.4.1 Flash Memory

The MVME5100 contains two banks of Flash memory. Bank B consists of two 32-pin devices which can be populated with 1MB of Flash memory (only 8-bit writes are supported for this bank). Refer to the application note following for more write-protect information on this product.

Bank A has 4 16-bit Smart Voltage FLASH SMT devices. With 32Mbit flash devices, the flash memory size is 16MB. Note that only 32-bit writes are supported for this bank of flash memory. Application Note: For Am29DL322C or Am29DL323C, 32Megabit (4M x 8-Bit/2M x 16-bit) CMOS 3.0 Volt-only Flash Memory.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 70

Functional Description

The Write Protect function provides a hardware method of protecting certain boot sectors. If the system asserts V IL (low signal) on the WP#/ACC pin, the device disables the program and erase capability, independently of whether those sectors were protected or unprotected using the method described in the Sector/Sector Block Protection and Unprotection of the AMD datasheet. The two outermost 8Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device.

The aforementioned implemented device (at the time of this printing is the only qualified Flash device used on this product) is a top-boot device, and as such, the write protected area is in the upper 16KB of each device. Since it uses 4 devices for the soldered Flash bank, the write protected region corresponds to the upper 64KB of the soldered Flash memory map. Thus the address range of $F4FF 0000 to F4FF FFFF is the write protected region when the J16 header is jumpered across pins 2 and 3.

If PPCBug tries to write to those write-protected address areas when pins 2-3 on J16 are set, the command will simply not finish (i.e., erase sector function stops at $F4FF 0000).

4.3.4.2 ECC SDRAM Memory

The MVME5100’s on-board memory and optional memory mezzanines allow for a variety of memory size options. Memory size can be 64 or 512MB for a total of 1.5GB on-board and mezzanine ECC memory. The memory is controlled by the hardware which provides single-bit error correction and double-bit error detection (ECC is calculated over 72-bits).

Either 1 or 2 mezzanines can be installed. Each mezzanine will add 1 bank of SDRAM memory of 256 or 512MB. A total of 1GB of mezzanine memory can be added. Refer to Chapter 5,

RAM500 Memory Expansion Module, for more information.

4.3.5 P2 Input/Output (I/O) Modes

The MVME5100 has two P2 I/O modes (SBC and PMC) that are user- configurable with jumpers on the board (J6 and J20). The jumpers route the on-board Ethernet port 2 to row C of the P2 connector. Ethernet jumpers (J4, J10, and J17) should also be configured.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 71

The SBC mode (also called 761 or IPMC mode) are backwards compatible with the corresponding MVME712 and MVME761 transition cards and the P2 adapter card (excluding PMC I/O routing) used on the MVME2600/2700. The SBC mode is accomplished by configuring the on-board jumpers and attaching an IPMC712 or IPMC761 PMC in PMC slot 1 of the MVME5100.

PMC mode is backwards compatible with the MVME2300/MVME2400. PMC mode is accomplished by simply configuring the on-board jumpers.

Note: Refer to Chapter 6, Pin Assignments for P2 Input/Output Mode jumper settings.

4.3.6 Input/Output Interfaces

The following subsections describe the major I/O interfaces on the MVME5100 including Ethernet, VMEbus, asynchronous communications ports, real-time clock/NVRAM/Watchdog Timer, other timer interfaces, interrupt routing capabilities and IDSEL routing capabilities.

Functional Description

4.3.6.1 Ethernet Interface

The MVME5100 incorporates dual Ethernet interfaces (Port 1 and Port 2) via two Fast Ethernet PCI controller chips.

The Port 1 10BaseT/100BaseTX interface is routed to the front panel. The Port 2 Ethernet interface is routed to either the front panel or the P2 connector as configured by jumpers. The front panel connectors are of the RJ45 type.

Every board is assigned two Ethernet Station Addresses. The address is $0001AFXXXXX where XXXXX is the unique number assigned to each interface. Each Ethernet Station Address is displayed on a label attached to the PMC front-panel keep-out area.

In addition, LAN 1 Ethernet address is stored in the configuration area of the NVRAM specified by the Boot ROM and in SROM.

4.3.6.2 VMEbus Interface

The VMEbus interface is provided by the Universe II ASIC. Refer to the Universe II User’s Manual, as listed in Appendix D, Related Documentation, for additional information.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 72

Functional Description

4.3.6.3 Asynchronous Communications

The MVME5100 provides dual asynchronous debug ports. The serial signals COM1 and COM2 are routed through appropriate EIA-232 drivers and receivers to an RJ45 connector on the front panel (COM1) and an on-board connector (COM2). The external signals are ESD protected.

4.3.6.4 Real-Time Clock & NVRAM & Watchdog Timer

The MVME5100’s design incorporates 32KB of non-volatile static RAM, along with a real-time clock and a watchdog function an integrated device. Refer to the M48T37V CMOS 32Kx8 Timekeeper SRAM Data Sheet, as referenced in Appendix D, Related Documentation for additional programming and engineering information.

4.3.6.5 Timers

Timers and counters on the MVME5100 are provided by the board’s hardware (Hawk ASIC). There are four 32-bit timers on the board that may be used for system timing or to generate periodic interrupts.

4.3.6.6 Interrupt Routing

Legacy interrupt assignment for the PCI/ISA Bridge is maintained to ensure software compatibility between the MVME5100 and the MVME2700 while in SBC mode.

This is accomplished by using the corresponding on-board IPMC712 or IPMC761 connector to route the PCI/ISA Bridge interrupt signal to the external interrupt 0 of the Hawk ASIC (MPIC).

Note: The SCSI device on either the IPMC712 or IPMC761 uses the standard INTA# pin J11-04 of PMC Slot 1.

4.3.6.7 IDSEL Routing

Legacy IDSEL assignment for the PCI/ISA Bridge is also maintained to ensure software compatibility between MVME5100 and the MVME2700 while in SBC mode (also called 761 or IPMC mode).

This is accomplished by using either the on-board IPMC712 or IPMC761 connector to route IDSEL (AD11) to the PCI/ISA Bridge on the IPMC712 or IPMC761.

Note: The SCSI device on the IPMC712 and IPMC761 uses the standard IDSEL pin J12-25 connected to AD16.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 73

Functional Description

When a standard PMC card (not the IPMC712 or IPMC761) is plugged into slot 1, its IDSEL assignment corresponds to the standard IDSEL pin J12-25 and shall be connected to AD16.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 74

Functional Description

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 75

RAM500 Memory Expansion Module

5.1 Overview

The RAM500 memory expansion module can be used on the MVME5100 as an option for additional memory capability. Each expansion module is a single bank of SDRAM with either 256 or 512MB of available ECC memory. Currently, two expansion modules can be used in tandum to produce an additional expanded memory capability of 1GB. There are two configurations of the board to accommodate tandum usage. The bottom expansion module has both a bottom and top connector: one to plug into the base board, and one to mate with the second RAM500 module. The top expansion module is designed with just a bottom connector to plug into the lower RAM500 module. The RAM500 incorporates a Serial ROM for system memory Serial Presence Detect (SPD) data.

A maximum of two expansion modules are allowed: one bottom and one top. If only one module is used, the RAM500 module with the top configuration is recommended.

Chapter 5

5.2 Features

The following table lists the features of the RAM500 memory expansion module:

Table 5-1 RAM500 Feature Summary

Feature Specification

Form Factor Dual sided mezzanine, with screw/post attachment to host board

SROM Single 256x8 I2C SROM for Serial Presence Detect Data

SDRAM Double-Bit-Error detect, Single-Bit-Error correct across 72 bits

Memory Expansion

Flexibility

VMEbus Tundra Universe Controller, 64-bit PCI

128, 256, or 512MB mezzanine memory @ 100MHz

Any RAM500 memory size can be attached to the host board followed by any secondary RAM500 memory size for maximum memory expansion flexibility.

Programmable Interrupter & Interrupt Handler

Programmable DMA Controller With Link List Support

Full System Controller Functions

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 76

RAM500 Memory Expansion Module

5.3 Functional Description

The following sections describe the physical and electrical structure of the RAM500 memory expansion module.

5.3.1 RAM500 Description

The RAM500 is a memory expansion module that is used on the MVME5100 Single Board Computer. The RAM500 is based on a single memory mezzanine board design with the flexibility of being populated with different sized SDRAM components and SPD options to provide a variety of memory configurations. The design of the RAM500 allows any memory size module to connect to and operate with any other available memory size module.

The optional RAM500 memory expansion module is currently available in three sizes: 128MB, 256MB, and 512MB, with a total added capacity of 1GB. The SDRAM memory is controlled by the Hawk ASIC, which provides single-bit error correction and double-bit error detection. ECC is calculated over 72-bits. Refer to the MVME5100 Single Board Computer Programmer’s Reference Guide (V5100A/PG) for more information.

The RAM500 consists of a single bank/block of memory. The memory block size is dependent upon the SDRAM devices installed. Refer to Table 5-2 for memory options.

The RAM500 memory expansion module is connected to the host board with a 140-pin AMP

0.6mm Free Height plug connector. If the expansion module is designed to accommodate

another RAM500 module, the bottom expansion module will have two 140-pin AMP connectors installed: one on the bottom side of the module, and one on the top side of the module. The RAM500 memory expansion module draws +3.3V through this connector.

When populated, the optional RAM500 memory expansion memory blocks should appear as Block C and Block E to the Hawk ASIC. Block C and E are used because each of the module’s SPD is defined to correspond to two banks of memory each: C and D for the first SPD and E and F for the second SPD.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 77

RAM500 Memory Expansion Module

The RAM500 SPD uses the SPD JEDEC standard definition and is accessed at address $AA or $AC. Refer to the following section on SROM for more details.

Table 5-2 RAM500 SDRAM Memory Size Options

RAM500 Memory Size Device Size Device Organization Number of Devices

32 Mbytes 64 Mbit 4Mx16 5*

64 Mbytes 128 Mbit 8Mx16 5*

128 Mbytes 256 Mbit 16Mx16 5*

64 Mbytes 64 Mbit 8Mx8 9

128 Mbytes 128 Mbit 16Mx8 9

256 Mbytes 256 Mbit 32Mx8 9

Figure 5-1 RAM500 Block Diagram

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 78

RAM500 Memory Expansion Module

5.3.2 SROM

The RAM500 memory expansion module contains a single 3.3V, 256 x 8, Serial EEPROM device (AT24C02). The Serial EEPROM provides Serial Presence Detect (SPD) storage of the module memory subsystem configuration. The RAM500 SPD is software addressable by a unique address as follows: The first RAM500 attached to the host board has its SPD addressable at $AA. The second RAM500 attached to the host board has its SPD addressable at $AC. This dynamic address relocation of the RAM500 SPD shall be done using the bottom-side connector signal A1_SPD and A0_SPD.

5.4 RAM500 Module Installation

One or more RAM500 memory expansion modules can be mounted on top of the MVME5100 for additional memory capacity. To upgrade or install a RAM500 module, refer to below figure and proceed as follows:

1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2. Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove the chassis or system cover(s) as necessary for access to the CompactPCI boards.

3. Carefully remove the MVME5100 from its VME card slot and lay it flat, with connectors P1 and P2 facing you.

4. Inspect the RAM500 module that is being installed on the MVME5100 host board (bottom configuration if two are being installed, top configuration if only one is being installed) to ensure that standoffs are installed in the three mounting holes on the module.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 79

RAM500 Memory Expansion Module

5. With standoffs installed in the three mounting holes on the RAM500 module, align the standoffs and the P1 connector on the module with the three holes and the J16 connector on the MVME5100 host board and press the two connectors together until they are firmly seated in place.

6. (Optional step) If a second RAM500 module is being used, align the top connector on the bottom RAM500 module with the bottom connector on the top RAM500 module and press the two connectors together until the connectors are seated in place.

7. Insert the three short Phillips screws through the holes at the corners of the RAM500 and screw them into the standoffs.

8. Turn the entire assembly over, and fasten the three nuts provided to the standoff posts on the bottom of the MVME5100 host board.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 80

RAM500 Memory Expansion Module

9. Reinstall the MVME5100 assembly in its proper card slot. Be sure the host board is well seated in the backplane connectors. Do not damage or bend connector pins.

10. Replace the chassis or system cover(s), reconnect the system to the AC or DC power source, and turn the equipment power on.

5.5 RAM500 Connectors

RAM500 memory expansion modules are populated with one or two connectors. If the module is to be used in tandum with a second RAM500 module, the “bottom” module will have two connectors: one to mate with the MVME5100 host board (P1), and one to mate with the “top” RAM500 module (J1). The “top” RAM500 module has only one connector, since it needs to mate only with the RAM500 module directly underneath it and because an added connector on a tandum RAM500 configuration would exceed the height limitations in some backplanes. If only one RAM500 module is being used, a top module, single connector configuration is used.

A 4H plug and receptacle are used on both boards to provide a 4 millimeter stacking height between dual RAM500 cards and the host board.

The following subsections specify the pin assignments for the connectors on the RAM500.

5.5.1 Bottom Side Memory Expansion Connector (P1)

The bottom side connector on the RAM500 is a 140-pin AMP 0.6mm Free Height mating plug. This plug includes common ground contacts that mate with standard AMP receptacle assemblies or AMP GIGA assemblies with ground plates. A single memory expansion module will have 1 bank of SDRAM for a maximum of 5Mbytes of memory. Attaching a second memory module to the first module will provide 2 banks of SDRAM with a maximum of 1Gigabytes

Table 5-3 RAM500 Bottom Side Connector (P1)Pin Assignments

1 GND* GND* 2

3 DQ00 DQ01 4

5 DQ02 DQ03 6

7 DQ04 DQ05 8

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 81

RAM500 Memory Expansion Module

Table 5-3 RAM500 Bottom Side Connector (P1)Pin Assignments

9 DQ06 DQ07 10

11 +3.3V +3.3V 12

13 DQ08 DQ09 14

15 DQ10 DQ11 16

17 DQ12 DQ13 18

19 DQ14 DQ15 20

21 GND* GND* 22

23 DQ16 DQ17 24

25 DQ18 DQ19 26

27 DQ20 DQ21 28

29 DQ22 DQ23 30

31 +3.3V +3.3V 32

33 DQ24 DQ25 34

35 DQ26 DQ27 36

37 DQ28 DQ29 38

39 DQ30 DQ31 40

41 GND* GND* 42

43 DQ32 DQ33 44

45 DQ34 DQ35 46

47 DQ36 DQ37 48

49 DQ38 DQ39 50

51 +3.3V +3.3V 52

53 DQ40 DQ41 54

55 DQ42 DQ43 56

57 DQ44 DQ45 58

59 DQ46 DQ47 60

61 GND* GND* 62

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 82

RAM500 Memory Expansion Module

Table 5-3 RAM500 Bottom Side Connector (P1)Pin Assignments

63 DQ48 DQ49 64

65 DQ50 DQ51 66

67 DQ52 DQ53 68

69 +3.3V +3.3V 70

71 DQ54 DQ55 72

73 DQ56 DQ57 74

75 DQ58 DQ59 76

77 DQ60 DQ61 78

79 GND* GND* 80

81 DQ62 DQ63 82

83 CKD00 CKD01 84

85 CKD02 CKD03 86

87 CKD04 CKD05 88

89 +3.3V +3.3V 90

91 CKD06 CKD07 92

93 BA1 BA0 94

95 A12 A11 96

97 A10 A09 98

99 GND* GND* 100

101 A08 A07 102

103 A06 A05 104

105 A04 A03 106

107 A02 A01 108

109 +3.3V +3.3V 110

111 A00 CS_E0_L 112

113 GND* GND* 114

115 CS_E1_L 116

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 83

RAM500 Memory Expansion Module

Table 5-3 RAM500 Bottom Side Connector (P1)Pin Assignments

117 WE_L RAS_L 118

119 GND* GND* 120

121 CAS_L +3.3V 122

123 +3.3V DQMB1 124

125 SCL 126

127 SDA 128

129 A1_SPD MEZZ2_L 130

131 GND 132

133 GND SDRAMCLK3134

135 +3.3V 136

137 SDRAMCLK4138

139 GND* GND* 140

*Common GND pins mate to GIGA assemblies with ground plates.

5.6 RAM500 Programming Issues

The RAM500 contains no user programmable registers, other than the Serial Presence Detect (SPD) Data.

5.6.1 Serial Presence Detect (SPD) Data

This register is partially described for the RAM500 within the MVME5100 Single Board Computer Programmer’s Reference Guide. The register is accessed through the I2C interface of the Hawk ASIC on the host board (MVME5100). The RAM500 SPD is software addressable by a unique address as follows: The first RAM500 attached to the host board has has an SPD address of $AA. The second RAM500 attached to the top of the first RAM500 has an SPD address of $AC.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 84

RAM500 Memory Expansion Module

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 85

Pin Assignments

6.1 Introduction

This chapter provides information on pin assignments for various jumpers and connectors on the MVME5100 Single Board Computer.

6.1.1 Summary

The following tables summarize all of the jumpers and connectors:

Jumper Description Connector Description

Chapter 6

J1 RISCWatch

Header

J2 PAL Programming

Header

J4 Ethernet Port 2

Configuration

J6, J20

Operation Mode Jumpers

J7 Flash Memory

Selection

J10, J17 Ethernet Port

Selection

J15 System Controller

(VME)

J16 Soldered Flash

Protection

J3 IPMC761 Interface

J8 Memory Expansion

J25 PCI Expansion

Interface

J11 - J14 PMC Interface (Slot 1)

J21 - J24 PMC Interface (Slot 2)

P1, P2 VMEbus Interface

J18

J19 COM1 Interface

J5 COM2 Interface

Ethernet Interface (LAN1)

Ethernet Interface (LAN2)

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 86

Pin Assignments

6.2 Jumper Settings

The following table provides information about the jumper settings associated with th MVME5100 Single Board Computer. The table below provides a brief description of each jumper and the appropriate setting(s) for proper board operation.

Jumper Description Setting Default

J1 RISCWatch Header None (Factory Use Only) N/A

J2 PAL Programming Header None (Lab Use Only) N/A

J4 Ethernet Port 2 Selection

(set in conjunction with jumpers J10 and J17)

J6, J20 Operation Mode

(Set Both Jumpers)

J7 Flash Memory Selection

at Boot

J10, J17 Ethernet Port 2 Selection

(set in conjunction with jumper J4

For “P2” Ethernet Port 2:

Pins 1,2; 3,4; 5,6; 7,8 (set for 712/761)

Ethernet Port 2:

No Jumpers Installed

Pins 1,2 for PMC Mode PMC

Pins 2,3 for SBC Mode (761 Mode)

Pins 1,2 for Soldered Bank ASocketed

Pins 2,3 for Socketed Bank B

For “Front Panel” Ethernet Port 2:

Pins 1,3 and 2,4 on Both Jumpers

For “P2” Ethernet Port 2:

Pins 3,5 and 4,6 on Both Jumpers (set for 712/761)

Jumper

Installed

(front panel)For “Front Panel”

Mode

Bank B

Front

Panel

Ethernet

Port 2

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 87

Jumper Description Setting Default

J15 System Controller (VME) Pins 1,2 for No SCON

Pins 2,3 for Auto SCON

No Jumper for ALWAYS SCON

Auto

SCON

Pin Assignments

J16 Soldered Flash Protection Pins 1,2 Enables

Programming of Flash

Programming of the upper 64KB of Flash

Flash

Prog.

EnabledPins 2,3 Disables

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 88

Pin Assignments

6.3 Connectors

6.3.1 IPMC761 Connector (J3) Pin Assignments

This connector is used to provide an interface to the IPMC761 module signals and is located near J11. The pin assignments for this connector are as follows:

Table 6-1 IPMC761 Connector Pin Assignments

Pin Assignment Pin

1 I2CSCL I2CSDA 2

3GND GND 4

5 DB8# GND 6

7 GND DB9# 8

9 DB10# +3.3V 10

11 +3.3V DB11# 12

13 DB12# GND 14

14 GND DB13# 16

17 DB14# +3.3V 18

19 +3.3V DB15# 20

21 DBP1# GND 22

23 GND LANINT2_L 24

25 PIB_INT +3.3V 26

27 +3.3V PIB_PMCREQ# 28

29 PIB_PMCGNT# GND 30

31 GND +3.3V 32

33 +5.0V +5.0V 34

35 GND GND 36

37 +5.0V +5.0V 38

39 GND GND 40

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 89

Pin Assignments

6.3.2 Memory Expansion Connector (J8) Pin Assignments

This connector is used to provide memory expansion capability. A single memory mezzanine card provides a maximum of 256MB of memory. Attaching another memory mezzanine to the first mezzanine provides an additional 512MB of expansion memory. The pin assignments for this connector are as follows:

Table 6-2 RAM500 Bottom Side Connector (P1)Pin Assignments

Pin Assignment Assignment Pin

1 GND* GND 2

3 DQ00 DQ01 4

5 DQ02 DQ03 6

7 DQ04 DQ05 8

9 DQ06 DQ07 10

11 +3.3V +3.3V 12

13 DQ08 DQ09 14

15 DQ10 DQ11 16

17 DQ12 DQ13 18

19 DQ14 DQ15 20

21 GND GND 22

23 DQ16 DQ17 24

25 DQ18 DQ19 26

27 DQ20 DQ21 28

29 DQ22 DQ23 30

31 +3.3V +3.3V 32

33 DQ24 DQ25 34

35 DQ26 DQ27 36

37 DQ28 DQ29 38

39 DQ30 DQ31 40

41 GND GND 42

43 DQ32 DQ33 44

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 90

Pin Assignments

Table 6-2 RAM500 Bottom Side Connector (P1)Pin Assignments (continued)

Pin Assignment Assignment Pin

45 DQ34 DQ35 46

47 DQ36 DQ37 48

49 DQ38 DQ39 50

51 +3.3V +3.3V 52

53 DQ40 DQ41 54

55 DQ42 DQ43 56

57 DQ44 DQ45 58

59 DQ46 DQ47 60

61 GND* GND* 62

63 DQ48 DQ49 64

65 DQ50 DQ51 66

67 DQ52 DQ53 68

69 +3.3V +3.3V 70

71 DQ54 DQ55 72

73 DQ56 DQ57 74

75 DQ58 DQ59 76

77 DQ60 DQ61 78

79 GND GND 80

81 DQ62 DQ63 82

83 CKD00 CKD01 84

85 CKD02 CKD03 86

87 CKD04 CKD05 88

89 +3.3V +3.3V 90

91 CKD06 CKD07 92

93 BA1 BA0 94

95 A12 A11 96

97 A10 A09 98

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 91

Table 6-2 RAM500 Bottom Side Connector (P1)Pin Assignments (continued)

Pin Assignment Assignment Pin

99 GND GND 100

101 A08 A07 102

103 A06 A05 104

105 A04 A03 106

107 A02 A01 108

109 +3.3V +3.3V 110

111 A00 CS_E0_L 112

113 CS_E0_L GND 114

115 CS_E1_L CS_E0_L 116

117 WE_L RAS_L 118

119 GND GND 120

Pin Assignments

121 CAS_L +3.3V 122

123 +3.3V DQMB0 124

125 DQMB1 SCL 126

127 SDA A1_SPD 128

129 A0_SPD MEZZ2_L 130

131 MEZZ2_L GND 132

133 GND SDRAMCLK1 134

135 SDRAMCLK3 +3.3V 136

137 SDRAMCLK4 SDRAMCLK2 138

139 GND* GND* 140

Note: PIN 130, 131, MEZZ1_L, MEZZ2_L, configures the board’s local bus frequency. If a single mezzanine is attached to the board, MEZZ1_L will be pulled down on the board. If a second mezzanine is attached on-top to the first, MEZZ2_L will be pulled down on the board. This may cause the clock generation logic to set the local bus frequency to 83.33 MHz if necessary.

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 92

Pin Assignments

6.3.3 PCI Expansion Connector (J25) Pin Assignments

This connector is used to provide PCI/PMC expansion capability. The pin assignments for this connector are as follows:

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 93

Table 6-3 RAM500 Bottom Side Connector (P1)Pin Assignments

Pin Assignments Pin

Pin Assignments

1 +3.3V

3 PCICLK PMCINTA#4

5 GND PMCINTB#6

7 PURST# PMCINTC#8

9 HRESET# PMCINTD#10

11 TDO TDI 12

13 TMS TCK 14

15 TRST# PCIXP# 16

17 PCIXGNT

19 +12V -12V 20

21 PERR# SERR# 22

23 LOCK# SDONE 24

25 DEVSEL# SBO# 26

27 GND GND 28

GND

+3.3V 2

PCIXREQ#18

29 TRDY# IRDY# 30

31 STOP# FRAME# 32

33 GND GND 34

35 ACK64# Reserved 36

37 REQ64# Reserved 38

39 PAR PCIRST# 40

41 C/BE1# C/BE0# 42

43 C/BE3# C/BE2# 44

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 94

Pin Assignments

Table 6-3 RAM500 Bottom Side Connector (P1)Pin Assignments (continued)

Pin Assignments Pin

45 AD1

47 AD3 AD4 48

49 AD5 AD6 50

51 AD7 AD8 52

AD0 46

53 AD9 AD10 54

55 AD11 AD12 56

57 AD13 AD14 58

59 AD15 AD16 60

61 AD17 AD18 62

63 AD19 AD20 64

65 AD21 AD22 66

67 AD23 AD24 68

69 AD25 AD26 70

71 AD27 AD28 72

73 AD29 AD30 74

75 PAR64 Reserved 76

77 C/BE5# C/BE4# 78

79 C/BE7# C/BE6# 80

81 AD33 AD32 82

83 AD35 AD34 84

85 AD37 AD36 86

87 AD35 AD34 88

+5V

89 AD37 AD36 90

91 AD39 AD38 92

93 AD41 AD40 94

95 AD43 AD42 96

97 AD45 AD44 98

GND

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 95

Table 6-3 RAM500 Bottom Side Connector (P1)Pin Assignments (continued)

Pin Assignments Pin

99 AD47 AD46 100

101 AD49 AD48 102

103 AD51 AD50 104

105 AD53 AD52 106

107 AD55 AD56 108

109 AD57 AD58 110

111 AD61 AD60 112

113 AD63 AD62 114

6.3.4 PCI Mezzanine Card (PMC) Connectors

Pin Assignments

These connectors provide 32/64-bit PCI interfaces and P2 I/O for two optional add-on PCI Mezzanine Cards (PMC). The pin assignments for these connectors are as follows.

Table 6-4 PMC Slot 1 Connector (J11) Pin Assignments

Pin Assignment Pin

1 TCK -12V 2

3GND INTA#4

5 INTB# INTC# 6

7 PMCPRSNT1# +5V 8

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 96

Pin Assignments

Table 6-4 PMC Slot 1 Connector (J11) Pin Assignments (continued)

Pin Assignment Pin

9 INTD# Not

Used

11 GND Not

Used

13 CLK GND 14

15 GND PMCGN

T1#

17 PMCREQ1# +5V 18

19 +5V (Vio) AD31 20

21 AD28 AD27 22

23 AD25 GND 24

25 GND C/BE3# 26

27 AD22 AD21 28

29 AD19 +5V 30

31 +5V (Vio) AD17 32

33 FRAME# GND 34

35 GND IRDY# 36

37 DEVSEL# +5V 38

39 GND LOCK# 40

41 SDONE# SBO# 42

43 PAR GND 44

45 +5V (Vio) AD15 46

47 AD12 AD11 48

49 AD09 +5V 50

51 GND C/BE0# 52

53 AD06 AD05 54

55 AD04 GND 56

57 +5V (Vio) AD03 58

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 97

Table 6-4 PMC Slot 1 Connector (J11) Pin Assignments (continued)

Pin Assignment Pin

59 AD02 AD01 60

61 AD00 +5V 62

63 GND REQ64#64

Table 6-5 PMC Slot 1 Connector (J12) Pin Assignments

Pin Assignment Pin

1 +12V TRST# 2

3 TMS TDO 4

Pin Assignments

5 TDI GND 6

7 GND Not Used 8

9 Not Used Not Used 10

11 Pull-up to

+3.3V

13 RST# Pull-down

15 +3.3V Pull-down

17 Not Used GND 18

19 AD30 AD29 20

21 GND AD26 22

23 AD24 +3.3V 24

25 IDSEL1 AD23 26

27 +3.3V AD20 28

29 AD18 GND 30

31 AD16 C/BE2# 32

33 GND Not Used 34

+3.3V 12

to GND

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 98

Pin Assignments

Table 6-5 PMC Slot 1 Connector (J12) Pin Assignments (continued)

Pin Assignment Pin

35 TDRY# +3.3V 36

37 GND STOP# 38

39 PERR# GND 40

41 +3.3V SERR# 42

43 C/BE1# GND 44

45 AD14 AD13 46

47 GND AD10 48

49 AD08 +3.3V 50

51 AD07 Not Used 52

53 +3.3V Not Used 54

55 Not Used GND 56

100

57 Not Used Not Used 58

59 GND Not Used 60

61 ACK64# +3.3V 62

63 GND Not Used 64

Pin Assignment Pin

1 Reserved GND 2

3 GND C/BE7# 4

5 C/BE6# C/BE5# 6

7 C/BE4# GND 8

9 +5V (Vio) PAR64 10

11 AD63 AD62 12

13 AD61 GND 14

15 GND AD60 16

17 AD59 AD58 18

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Page 99

Pin Assignment Pin

19 AD57 GND 20

21 +5V (Vio) AD56 22

23 AD55 AD54 24

25 AD53 GND 26

27 GND AD52 28

29 AD51 AD50 30

31 AD49 GND 32

33 GND AD48 34

35 AD47 AD46 36

37 AD45 GND 38

39 +5V (Vio) AD44 40

41 AD43 AD42 42

Pin Assignments

43 AD41 GND 44

45 GND AD40 46

47 AD39 AD38 48

49 AD37 GND 50

51 GND AD36 52

53 AD35 AD34 54

55 AD33 GND 56

57 +5V (Vio) AD32 58

59 Reserved Reserved 60

61 Reserved GND 62

63 GND Reserved 64

Table 6-6 PMC Slot 1 Connector (J14) Pin Assignments

Pin Assignment Pin

1 Jumper Configurable PMC1_2 (P2-A1) 2

3 Jumper Configurable PMC1_4 (P2-A2) 4

MVME51005E Single Board Computer Installation and Use (6806800A38D)

101

Page 100

Pin Assignments

Table 6-6 PMC Slot 1 Connector (J14) Pin Assignments (continued)

Pin Assignment Pin

5 Jumper Configurable PMC1_6 (P2-A3) 6

7 Jumper Configurable PMC1_8 (P2-A4) 8

9 PMC1 _9 (P2-C5) PMC1_10 (P2-

A5)

11 PMC1_11 (P2-C6) PMC1_12 (P2-

A6)

13 PMC1_13 (P2-C7) PMC1_14 (P2-

A7)

15 PMC1_15 (P2-C8) PMC1_16 (P2-

A8)

17 PMC1_17 (P2-C9) PMC1_18 (P2-

A9)

19 PMC1_19 (P2-C10) PMC1_20 (P2-

A10)

21 PMC1_21 (P2-C11) PMC1_22 (P2-

A11)

23 PMC1_23 (P2-C12) PMC1_24 (P2-

A12)

25 PMC1_25 (P2-C13) PMC1_26 (P2-

A13)

27 PMC1_27 (P2-C14) PMC1_28 (P2-

A14)

29 PMC1_29 (P2-C15) PMC1_30 (P2-

A15)

102

31 PMC1_31 (P2-C16) PMC1_32 (P2-

A16)

33 PMC1_33 (P2-C17) PMC1_34 (P2-

A17)

35 PMC1_35 (P2-C18) PMC1_36 (P2-

A18)

37 PMC1_37 (P2-C19) PMC1_38 (P2-

A19)

MVME51005E Single Board Computer Installation and Use (6806800A38D)

Artesyn MVME51005E Installation

Specifications and Main Features

Frequently Asked Questions

User Manual

MVME51005E Single Board Computer

Contents

About this Manual

Overview of Contents

Abbreviations

Conventions

Summary of Changes

Hardware Preparation and Installation

1.1 Introduction

1.1.1 Getting Started

1.1.2 Overview and Equipment Requirements

1.1.3 Unpacking Instructions

1.2 Preparation

1.2.1 Hardware Configuration

1.2.2 Jumper Settings

1.2.2.1 PMC/SBC (761/IPMC) Mode Selection

1.2.3 Installation Considerations

1.3 Installation

1.3.1 PMC Modules

1.3.2 Primary PMCspan

1.3.3 Secondary PMCspan

1.3.4 MVME5100

Operation

2.1 Introduction

2.2 Switches and Indicators

2.2.1 ABT/RST Switch

2.2.1.1 Abort Function

2.2.1.2 Reset Function

2.2.2 Status Indicators

2.2.2.1 RST Indicator (DS1)

2.2.2.2 CPU Indicator (DS2)

2.2.3 Connectors

2.2.3.1 10/100BASE T Ports

2.2.3.2 DEBUG Port

2.3 System Powerup

2.3.1 Initialization Process

PPCBug Firmware

3.1 Introduction

3.2 PPCBug Overview

3.2.1 Implementation and Memory Requirements

3.3 Using PPCBug

3.3.1 Hardware and Firmware Initialization

3.4 Default Settings

3.4.1 CNFG - Configure Board Information Block

3.4.2 ENV - Set Environment

3.4.2.1 Configuring the PPCBug Parameters

3.4.3 LED/Serial Startup Diagnostic Codes

3.4.4 Configuring the VMEbus Interface

3.4.5 Firmware Command Buffer

3.5 Standard Commands

3.5.1 Diagnostics

Functional Description

4.1 Introduction

4.2 Features Summary

4.3 Features Descriptions

4.3.1 General

4.3.2 Processor

4.3.3 System Memory Controller and PCI Host Bridge

4.3.4 Memory

4.3.4.1 Flash Memory

4.3.4.2 ECC SDRAM Memory

4.3.5 P2 Input/Output (I/O) Modes

4.3.6 Input/Output Interfaces

4.3.6.1 Ethernet Interface

4.3.6.2 VMEbus Interface

4.3.6.3 Asynchronous Communications

4.3.6.4 Real-Time Clock & NVRAM & Watchdog Timer

4.3.6.5 Timers

4.3.6.6 Interrupt Routing

4.3.6.7 IDSEL Routing

RAM500 Memory Expansion Module

5.1 Overview

5.2 Features

5.3 Functional Description

5.3.1 RAM500 Description

5.3.2 SROM