TABLE_5_ITEM
DESCRIPTION OF CHANGE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
Apple Computer Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
TITLE
DRAWING NUMBER
SHT
OF
METRIC
DRAFTER
ENG APPD
QA APPD
RELEASE
DESIGN CK
MFG APPD
DESIGNER
SCALE
NONE
MATERIAL/FINISH
NOTED AS
APPLICABLE
SIZE
D
THIRD ANGLE PROJECTION
DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
X.XXX
DO NOT SCALE DRAWING
REV
ZONE
ECN
CK
APPD
DATE
ENG
APPD
DATE
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
ANGLES
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_5_ITEM
09/04/2003
INTREPID GPIOS/SERIAL/USB INTERFACES/SSCG
BATTERY CHARGER AND CONNECTOR
MARVELL GIGABIT ETHERNET PHY
SERIAL DEBUG (JOLLY ROGER, PWR/NMI/RESET)
SCHEM,MLB,PB17"
17
STUFF
EXT_TMDS
ATI_MEMIO_LO
ATI_MEMIO_HI
INTREPID_USB
NEC_USB
1_5V_MAXBUS
D3_HOT
D3_COLD
FIREWIRE A/B CONNECTORS, PORT POWER LIMITER
25
24
5V_HD_LOGIC
3V_HD_LOGIC
NO_4XVCORE
INT_TMDS
NO_SSCG
SPIDEY - KBD,TPAD,HALL EFFECT,PWR BUTTON
DUAL-CHANNEL LVDS
CONTENTS
PAGE
INTREPID AGP 4X/PCI
INTREPID MEMORY INTERFACE / BOOT ROM
10
MPC7450 DATA
TITLE PAGE AND CONTENTS
CPU PLL AND CONFIGURATION STRAPS
200PIN DDR MEMORY SODIMM CONNECTORS
INTREPID ENET/FW/UATA/EIDE INTERFACES
2
BBANG
NO_BBANG
32
30
1
4
5
13
11
12
14
9
18
SSCG
35
33
8
DDR MEMORY MUXES
INTREPID MAXBUS AND BOOT STRAPS
31
28
GPU_SS
NO STUFF
GPU_SWITCH
SERIAL_DEBUG
VCORE_OFFSET
1_8V_MAXBUS
BOM OPTIONS
3
SYSTEM BLOCK DIAGRAM
20
SIL1162 TMDS TRANSMITTER
39
PAGE
26
27
29
22
23
COMPONENT LOCATIONS
SIGNAL NAMES
FUNCTIONAL TEST POINTS
SIGNAL CONSTRAINTS (2 OF 3) - DIGITAL/DIFF
1.5V/ 1.8V / 2.5V SYSTEM POWER SUPPLIES
CPU CORE VOLTAGE POWER SUPPLY
3.3V / 5V SYSTEM POWER SUPPLIES
12.8V SYSTEM POWER SUPPLY / PMU POWER SUPPLY
PMU (POWER MANAGEMENT UNIT)
INTERNAL CONNECTORS - DVD,
LMU, LIGHT SENSOR, BOOTBANGER, SLEEP LED
36
37
38
40
M10 ANALOG, POWER, GND
SIGNAL CONSTRAINTS (3 OF 3) - POWER NETS
43-44
41-42
FAN CONTROLLER, MODEM, SOUND
VIDEO CONNECTORS - INVERTER, DVI, S-VIDEO
CARDSLOT, HARD DRIVE, LEFT USB/BLUETOOTH
USB 2.0
SIGNAL CONSTRAINTS (1 OF 3) - DIGITAL/CLK
REVISION HISTORY (1 OF 1)
M10 LVDS/TMDS/VGA/GPIO & GPU VCORE
M10 AGP & CLOCKS
CARDBUS CONTROLLER (PCI1510)
INTREPID DECOUPLING
INTREPID POWER RAILS
FIREWIRE A/B PHY
34
21
16
15
19
7
6
MPC7450 MAXBUS INTERFACE
PCB NOTES AND HOLES
POWER BLOCK DIAGRAM
CONTENTS
1
820-1524
PCBF,MLB,PB17 INCH
PCB1
PRODUCTION RELEASED
051-6531
44
?
293301B
1
09/11/03
SCHEM,MLB,PB17 INCH
B
051-6531
SCHEM,MLB,PB17 INCH
SCH1
1