Analog Devices SMP18FP, SMP18FRU, SMP18FS Datasheet

a		Octal Sample-and-Hold
		with Multiplexed Input
		SMP18

FEATURES

High Speed Version of SMP08

Internal Hold Capacitors

Low Droop Rate

TTL/CMOS Compatible Logic Inputs

Single or Dual Supply Operation

Break-Before-Make Channel Addressing

Compatible With CD4051 Pinout

Low Cost

APPLICATIONS

Multiple Path Timing Deskew for A.T.E.

Memory Programmers

Mass Flow/Process Control Systems

Multichannel Data Acquisition Systems

Robotics and Control Systems

Medical and Analytical Instrumentation

Event Analysis

Stage Lighting Control

GENERAL DESCRIPTION

The SMP18 is a monolithic octal sample-and-hold; it has eight internal buffer amplifiers, input multiplexer, and internal hold capacitors. It is manufactured in an advanced oxide isolated CMOS technology to obtain high accuracy, low droop rate, and fast acquisition time. The SMP18 has a typical linearity error of only 0.01% and can accurately acquire a 10-bit input signal to

±1/2 LSB in less than 2.5 microseconds. The SMP18’s output swing includes the negative supply in both single and dual supply operation.

The SMP18 was specifically designed for systems that use a calibration cycle to adjust a multiple of system parameters. The low cost and high level of integration make the SMP18 ideal for calibration requirements that have previously required an ASIC, or high cost multiple D/A converters.

The SMP18 is also ideally suited for a wide variety of sample- and-hold applications including amplifier offset or VCA gain adjustments. One or more SMP18s can be used with single or multiple DACs to provide multiple set points within a system.

FUNCTIONAL BLOCK DIAGRAM

	(LSB)		(MSB)
INPUT	A	B	C	INH
3	11	10	9	6
		1 OF 8 DECODER			8	DGND
					16	VDD
				SW	13	CH0OUT
				SW	14	CH1OUT
			SW		15	CH2OUT
			SW		12	CH3OUT
		SW			1	CH4OUT
		SW			5	CH5OUT
	SW				2	CH6OUT
	SW				4	CH7OUT
HOLD CAPS
(INTERNAL)
SMP18					7	VSS

The SMP18 offers significant cost and size reduction over discrete designs. It is available in a 16-pin plastic DIP, a narrow body SO-16 surface-mount SOIC package or the thin TSSOP-16 package. The SMP18 is a higher speed direct replacement for the SMP08.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Fax: [phone]	© Analog Devices, Inc., 1996

SMP18–SPECIFICATIONS

	ELECTRICAL CHARACTERISTICS					(@ VDD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP18F,
						unless otherwise noted)
	Parameter		Symbol			Conditions	Min	Typ	Max		Units
	Linearity Error					–3 V ≤ VIN ≤ +3 V		0.01		%
	Buffer Offset Voltage		VOS			TA = +25°C, VIN = 0 V		2.5	10		mV
						–40°C ≤ TA ≤ +85°C, VIN = 0 V		3.5	20		mV
	Hold Step		VHS			VIN = 0 V, TA = +25°C to +85°C		4	6		mV
						VIN = 0 V, TA = –40°C			8		mV
	Droop Rate		VCH/ t			TA = +25°C, VIN = 0 V		2	40		mV/s
	Output Source Current		ISOURCE			VIN = 0 V1	1.2				mA
	Output Sink Current		ISINK			VIN = 0 V1	0.5				mA
	Output Voltage Range					RL = 20 kΩ	–3.0		+3.0		V
	LOGIC CHARACTERISTICS
	Logic Input High Voltage		VINH				2.4				V
	Logic Input Low Voltage		VINL						0.8		V
	Logic Input Current		IIN			VIN = 2.4 V		0.5	1		μA
	DYNAMIC PERFORMANCE2					TA = +25°C, –3 V to +3 V to 0.1%					μs
	Acquisition Time3		tAQ					3.5
	Hold Mode Settling Time		tH			To ±1 mV of Final Value		1			μs
	Channel Select Time		tCH					90			ns
	Channel Deselect Time		tDCS					45			ns
	Inhibit Recovery Time		tIR					90			ns
	Slew Rate		SR					6			V/μs
	Capacitive Load Stability					<30% Overshoot		500			pF
	Analog Crosstalk					–3 V to +3 V Step		–72			dB
	SUPPLY CHARACTERISTICS					VSS = ±5 V to ±6 V
	Power Supply Rejection Ratio		PSRR				60	75			dB
	Supply Current		IDD			TA = +25°C		5.5	7.5		mA
						–40°C ≤ TA ≤ +85°C		7.5	9.5		mA
						(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP18F,
	ELECTRICAL CHARACTERISTICS unless otherwise noted)
	Parameter		Symbol			Conditions	Min	Typ	Max		Limits
	Linearity Error					60 mV ≤ VIN ≤ 10 V		0.01			%
	Buffer Offset Voltage		VOS			TA = +25°C, VIN = 6 V		2.5	10		mV
						–40°C ≤ TA ≤ +85°C, VIN = 6 V		3.5	20		mV
	Hold Step		VHS			VIN = 6 V, TA = +25°C to +85°C		4	6		mV
						VIN = 6 V, TA = –40°C			8		mV
	Droop Rate		VCH/ t			TA = +25°C, VIN = 6 V		2	40		mV/s
	Output Source Current		ISOURCE			VIN = 6 V1	1.2				mA
	Output Sink Current		ISINK			VIN = 6 V1	0.5				mA
	Output Voltage Range					RL = 20 kΩ	0.06		10.0		V
						RL = 10 kΩ	0.06		9.5		V
	LOGIC CHARACTERISTICS						2.4				V
	Logic Input High Voltage		VINH
	Logic Input Low Voltage		VINL						0.8		V
	Logic Input Current		IIN			VIN = 2.4 V		0.5	1		μA
	DYNAMIC PERFORMANCE2					TA = +25°C, 0 to 10 V to 0.1%					μs
	Acquisition Time3		tAQ					2.5	3.25
	Hold Mode Settling Time		tH			To ±1 mV of Final Value		1			μs
	Channel Select Time		tCH					90			ns
	Channel Deselect Time		tDCS					45			ns
	Inhibit Recovery Time		tIR					90			ns
	Slew Rate4		SR					7			V/μs
	Capacitive Load Stability					<30% Overshoot		500			pF
	Analog Crosstalk					0 V to 10 V Step		–72			dB
	SUPPLY CHARACTERISTICS					10.8 V ≤ VDD ≤ 13.2 V
	Power Supply Rejection Ratio		PSRR				60	75			dB
	Supply Current		IDD			TA = +25°C		6.0	8.0		mA
						–40°C ≤ TA ≤ +85°C		8.0	10.0		mA

NOTES

1Outputs are capable of sinking and sourcing over 10 mA but offset is guaranteed at specified load levels.

2All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 3This parameter is guaranteed without test.

4Slew rate is measured in the sample mode with a 0 to 10 V step from 20% to 80%.

Specifications subject to change without notice.

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SMP18

ABSOLUTE MAXIMUM RATINGS

VDD to DGND . . . . . . . . . . . . . . .	. . . . . . . . . . . . –0.3 V, 17 V
VDD to VSS . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . –0.3 V, 17 V
VLOGIC to DGND . . . . . . . . . . . .	. . . . . . . . . . . . –0.3 V, VDD
VIN to DGND . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . VSS, VDD
VOUT to DGND . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . VSS, VDD
Analog Output Current . . . . . . . . .	. . . . . . . . . . . . . . ±20 mA
	(Not short-circuit protected)

Operating Temperature Range

FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C

Package Type	uJA*	uJC	Units
16-Pin Plastic DIP (P)	76	33	°C/W
16-Pin SOIC (S)	92	27	°C/W
16-Lead TSSOP (RU)	180	35	°C/W

NOTES

*θJA is specified for worst case mounting conditions, i.e., θJA is specified for device in socket for plastic DIP packages; θJA is specified for device soldered to printed circuit board for SOIC and TSSOP packages.

PIN CONNECTIONS

CH4OUT				VDD
	1		16
CH6OUT				CH2OUT
	2		15
INPUT				CH1OUT
	3	SMP18	14
CH7OUT				CH0OUT
	4		13
CH5OUT		TOP VIEW		CH3OUT
	5	(Not to Scale)	12
INH
	6		11	A CONTROL
VSS
	7		10	B CONTROL
DGND
	8		9	C CONTROL

ORDERING GUIDE

	Temperature	Package	Package
Model	Range	Description	Option
SMP18FP	–40°C to +85°C	Plastic DIP	N-16
SMP18FRU	–40°C to +85°C	TSSOP-16	RU-16
SMP18FS	–40°C to +85°C	SO-16	R-16A

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SMP18 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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