a |
Four-Channel, Four-Quadrant |
Analog Multiplier |
Four Independent Channels Voltage IN, Voltage OUT No External Parts Required 8 MHz Bandwidth
Four-Quadrant Multiplication Voltage Output; W = (X ´ Y)/2.5 V
0.2% Typical Linearity Error on X or Y Inputs Excellent Temperature Stability: 0.005%
±2.5 V Analog Input Range Operates from ±5 V Supplies
Low Power Dissipation: 150 mW typ Spice Model Available
Geometry Correction in High-Resolution CRT Displays
Waveform Modulation & Generation
Voltage Controlled Amplifiers
Automatic Gain Control
Modulation and Demodulation
GENERAL DESCRIPTION
The MLT04 is a complete, four-channel, voltage output analog multiplier packaged in an 18-pin DIP or SOIC-18. These complete multipliers are ideal for general purpose applications such as voltage controlled amplifiers, variable active filters, “zipper” noise free audio level adjustment, and automatic gain control. Other applications include cost-effective multiple-channel power calculations
(I ´ V), polynomial correction generation, and low frequency modulation. The MLT04 multiplier is ideally suited for generating complex, high-order waveforms especially suitable for geometry correction in high-resolution CRT display systems.
40 |
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VCC = +5V |
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VEE = –5V |
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20 |
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TA |
= +25°C |
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90 |
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dB–GAINAv |
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Ø (X OR Y) |
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DegreesPhase–Ø |
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8.9MHz |
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0 |
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Av (X OR Y) |
–3dB |
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–20 |
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–90 |
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X & Y MEASUREMENTS |
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SUPERIMPOSED: |
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–40 |
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X = 100mV RMS, Y = 2.5V DC |
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Y = 100mV RMS, X = 2.5V DC |
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1k |
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10k |
100k |
1M |
10M |
100M |
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FREQUENCY – Hz |
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MLT04
18-Lead Epoxy DIP (P Suffix)
18-Lead Wide Body SOIC (S Suffix)
W1 |
1 |
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18 |
W4 |
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GND1 |
2 |
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17 |
GND4 |
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X1 |
3 |
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16 |
X4 |
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Y1 |
4 |
MLT-04 |
15 |
Y4 |
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VCC |
5 |
14 |
VEE |
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MLT04 |
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9876543210876532 |
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Y2 |
6 |
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13 |
Y3 |
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X2 |
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12 |
X3 |
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GND2 |
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11 |
GND3 |
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W2 |
9 |
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10 |
W3 |
W = (X • Y)/2.5V
Fabricated in a complementary bipolar process, the MLT04 includes four 4-quadrant multiplying cells which have been lasertrimmed for accuracy. A precision internal bandgap reference normalizes signal computation to a 0.4 scale factor. Drift over temperature is under 0.005%/°C. Spot noise voltage of 0.3 mV/ÖHz results in a THD + Noise performance of 0.02% (LPF = 22 kHz) for the lower distortion Y channel. The four 8 MHz channels consume a total of 150 mW of quiescent power.
The MLT04 is available in 18-pin plastic DIP, and SOIC-18 surface mount packages. All parts are offered in the extended industrial temperature range (–40°C to +85°C).
100
VCC = +5V
10VEE = –5V TA = +25°C
%– |
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NOISE+ |
1 |
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LPF = 500kHz |
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THD |
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THDX: X = 2.5VP, Y = +2.5V DC |
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0.1 |
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THDY: Y = 2.5VP, X = +2.5V DC |
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0.01 |
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10 |
100 |
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1k |
10k |
100k |
1M |
FREQUENCY – Hz
Figure 1. Gain & Phase vs. Frequency Response
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Figure 2. THD + Noise vs. Frequency
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
MLT04–SPECIFICATIONS (VCC = +5 V, VEE = –5 V, VIN = ±2.5 VP, RL = 2 kΩ, TA = +25°C unless otherwise noted.)
Parameter |
Symbol |
Conditions |
Min |
Typ |
Max |
Units |
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MULTIPLIER PERFORMANCE1 |
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±2 |
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Total Error2 X |
EX |
–2.5 V < X < +2.5 V, Y = +2.5 V |
–5 |
5 |
% FS |
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Total Error2 Y |
EY |
–2.5 V < Y < +2.5 V, X = +2.5 V |
–5 |
±2 |
5 |
% FS |
Linearity Error2 X |
LEX |
–2.5 V < X < +2.5 V, Y = +2.5 V |
–1 |
±0.2 |
+1 |
% FS |
Linearity Error2 Y |
LEY |
–2.5 V < Y < +2.5 V, X = +2.5 V |
–1 |
±0.2 |
+1 |
% FS |
Total Error Drift |
TCEX |
X = –2.5 V, Y = 2.5 V, TA = –40°C to +85°C |
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0.005 |
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%/°C |
Total Error Drift |
TCEY |
Y = –2.5 V, X = 2.5 V, TA = –40°C to +85°C |
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0.005 |
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%/°C |
Scale Factor3 |
K |
X = ±2.5 V, Y = ±2.5 V, TA = –40°C to +85°C |
0.38 |
0.40 |
0.42 |
1/V |
Output Offset Voltage |
ZOS |
X = 0 V, Y = 0 V, TA= –40°C to +85°C |
–50 |
±10 |
50 |
mV |
Output Offset Drift |
TCZOS |
X = 0 V, Y = 0 V, TA= –40°C to +85°C |
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mV/°C |
Offset Voltage, X |
XOS |
X = 0 V, Y = ±2.5 V, TA = –40°C to +85°C |
–50 |
±10.5 |
50 |
mV |
Offset Voltage, Y |
YOS |
Y = 0 V, X = ±2.5 V, TA = –40°C to +85°C |
–50 |
±10.5 |
50 |
mV |
DYNAMIC PERFORMANCE |
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Small Signal Bandwidth |
BW |
VOUT = 0.1 V rms |
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Slew Rate |
SR |
VOUT = ±2.5 V |
30 |
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V/ms |
Settling Time |
tS |
VOUT = D2.5 V to 1% Error Band |
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AC Feedthrough |
FTAC |
X = 0 V, Y = 1 V rms @ f = 100 kHz |
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dB |
Crosstalk @ 100 kHz |
CTAC |
X = Y = 1 V rms Applied to Adjacent Channel |
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–90 |
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dB |
OUTPUTS |
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mV rms |
Audio Band Noise |
EN |
f = 10 Hz to 50 kHz |
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Wide Band Noise |
EN |
Noise BW = 1.9 MHz |
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mV rms |
Spot Noise Voltage |
eN |
f = 1 kHz |
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0.3 |
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mV/ÖHz |
Total Harmonic Distortion |
THDX |
f = 1 kHz, LPF = 22 kHz, Y = 2.5 V |
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0.1 |
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THDY |
f = 1 kHz, LPF = 22 kHz, X = 2.5 V |
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0.02 |
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% |
Open Loop Output Resistance |
ROUT |
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40 |
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W |
Voltage Swing |
VPK |
VCC = +5 V, VEE = –5 V |
±3.0 |
±3.3 |
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VP |
Short Circuit Current |
ISC |
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30 |
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mA |
INPUTS |
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Analog Input Range |
IVR |
GND = 0 V |
–2.5 |
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+2.5 |
V |
Bias Current |
IB |
X = Y = 0 V |
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2.3 |
10 |
mA |
Resistance |
RIN |
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1 |
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MW |
Capacitance |
CIN |
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3 |
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pF |
SQUARE PERFORMANCE |
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Total Square Error |
ESQ |
X = Y = 1 |
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5 |
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% FS |
POWER SUPPLIES |
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VCC = 5.25 V, VEE = –5.25 V |
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20 |
mA |
Positive Current |
ICC |
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Negative Current |
IEE |
VCC = 5.25 V, VEE = –5.25 V |
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20 |
mA |
Power Dissipation |
PDISS |
Calculated = 5 V ´ ICC + 5 V ´ IEE |
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200 |
mW |
Supply Sensitivity |
PSSR |
X = Y = 0 V, VCC = D5% or VEE = D5% |
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10 |
mV/V |
Supply Voltage Range |
VRANGE |
For VCC & VEE |
±4.75 |
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±5.25 |
V |
NOTES
1Specifications apply to all four multipliers.
2Error is measured as a percent of the ±2.5 V full scale, i.e., 1% FS = 25 mV.
3Scale Factor K is an internally set constant in the multiplier transfer equation W = K × X × Y.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS* |
±7 V |
Supply Voltages VCC, VEE to GND |
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Inputs XI, YI |
VCC, VEE |
Outputs WI |
VCC, VEE |
Operating Temperature Range |
–40°C to +85°C |
Maximum Junction Temperature (TJ max) |
+150°C |
Storage Temperature |
–65°C to +150°C |
Lead Temperature (Soldering, 10 sec) |
+300°C |
Package Power Dissipation |
(TJ max–TA)/qJA |
Thermal Resistance qJA |
74°C/W |
PDIP-18 (N-18) |
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SOIC-18 (SOL-18) |
89°C/W |
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification are not implied.
ORDERING INFORMATION*
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Temperature |
Package |
Package |
Model |
Range |
Description |
Option |
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MLT04GP |
–40°C to +85°C |
18-Pin P-DIP |
N-18 |
MLT04GS |
–40°C to +85°C |
18-Lead SOIC |
SOL-18 |
MLT04GS-REEL |
–40°C to +85°C |
18-Lead SOIC |
SOL-18 |
MLT04GBC |
+25°C |
Die |
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*For die specifications contact your local Analog sales office. The MLT04 contains 211 transistors.
–2– |
REV. B |
MLT04
The MLT04 is a low cost quad, 4-quadrant analog multiplier with single-ended voltage inputs and voltage outputs. The functional block diagram for each of the multipliers is illustrated in Figure 3. Due to packaging constraints, access to internal nodes for externally adjusting scale factor, output offset voltage, or additional summing signals is not provided.
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+VS |
X1, X2, X3, X4 |
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MLT04 |
G1, G2, G3, G4 |
0.4 |
W1, W2, W3, W4 |
Y1, Y2, Y3, Y4
–VS
Figure 3. Functional Block Diagram of Each MLT04
Multiplier
Each of the MLT04’s analog multipliers is based on a Gilbert cell multiplier configuration, a 1.23 V bandgap reference, and a unityconnected output amplifier. Multiplier scale factor is determined through a differential pair/trimmable resistor network external to the core. An equivalent circuit for each of the multipliers is shown in Figure 4.
VCC
W INTERNAL OUT
BIAS
XIN |
22k |
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22k |
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22k |
SCALE |
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GND |
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FACTOR |
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YIN |
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200µA |
200µA |
200µA |
200µA |
200µA |
200µA |
VEE
Figure 4. Equivalent Circuit for the MLT04
Details of each multiplier’s output-stage amplifier are shown in Figure 5. The output stages idles at 200 μA, and the resistors in series with the emitters of the output stage are 25 Ω. The output stage can drive load capacitances up to 500 pF without oscillation. For loads greater than 500 pF, the outputs of the MLT04 should be isolated from the load capacitance with a 100 Ω resistor.
VCC
25Ω
W OUT
25Ω
VEE
Figure 5. Equivalent Circuit for MLT04 Output Stages
Multiplier errors consist primarily of input and output offsets, scale factor errors, and nonlinearity in the multiplying core. An expression for the output of a real analog multiplier is given by:
VO = ( K + |
K ){(VX + X OS )(VY + Y OS ) + ZOS + f ( X , Y )} |
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where: K |
= |
Multiplier Scale Factor |
K |
= |
Scale Factor Error |
VX |
= |
X-Input Signal |
XOS |
= |
X-Input Offset Voltage |
VY |
= |
Y-Input Signal |
YOS |
= |
Y-Input Offset Voltage |
ZOS |
= Multiplier Output Offset Voltage |
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ƒ(X, Y) = |
Nonlinearity |
Executing the algebra to simplify the above expression yields expressions for all the errors in an analog multiplier:
Term |
Description |
Dependence on Input |
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KVXVY |
True Product |
Goes to Zero As Either or |
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Both Inputs Go to Zero |
KVYVY |
Scale-Factor Error |
Goes to Zero at VX, VY = 0 |
VXYOS |
Linear “X” Feedthrough |
Proportional to VX |
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Due to Y-Input Offset |
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VYXOS |
Linear “Y” Feedthrough |
Proportional to VY |
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Due to X-Input Offset |
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XOSYOS |
Output Offset Due to X-, |
Independent of VX, VY |
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Y-Input Offsets |
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ZOS |
Output Offset |
Independent of VX, VY |
ƒ(X, Y) |
Nonlinearity |
Depends on Both VX, VY. |
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Contains Terms Dependent |
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on VX, VY, Their Powers |
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and Cross Products |
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As shown in the table, the primary static errors in an analog multiplier are input offset voltages, output offset voltage, scale factor, and nonlinearity. Of the four sources of error, only two are externally trimmable in the MLT04: the X- and Y-input offset voltages. Output offset voltage in the MLT04 is factory-trimmed to
±50 mV, and the scale factor is internally adjusted to ±2.5% of full scale. Input offset voltage errors can be eliminated by using the optional trim circuit of Figure 6. This scheme then reduces the net error to output offset, scale-factor (gain) error, and an irreducible nonlinearity component in the multiplying core.
+VS |
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50kΩ |
I |
50kΩ |
±100mV |
FOR XOS, YOS TRIM |
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CONNECT TO SUM |
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NODE OF AN EXT OP AMP |
–VS |
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Figure 6. Optional Offset Voltage Trim Configuration
REV. B |
–3– |
MLT04
Feedthrough
In the ideal case, the output of the multiplier should be zero if either input is zero. In reality, some portion of the nonzero input will “feedthrough” the multiplier and appear at the output. This is caused by the product of the nonzero input and the offset voltage of the “zero” input. Introducing an offset equal to and opposite of the “zero” input offset voltage will null the linear component of the feedthrough. Residual feedthrough at the output of the multiplier is then irreducible core nonlinearity.
Typical X- and Y-input feedthrough curves for the MLT04 are shown in Figures 7 and 8, respectively. These curves illustrate MLT04 feedthrough after “zero” input offset voltage trim.
Residual X-input feedthrough measures 0.08% of full scale, whereas residual Y-input feedthrough is almost immeasurable.
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X-INPUT: ±2.5V @ 10Hz |
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100 |
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YOS NULLED |
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5mV/DIV– |
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90 |
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TA = +25°C |
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VERTICAL |
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0% |
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HORIZONTAL – 0.5V/DIV
Figure 7. X-Input Feedthrough with YOS Nulled
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Y-INPUT: ±2.5V @ 10Hz |
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100 |
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XOS NULLED |
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5mV/DIV– |
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90 |
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TA = +25°C |
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VERTICAL |
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0% |
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HORIZONTAL – 0.5V/DIV
Figure 8. Y-Input Feedthrough with XOS Nulled
Nonlinearity
Multiplier core nonlinearity is the irreducible component of error. It is the difference between actual performance and “best-straight- line” theoretical output, for all pairs of input values. It is expressed as a percentage of full scale with all other dc errors nulled. Typical X- and Y-input nonlinearities for the MLT04 are shown in Figures 9 through 12. Worst-case X-input nonlinearity measured less than 0.2%, and Y-input nonlinearity measured better than 0.06%. For modulator/demodulator or mixer applications it is, therefore, recommended that the carrier be connected to the X-input while the signal is applied to the Y-input.
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5mV/DIV– |
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90 |
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VERTICAL |
0% |
YOS NULLED |
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X-INPUT: ±2.5V @ 10Hz |
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10 |
Y-INPUT: +2.5V |
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TA = +25°C |
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HORIZONTAL – 0.5V/DIV
Figure 9. X-Input Nonlinearity @ Y = +2.5 V
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100 |
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5mV/DIV– |
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90 |
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VERTICAL |
0% |
YOS NULLED |
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X-INPUT: ±2.5V @ 10Hz |
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10 |
Y-INPUT: –2.5V |
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TA = +25°C |
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HORIZONTAL – 0.5V/DIV
Figure 10. X-Input Nonlinearity @ Y = –2.5 V
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Y-INPUT: ±2.5V @ 10Hz |
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100 |
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X-INPUT: +2.5V |
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XOS NULLED |
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5mV/DIV– |
90 |
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TA = +25°C |
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VERTICAL |
10 |
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0% |
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HORIZONTAL – 0.5V/DIV
Figure 11. Y-Input Nonlinearity @ X = +2.5 V
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Y-INPUT: ±2.5V @ 10Hz |
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100 |
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X-INPUT: –2.5V |
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XOS NULLED |
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5mV/DIV– |
90 |
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TA = +25°C |
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VERTICAL |
10 |
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0% |
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HORIZONTAL – 0.5V/DIV
Figure 12. Y-Input Nonlinearity @ X = –2.5 V
–4– |
REV. B |
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