Analog Devices AD5533 Datasheet

32-Channel Infinite

a

FEATURES
Infinite Sample-and-Hold Capability to ⴞ0.018% Accuracy
High Integration: 32-Channel SHA in 12 ⴛ 12 mm
Per Channel Acquisition Time of 16 ␮s max
Adjustable Voltage Output Range
Output Voltage Span 10 V
Output Impedance 0.5 ⍀
Readback Capability
DSP-/Microcontroller-Compatible Serial Interface
Parallel Interface
Temperature Range –40ⴗC to +85ⴗC

APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
Low Cost I/O

2

LFBGA

Sample-and-Hold

AD5533*

GENERAL DESCRIPTION

The AD5533 combines a 32-channel voltage translation function
with an infinite output hold capability. An analog input voltage
on the common input pin, V
sentation transferred to a chosen DAC register. V
DAC is then updated to reflect the new contents of the DAC
register. Channel selection is accomplished via the parallel address
inputs A0–A4 or via the serial input port. The output voltage
range is determined by the offset voltage at the OFFS_IN pin
and the gain of the output amplifier. It is restricted to a range
from V

+ 2 V to VDD – 2 V because of the headroom of the

SS

output amplifier.

The device is operated with AV

5.25 V, V

= –4.75 V to –16.5 V and VDD = 8 V to 16.5 V and

SS

requires a stable 3 V reference on REF_IN as well as an offset
voltage on OFFS_IN.

PRODUCT HIGHLIGHTS

1. Infinite Droopless Sample-and-Hold Capability.

2. The AD5533 is available in a 74-lead LFBGA package with a

body size of 12 mm × 12 mm.

, is sampled and its digital repre-

IN

= 5 V ± 5%, DVCC = 2.7 V to

CC

OUT

for this

FUNCTIONAL BLOCK DIAGRAM

DV

AV

CC

V

IN

TRACK /RESET

BUSY

GND

DAC

AGND

DGND

SER / PAR

*Protected by U.S. Patent No. 5,969,657; other patents pending.

AD5533

SCLK

ADC

INTERFACE

CONTROL

LOGIC

DIND

REF IN REF OUT

CC

OUT

DAC

DAC

DAC

SYNC/ CS

OFFS IN

ADDRESS INPUT REGISTER

A4– A0

CAL

VDDV

OFFSET SEL

SS

V

0

OUT

V

31

OUT

OFFS OUT

WR

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

(VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V

AD5533–SPECIFICATIONS

V

+ 2 V to VDD – 2 V. All outputs unloaded. All specifications T

SS

Parameter

1

to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from

to T

MIN

A Version

unless otherwise noted.)

MAX

2

Unit Conditions/Comments

ANALOG CHANNEL

V

IN

to V

Nonlinearity ±0.018 % max Input Range 100 mV to 2.96 V

OUT

±0.006 % typ After Gain and Offset Adjustment

Gain 3.46/3.6 min/max 3.52 typ
Offset Error ±50 mV max

ANALOG INPUT (V

)

IN

Input Voltage Range 0 to 3 V Nominal Input Range
Input Lower Deadband 70 mV max 50 mV typ. Referred to V

See Figure 5

Input Upper Deadband 40 mV max 12 mV typ. Referred to V

See Figure 5

Input Current 1 µA max 100 nA typ. V

One Channel

Input Capacitance

3

20 pF typ

Being Acquired on

IN

ANALOG INPUT (OFFS_IN)

Input Current 1 µA max 100 nA typ

VOLTAGE REFERENCE

REF_IN

Nominal Input Voltage 3.0 V
Input Voltage Range

3

2.85/3.15 V min/max

Input Current 1 µA max <1 nA typ

REF_OUT

Output Voltage 3 V typ
Output Impedance
Reference Temperature Coefficient

ANALOG OUTPUTS (V

Output Temperature Coefficient

3

3

0–31)

OUT

3, 4

280 kΩ typ
60 ppm/°C typ

20 ppm/°C typ

DC Output Impedance 0.5 Ω typ
Output Range V
Resistive Load
Capacitive Load
Short-Circuit Current
DC Power Supply Rejection Ratio

DC Crosstalk

ANALOG OUTPUT (OFFS_OUT)

Output Temperature Coefficient
DC Output Impedance

3, 5

3, 5

3

3

3

3, 4

3

+ 2 /VDD – 2 V min/max 100 µA Output Load

SS

5kΩ min
500 pF max
10 mA typ
–70 dB typ VDD = +15 V ± 5%
–70 dB typ V

= –15 V ± 5%

SS

250 µV max

20 ppm/°C typ

1.3 kΩ typ

Output Range 50 to REF_IN – 12 mV typ
Output Current 10 µA max Source Current
Capacitive Load 100 pF max

DIGITAL INPUTS

3

Input Current ±10 µA max 5 µA typ
Input Low Voltage 0.8 V max DV

0.4 V max DV

Input High Voltage 2.4 V min DV

2.0 V min DV

= 5 V ± 5%

CC

= 3 V ± 10%

CC

= 5 V ± 5%

CC

= 3 V ± 10%

CC

Input Hysteresis (SCLK and CS Only) 200 mV typ
Input Capacitance 10 pF max

DIGITAL OUTPUTS (BUSY, DOUT)

3

Output Low Voltage 0.4 V max DVCC = 5 V. Sinking 200 µA
Output High Voltage 4.0 V min DV
Output Low Voltage 0.4 V max DV
Output High Voltage 2.4 V min DV
High Impedance Leakage Current ±1 µA max D
High Impedance Output Capacitance 15 pF typ D

= 5 V. Sourcing 200 µA

CC

= 3 V. Sinking 200 µA

CC

= 3 V. Sourcing 200 µA

CC

Only

OUT

Only

OUT

.

IN

.

IN

–2–

REV. 0

AD5533

Parameter

1

A Version

2

Unit Conditions/Comments

POWER REQUIREMENTS

Power-Supply Voltages

V

DD

V

SS

AV

CC

DV

CC

Power-Supply Currents

I

DD

I

SS

AI

CC

DI

CC

Power Dissipation

NOTES

1

See Terminology.

2

A Version: Industrial temperature range –40°C to +85°C; typical at +25°C.

3

Guaranteed by design and characterization, not production tested.

4

AD780 as reference for the AD5533.

5

Ensure that you do not exceed TJ (max). See maximum ratings.

6

Outputs unloaded.

Specifications subject to change without notice.

6

6

8/16.5 V min/max
–4.75/–16.5 V min/max

4.75/5.25 V min/max

2.7/5.25 V min/max

15 mA max 10 mA typ. All Channels Full Scale
15 mA max 10 mA typ. All Channels Full Scale
33 mA max 26 mA typ

1.5 mA max 1 mA typ
280 mW typ VDD = +10 V, VSS = –5 V

(VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND =

AC CHARACTERISTICS

All specifications T

Parameter A Version

Output Settling Time
Acquisition Time 16 µs max
OFFS_IN Settling Time
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
AC Crosstalk

NOTES

1

A version: Industrial temperature range –40°C to +85°C; typical at 25°C.

2

Guaranteed by design and characterization, not production tested

Specifications subject to change without notice.

to T

MIN

2

unless otherwise noted.)

MAX

2

2

2

DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from V

1

Unit Conditions/Comments

3 µs max

10 µs max 500 pF, 5 kΩ Load; 0 V–3 V Step

2

0.2 nV-s typ
400 nV/(√Hz) typ
5 nV-s typ

+ 2 V to VDD – 2 V. All outputs unloaded.

SS

REV. 0

–3–

AD5533

TIMING CHARACTERISTICS

PARALLEL INTERFACE

Parameter

t

1

t

2

t

3

t

4

t

5

t

6

NOTES

1

See Interface Timing Diagram.

2

Guaranteed by design and characterization, not production tested.

Specifications subject to change without notice.

1, 2

Limit at T
(A Version) Unit Conditions/Comments

0 ns min CS to WR Setup Time
0 ns min CS to WR Hold Time
50 ns min CS Pulsewidth Low
50 ns min WR Pulsewidth Low
20 ns min A4–A0, CAL, OFFS_SEL to WR Setup Time
0 ns min A4–A0, CAL, OFFS_SEL to WR Hold Time

SERIAL INTERFACE

Parameter

f

CLKIN

t

1

t

2

t

3

t

4

t

5

t

6

t

7

3

t

8

3

t

9

t

10

NOTES

1

See Serial Interface Timing Diagrams.

2

Guaranteed by design and characterization, not production tested.

3

These numbers are measured with the load circuit of Figure 2.

Specifications subject to change without notice.

1, 2

Limit at T
(A Version) Unit Conditions/Comments

20 MHz max SCLK Frequency
20 ns min SCLK High Pulsewidth
20 ns min SCLK Low Pulsewidth
10 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time
50 ns min SYNC Low Time
10 ns min DIN Setup Time
5 ns min DIN Hold Time
5 ns min SYNC Falling Edge to SCLK Rising Edge Setup Time
20 ns max SCLK Rising Edge to D
60 ns max SCLK Falling Edge to D
400 ns min 10th SCLK Falling Edge to SYNC Falling Edge for Readback

MIN

MIN

, T

, T

MAX

MAX

Valid

OUT

High Impedance

OUT

PARALLEL INTERFACE TIMING DIAGRAM

CS

WR

A4– A0, CAL,

SEL

OFFS

Figure 1. Parallel Write (SHA Mode Only)

–4–

200␮A

TO

OUTPUT

PIN

C

L

50pF

200␮A

Figure 2. Load Circuit for D

I

OL

1.6V

I

OH

Timing Specifications

OUT

REV. 0

SERIAL INTERFACE TIMING DIAGRAMS

12345678910

t

1

t

2

t

3

t

4

t

5

t

6

MSB LSB

SCLK

SYNC

D

IN

Figure 3. 10-Bit Write (SHA Mode and Both Readback Modes)

t

1

SCLK

SYNC

D

OUT

10

t

7

t

10

2

13456789

t

2

t

4

MSB

t

8

AD5533

10

11

12 13 14

t

9

LSB

Figure 4. 14-Bit Read (Both Readback Modes)

REV. 0

–5–