FINAL |
COM'L: -12/15/20 |
IND: -14/18/24 |
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MACH110-12/15/20 |
Advanced |
Micro |
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High-Density EE CMOS Programmable Logic |
Devices |
DISTINCTIVE CHARACTERISTICS
■ 44 Pins |
■ 32 Outputs |
■ 32 Macrocells |
■ 32 Flip-flops; 2 clock choices |
■ 12 ns tPD Commercial |
■ 2 “PAL22V16” Blocks |
14 ns tPD Industrial |
■ Pin-compatible with MACH111, MACH210, |
■ 77 MHz fCNT |
MACH211, MACH215 |
■ 38 Inputs |
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GENERAL DESCRIPTION
The MACH110 is a member of AMD's high-performance EE CMOS MACH 1 family. This device has approximately three times the logic macrocell capability of the popular PAL22V10 without loss of speed.
The MACH110 consists of two PAL blocks interconnected by a programmable switch matrix. The two PAL blocks are essentially “PAL22V16” structures complete with product-term arrays and programmable macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently.
The MACH110 macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input.
Publication# 14127 Rev. I Amendment /0
Issue Date: May 1995
AMD
BLOCK DIAGRAM
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I0 – I 1, |
I/O0 – I/O 15 |
I3 – I 4 |
16 |
16 |
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I/O |
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Cells |
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16 |
16 |
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Macrocells |
2 |
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OE |
4 |
44 x 70 |
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AND Logic Array |
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and |
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Logic Allocator |
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22 |
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Switch Matrix
22 |
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44 x 70 |
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AND Logic Array |
2 |
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and |
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Logic Allocator |
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OE |
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Macrocells |
2 |
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16 |
16 |
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I/O |
2 |
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Cells |
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16 |
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16 |
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I/O16 – I/O 31 |
CLK /I |
5, |
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1 |
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CLK0/I2 |
14127I-1 |
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2 |
MACH110-12/15/20 |
AMD
CONNECTION DIAGRAM
Top View
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PLCC |
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4 |
3 |
2 |
1 |
0 |
GND |
CC |
31 |
30 |
29 |
28 |
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I/O |
I/O |
I/O |
I/O |
I/O |
V |
I/O |
I/O |
I/O |
I/O |
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6 |
5 |
4 |
3 |
2 |
1 |
44 |
43 42 |
41 |
40 |
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I/O5 |
7 |
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39 |
I/O27 |
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I/O6 |
8 |
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38 |
I/O26 |
I/O7 |
9 |
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37 |
I/O25 |
I0 |
10 |
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36 |
I/O24 |
I1 |
11 |
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35 |
CLK1/I5 |
GND |
12 |
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34 |
GND |
CLK0/I2 |
13 |
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33 |
I4 |
I/O8 |
14 |
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32 |
I3 |
I/O9 |
15 |
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31 |
I/O23 |
I/O10 |
16 |
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30 |
I/O22 |
I/O11 |
17 |
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20 |
21 22 |
23 |
24 |
25 |
26 |
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29 |
I/O21 |
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18 19 |
27 28 |
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12 |
13 |
14 |
15 |
CC |
GND |
16 |
17 |
18 |
19 |
20 |
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I/O |
I/O |
I/O |
I/O |
V |
I/O |
I/O |
I/O |
I/O |
I/O |
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14127I-2
Note:
Pin-compatible with MACH111, MACH210, MACH211, and MACH215.
PIN DESIGNATIONS
CLK/I = |
Clock or Input |
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GND = |
Ground |
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I |
= |
Input |
I/O |
= |
Input/Output |
VCC |
= |
Supply Voltage |
MACH110-12/15/20 |
3 |
AMD
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
MACH 110 -12 J C
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
DEVICE NUMBER
110 = 32 Macrocells, 44 Pins
SPEED
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
PACKAGE TYPE
-12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD
Valid Combinations
MACH110-12
MACH110-15 JC
MACH110-20
J= 44-Pin Plastic Leaded Chip Carrier (PL 044)
Valid Combinations
The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4 |
MACH110-12/15/20 (Com'l) |
AMD
ORDERING INFORMATION
Industrial Products
AMD programmable logic products for Industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
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MACH 110 -14 J |
I |
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FAMILY TYPE |
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OPTIONAL PROCESSING |
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MACH = Macro Array CMOS High-Speed |
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Blank = Standard Processing |
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DEVICE NUMBER |
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OPERATING CONDITIONS |
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110 |
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32 Macrocells, 44 Pins |
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I = Industrial (–40 °C to +85°C) |
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SPEED |
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PACKAGE TYPE |
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-14 |
= |
14 ns tPD |
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J = 44-Pin Plastic Leaded Chip |
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-18 |
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18 ns tPD |
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Carrier (PL 044) |
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-24 |
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24 ns tPD |
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Valid Combinations |
Valid Combinations |
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MACH110-14 |
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The Valid Combinations table lists configurations |
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planned to be supported in volume for this device. |
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MACH110-18 |
JI |
Consult the local AMD sales office to confirm availability |
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of specific valid combinations and to check on newly |
MACH110-24 |
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released combinations. |
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MACH110-14/18/25 (Ind) |
5 |
AMD
FUNCTIONAL DESCRIPTION |
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Table 1. Logic Allocation |
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The MACH110 consists of two PAL blocks connected by |
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Available |
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a switch matrix. There are 32 I/O pins and 6 dedicated |
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Output Macrocell |
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Clusters |
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input pins feeding the switch matrix. These signals are |
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M0 |
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C0, C1 |
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distributed to the two PAL blocks for efficient design |
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implementation. There are two clock pins that can also |
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M1 |
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C0, C1, C2 |
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be used as dedicated inputs. |
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M2 |
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C1, C2, C3 |
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M3 |
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C2, C3, C4 |
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The PAL Blocks |
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M4 |
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C3, C4, C5 |
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Each PAL block in the MACH110 (Figure 1) contains a |
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M5 |
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C4, C5, C6 |
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64-product-term logic array, a logic allocator, 16 macro- |
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M6 |
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C5, C6, C7 |
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cells and 16 I/O cells. The switch matrix feeds each PAL |
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M7 |
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C6, C7 |
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block with 22 inputs. This makes the PAL block look |
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M8 |
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C8, C9 |
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effectively like an independent “PAL22V16”. |
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M9 |
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C8, C9, C10 |
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There are four additional output enable product terms in |
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M10 |
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C9, C10, C11 |
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each PAL block. For purposes of output enable, the 16 |
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M11 |
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C10, C11, C12 |
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I/O cells are divided into 2 banks of 8 macrocells. Each |
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M12 |
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C11, C12, C13 |
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bank is allocated two of the output enable product terms. |
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M13 |
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C12, C13, C14 |
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An asynchronous reset product term and an asynchro- |
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M14 |
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C13, C14, C15 |
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nous preset product term are provided for flip-flop |
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M15 |
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C14, C15 |
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initialization. All flip-flops within the PAL block are |
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initialized together. |
The Macrocell |
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The Switch Matrix |
The MACH110 macrocells can be configured as either |
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registered or combinatorial, with programmable polar- |
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The MACH110 switch matrix is fed by the inputs and |
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ity. The macrocell provides internal feedback whether |
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feedback signals from the PAL blocks. Each PAL block |
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configured as registered or combinatorial. The flip-flops |
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provides |
16 internal feedback signals and 16 I/O |
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can be configured as D-type or T-type, allowing for |
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feedback signals. The switch matrix distributes these |
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product-term optimization. |
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signals back to the PAL blocks in an efficient manner |
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The flip-flops can individually select one of two clock |
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that also provides for high performance. The design |
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software automatically configures the switch matrix |
pins, which are also available as data inputs. The regis- |
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when fitting a design into the device. |
ters are clocked on the LOW-to-HIGH transition of the |
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clock signal. The flip-flops can also be asynchronously |
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The Product-Term Array |
initialized with the common asynchronous reset and |
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preset product terms. |
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The MACH110 product-term array consists of 64 |
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product |
terms for logic use, and 6 special-purpose |
The I/O Cell |
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product terms. Four of the special-purpose product |
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The I/O cell in the MACH110 consists of a three-state |
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terms provide programmable output enable, one |
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provides asynchronous reset, and one provides a |
output buffer. The three-state buffer can be configured |
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synchronous preset. Two of the output enable product |
in one of three ways: always enabled, always disabled, |
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terms are used for the first eight I/O cells; the other two |
or controlled by a product term. If product term control is |
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control the last eight macrocells. |
chosen, one of two product terms may be used to |
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provide the control. The two product terms that are |
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The Logic Allocator |
available are common to eight I/O cells. Within each |
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PAL block, two product terms are available for selection |
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The logic allocator in the MACH110 takes the 64 logic |
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by the first eight three-state outputs; two other product |
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product terms and allocates them to the 16 macrocells |
terms are available for selection by the last eight |
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as needed. Each macrocell can be driven by up to |
three-state outputs. |
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12 product terms. The design software automatically |
These choices make it possible to use the macrocell as |
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configures the logic allocator when fitting the design into |
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the device. |
an output, an input, a bidirectional pin, or a three-state |
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Table 1 illustrates which product term clusters are |
output for use in driving a bus. |
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available to each macrocell within a PAL block. Refer to |
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Figure 1 for cluster and macrocell numbers. |
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6 |
MACH110-12/15/20 |
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AMD
0 |
4 |
8 |
12 |
16 |
20 |
24 |
28 |
32 |
36 |
40 |
43 |
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
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I/O |
I/O |
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M0 |
Output |
Cell |
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Macro |
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Cell |
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I/O |
I/O |
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Output |
Cell |
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M1 |
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Macro |
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Cell |
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I/O |
I/O |
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M2 |
Output |
Cell |
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Macro |
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Cell |
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I/O |
I/O |
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M3 |
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Macro |
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Cell |
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0 |
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I/O |
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C0 |
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M4 |
Output |
Cell |
I/O |
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C1 |
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C2 |
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I/O |
I/O |
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Output |
Cell |
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M5 |
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Macro |
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C3 |
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C4 |
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I/O |
I/O |
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Output |
Cell |
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M6 |
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Allocator |
Macro |
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C5 |
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C |
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I/O |
I/O |
Switch |
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6 |
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Macro |
Cell |
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M7 |
Output |
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Matrix |
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C7 |
Logic |
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C8 |
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Output |
I/O |
I/O |
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Cell |
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M8 |
Macro |
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C9 |
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C10 |
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I/O |
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Output |
Cell |
I/O |
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M9 |
Macro |
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C11 |
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C12 |
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I/O |
I/O |
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Output |
Cell |
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C |
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M10 |
Macro |
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13 |
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C14 |
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I/O |
I/O |
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Output |
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C15 |
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M |
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Macro |
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63 |
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11 |
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I/O |
I/O |
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Output |
Cell |
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Macro |
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M12 |
Cell |
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I/O |
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Output |
Cell |
I/O |
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M13 |
Macro |
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Cell |
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I/O |
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Cell |
I/O |
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Output |
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M14 |
Macro |
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Cell |
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I/O |
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Cell |
I/O |
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Output |
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M15 |
Macro |
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Cell |
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CLK |
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4 |
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Output Enable |
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Output Enable |
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0 |
4 |
8 |
12 |
16 |
20 |
24 |
28 |
32 |
36 |
40 |
43 |
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16 |
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16 |
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14127I-3 |
Figure 1. MACH110 PAL Block
MACH110-12/15/20 |
7 |
AMD
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . |
. . . –65 °C to +150°C |
|
Ambient Temperature |
–55 °C to +125°C |
|
With Power Applied . . . . . . . . . . . |
||
Supply Voltage with |
|
|
Respect to Ground . . . . . . . . . . . |
. . –0.5 V to +7.0 V |
|
DC Input Voltage . . . . . . . . . . . . |
–0.5 V to V CC + 0.5 |
V |
DC Output or I/O |
|
|
Pin Voltage . . . . . . . . . . . . . . . . |
–0.5 V to V CC + 0.5 |
V |
Static Discharge Voltage . . . . . . |
. . . . . . . . . . 2001 |
V |
Latchup Current |
|
|
(TA = 0°C to 70°C) . . . . . . . . . . . . |
. . . . . . . . . 200 mA |
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . 0°C to +70°C
Supply Voltage (VCC)
with Respect to Ground . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter |
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Symbol |
Parameter Description |
Test Conditions |
Min |
Typ |
Max |
Unit |
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VOH |
Output HIGH Voltage |
IOH = –3.2 mA, V CC = Min |
2.4 |
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V |
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VIN = VIH or VIL |
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VOL |
Output LOW Voltage |
IOL = 16 mA, VCC = Min |
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0.5 |
V |
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VIN = VIH or VIL |
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VIH |
Input HIGH Voltage |
Guaranteed Input Logical HIGH |
2.0 |
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V |
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Voltage for all Inputs (Note 1) |
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VIL |
Input LOW Voltage |
Guaranteed Input Logical LOW |
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0.8 |
V |
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Voltage for all Inputs (Note 1) |
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IIH |
Input HIGH Current |
VIN = 5.25 V, VCC = Max (Note 2) |
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10 |
μA |
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IIL |
Input LOW Current |
VIN = 0 V, VCC = Max (Note 2) |
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–10 |
μA |
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IOZH |
Off-State Output Leakage |
VOUT = 5.25 V, VCC = Max |
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10 |
μA |
|
Current HIGH |
VIN = VIH or VIL (Note 2) |
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IOZL |
Off-State Output Leakage |
VOUT = 0 V, VCC = Max |
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–10 |
μA |
|
Current LOW |
VIN = VIH or VIL (Note 2) |
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ISC |
Output Short-Circuit Current |
VOUT = 0.5 V, VCC = Max (Note 3) |
–30 |
|
–160 |
mA |
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ICC |
Supply Current (Typical) |
VCC = 5 V, TA=25°C, |
|
95 |
|
mA |
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f = 25 MHz (Note 4) |
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Notes:
1.These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2.I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3.Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4.Measured with a 16-bit up/down counter program. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.
8 |
MACH110-12/15/20 (Com'l) |
|
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|
AMD |
|
CAPACITANCE (Note 1) |
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Parameter |
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Symbol |
Parameter Description |
Test Conditions |
Typ |
|
Unit |
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CIN |
Input Capacitance |
VIN = 2.0 V |
VCC = 5.0 V, TA = 25°C |
6 |
|
pF |
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COUT |
Output Capacitance |
VOUT = 2.0 V |
f = 1 MHz |
8 |
|
pF |
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|
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter |
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-12 |
-15 |
|
-20 |
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|||
Symbol |
Parameter Description |
|
|
Min |
Max |
Min |
|
Max |
Min |
|
Max |
Unit |
|||
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tPD |
Input, I/O, or Feedback to Combinatorial |
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12 |
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15 |
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20 |
ns |
||||
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Output (Note 3) |
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tS |
Setup Time from Input, I/O, or Feedback |
D-type |
7 |
|
10 |
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13 |
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ns |
||||
to Clock |
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T-type |
8 |
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11 |
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14 |
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ns |
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tH |
Hold Time |
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0 |
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0 |
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0 |
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ns |
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tCO |
Clock to Output (Note 3) |
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8 |
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10 |
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12 |
ns |
|||
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tWL |
Clock Width |
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LOW |
6 |
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6 |
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8 |
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ns |
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tWH |
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HIGH |
6 |
|
6 |
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8 |
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ns |
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External Feedback |
|
1/(tS + tCO) |
D-type |
66.7 |
|
50 |
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40 |
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MHz |
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Maximum |
|
T-type |
62.5 |
|
47.6 |
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38.5 |
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MHz |
|||
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||||||
fMAX |
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|
D-type |
76.9 |
|
66.6 |
|
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47.6 |
|
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MHz |
|
Frequency |
|
Internal Feedback (fCNT) |
|
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||||||||
|
(Note 1) |
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|||
|
T-type |
71.4 |
|
55.5 |
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43.5 |
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MHz |
|||||
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No Feedback |
|
1/(tWL + tWH) |
|
83.3 |
|
83.3 |
|
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62.5 |
|
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MHz |
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||
tAR |
Asynchronous Reset to Registered Output |
|
|
16 |
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20 |
|
|
25 |
ns |
||||
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|||
tARW |
Asynchronous Reset Width (Note 1) |
|
|
12 |
|
15 |
|
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20 |
|
|
ns |
|||
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|||
tARR |
Asynchronous Reset Recovery Time (Note 1) |
|
8 |
|
10 |
|
|
15 |
|
|
ns |
||||
|
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|||
tAP |
Asynchronous Preset to Registered Output |
|
|
16 |
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|
20 |
|
|
25 |
ns |
||||
|
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|
|||
tAPW |
Asynchronous Preset Width (Note 1) |
|
12 |
|
15 |
|
|
20 |
|
|
ns |
||||
|
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|
|||
tAPR |
Asynchronous Preset Recovery Time (Note 1) |
|
8 |
|
10 |
|
|
15 |
|
|
ns |
||||
|
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|||
tEA |
Input, I/O, or Feedback to Output Enable (Note 3) |
|
|
12 |
|
|
15 |
|
|
20 |
ns |
||||
|
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|
||||
tER |
Input, I/O, or Feedback to Output Disable (Note 3) |
|
|
12 |
|
|
15 |
|
|
20 |
ns |
||||
|
|
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|
|
Notes:
1.These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
2.See Switching Test Circuit, for test conditions.
3.Parameters measured with 16 outputs switching.
MACH110-12/15/20 (Com'l) |
9 |