AMD MACH110-24JI, MACH110-20JC, MACH110-18JI, MACH110-15JC, MACH110-14JI Datasheet

...
0 (0)

FINAL

COM'L: -12/15/20

IND: -14/18/24

 

 

 

MACH110-12/15/20

Advanced

Micro

High-Density EE CMOS Programmable Logic

Devices

DISTINCTIVE CHARACTERISTICS

44 Pins

32 Outputs

32 Macrocells

32 Flip-flops; 2 clock choices

12 ns tPD Commercial

2 “PAL22V16” Blocks

14 ns tPD Industrial

Pin-compatible with MACH111, MACH210,

77 MHz fCNT

MACH211, MACH215

38 Inputs

 

 

 

GENERAL DESCRIPTION

The MACH110 is a member of AMD's high-performance EE CMOS MACH 1 family. This device has approximately three times the logic macrocell capability of the popular PAL22V10 without loss of speed.

The MACH110 consists of two PAL blocks interconnected by a programmable switch matrix. The two PAL blocks are essentially “PAL22V16” structures complete with product-term arrays and programmable macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently.

The MACH110 macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input.

Publication# 14127 Rev. I Amendment /0

Issue Date: May 1995

AMD

BLOCK DIAGRAM

 

I0 – I 1,

I/O0 – I/O 15

I3 – I 4

16

16

 

I/O

 

Cells

 

16

16

 

Macrocells

2

 

OE

4

44 x 70

AND Logic Array

 

and

 

Logic Allocator

 

22

 

Switch Matrix

22

 

 

 

44 x 70

 

 

 

AND Logic Array

2

 

 

and

 

 

 

 

 

Logic Allocator

 

 

 

OE

 

 

 

Macrocells

2

 

 

 

 

 

16

16

 

 

I/O

2

 

 

Cells

 

 

 

16

 

 

16

 

 

 

I/O16 – I/O 31

CLK /I

5,

 

1

 

 

CLK0/I2

14127I-1

 

 

 

2

MACH110-12/15/20

AMD

CONNECTION DIAGRAM

Top View

 

 

 

 

 

 

PLCC

 

 

 

 

 

4

3

2

1

0

GND

CC

31

30

29

28

 

 

I/O

I/O

I/O

I/O

I/O

V

I/O

I/O

I/O

I/O

 

 

6

5

4

3

2

1

44

43 42

41

40

 

I/O5

7

 

 

 

 

 

 

 

 

 

39

I/O27

 

 

 

 

 

 

 

 

 

 

I/O6

8

 

 

 

 

 

 

 

 

 

38

I/O26

I/O7

9

 

 

 

 

 

 

 

 

 

37

I/O25

I0

10

 

 

 

 

 

 

 

 

 

36

I/O24

I1

11

 

 

 

 

 

 

 

 

 

35

CLK1/I5

GND

12

 

 

 

 

 

 

 

 

 

34

GND

CLK0/I2

13

 

 

 

 

 

 

 

 

 

33

I4

I/O8

14

 

 

 

 

 

 

 

 

 

32

I3

I/O9

15

 

 

 

 

 

 

 

 

 

31

I/O23

I/O10

16

 

 

 

 

 

 

 

 

 

30

I/O22

I/O11

17

 

20

21 22

23

24

25

26

 

29

I/O21

 

18 19

27 28

 

 

12

13

14

15

CC

GND

16

17

18

19

20

 

 

I/O

I/O

I/O

I/O

V

I/O

I/O

I/O

I/O

I/O

 

14127I-2

Note:

Pin-compatible with MACH111, MACH210, MACH211, and MACH215.

PIN DESIGNATIONS

CLK/I =

Clock or Input

GND =

Ground

I

=

Input

I/O

=

Input/Output

VCC

=

Supply Voltage

MACH110-12/15/20

3

AMD

ORDERING INFORMATION

Commercial Products

AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:

MACH 110 -12 J C

FAMILY TYPE

MACH = Macro Array CMOS High-Speed

DEVICE NUMBER

110 = 32 Macrocells, 44 Pins

SPEED

OPTIONAL PROCESSING

Blank = Standard Processing

OPERATING CONDITIONS

C = Commercial (0°C to +70°C)

PACKAGE TYPE

-12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD

Valid Combinations

MACH110-12

MACH110-15 JC

MACH110-20

J= 44-Pin Plastic Leaded Chip Carrier (PL 044)

Valid Combinations

The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

4

MACH110-12/15/20 (Com'l)

AMD

ORDERING INFORMATION

Industrial Products

AMD programmable logic products for Industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:

 

 

 

 

 

 

MACH 110 -14 J

I

FAMILY TYPE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OPTIONAL PROCESSING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MACH = Macro Array CMOS High-Speed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Blank = Standard Processing

DEVICE NUMBER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OPERATING CONDITIONS

110

=

32 Macrocells, 44 Pins

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I = Industrial (–40 °C to +85°C)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPEED

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PACKAGE TYPE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-14

=

14 ns tPD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

J = 44-Pin Plastic Leaded Chip

-18

=

18 ns tPD

 

 

 

 

 

 

 

Carrier (PL 044)

-24

=

24 ns tPD

 

 

 

 

 

 

 

 

Valid Combinations

Valid Combinations

MACH110-14

 

The Valid Combinations table lists configurations

 

planned to be supported in volume for this device.

 

 

MACH110-18

JI

Consult the local AMD sales office to confirm availability

 

 

of specific valid combinations and to check on newly

MACH110-24

 

 

released combinations.

 

 

 

MACH110-14/18/25 (Ind)

5

AMD

FUNCTIONAL DESCRIPTION

 

Table 1. Logic Allocation

The MACH110 consists of two PAL blocks connected by

 

 

 

 

Available

 

 

a switch matrix. There are 32 I/O pins and 6 dedicated

 

 

 

 

 

Output Macrocell

 

Clusters

 

 

input pins feeding the switch matrix. These signals are

 

 

 

 

 

 

 

 

 

 

M0

 

C0, C1

 

 

distributed to the two PAL blocks for efficient design

 

 

 

implementation. There are two clock pins that can also

 

M1

 

C0, C1, C2

 

 

be used as dedicated inputs.

 

M2

 

C1, C2, C3

 

 

 

 

 

 

 

 

 

 

 

 

M3

 

C2, C3, C4

 

 

The PAL Blocks

 

 

 

 

 

 

M4

 

C3, C4, C5

 

 

Each PAL block in the MACH110 (Figure 1) contains a

 

M5

 

C4, C5, C6

 

 

64-product-term logic array, a logic allocator, 16 macro-

 

M6

 

C5, C6, C7

 

 

cells and 16 I/O cells. The switch matrix feeds each PAL

 

 

 

 

 

 

M7

 

C6, C7

 

 

block with 22 inputs. This makes the PAL block look

 

 

 

 

 

 

 

M8

 

C8, C9

 

 

effectively like an independent “PAL22V16”.

 

 

 

 

 

 

 

 

 

 

M9

 

C8, C9, C10

 

 

 

 

 

 

 

There are four additional output enable product terms in

 

 

 

 

 

 

M10

 

C9, C10, C11

 

 

each PAL block. For purposes of output enable, the 16

 

M11

 

C10, C11, C12

 

 

I/O cells are divided into 2 banks of 8 macrocells. Each

 

 

 

 

 

 

 

M12

 

C11, C12, C13

 

 

bank is allocated two of the output enable product terms.

 

 

 

 

 

 

 

 

 

 

M13

 

C12, C13, C14

 

 

 

 

 

 

 

An asynchronous reset product term and an asynchro-

 

 

 

 

 

 

M14

 

C13, C14, C15

 

 

nous preset product term are provided for flip-flop

 

M15

 

C14, C15

 

 

initialization. All flip-flops within the PAL block are

 

 

 

 

 

 

 

 

 

 

 

 

initialized together.

The Macrocell

 

 

 

 

 

 

 

 

The Switch Matrix

The MACH110 macrocells can be configured as either

registered or combinatorial, with programmable polar-

The MACH110 switch matrix is fed by the inputs and

ity. The macrocell provides internal feedback whether

feedback signals from the PAL blocks. Each PAL block

configured as registered or combinatorial. The flip-flops

provides

16 internal feedback signals and 16 I/O

can be configured as D-type or T-type, allowing for

feedback signals. The switch matrix distributes these

product-term optimization.

 

 

 

signals back to the PAL blocks in an efficient manner

 

 

 

The flip-flops can individually select one of two clock

that also provides for high performance. The design

software automatically configures the switch matrix

pins, which are also available as data inputs. The regis-

when fitting a design into the device.

ters are clocked on the LOW-to-HIGH transition of the

 

 

clock signal. The flip-flops can also be asynchronously

The Product-Term Array

initialized with the common asynchronous reset and

preset product terms.

 

 

 

The MACH110 product-term array consists of 64

 

 

 

 

 

 

 

 

 

product

terms for logic use, and 6 special-purpose

The I/O Cell

 

 

 

product terms. Four of the special-purpose product

 

 

 

The I/O cell in the MACH110 consists of a three-state

terms provide programmable output enable, one

provides asynchronous reset, and one provides a

output buffer. The three-state buffer can be configured

synchronous preset. Two of the output enable product

in one of three ways: always enabled, always disabled,

terms are used for the first eight I/O cells; the other two

or controlled by a product term. If product term control is

control the last eight macrocells.

chosen, one of two product terms may be used to

 

 

provide the control. The two product terms that are

The Logic Allocator

available are common to eight I/O cells. Within each

PAL block, two product terms are available for selection

The logic allocator in the MACH110 takes the 64 logic

by the first eight three-state outputs; two other product

product terms and allocates them to the 16 macrocells

terms are available for selection by the last eight

as needed. Each macrocell can be driven by up to

three-state outputs.

 

 

 

12 product terms. The design software automatically

These choices make it possible to use the macrocell as

configures the logic allocator when fitting the design into

the device.

an output, an input, a bidirectional pin, or a three-state

Table 1 illustrates which product term clusters are

output for use in driving a bus.

 

 

 

 

 

 

 

 

 

available to each macrocell within a PAL block. Refer to

 

 

 

 

 

 

Figure 1 for cluster and macrocell numbers.

 

 

 

 

 

 

 

 

 

 

 

 

 

6

MACH110-12/15/20

 

 

 

AMD MACH110-24JI, MACH110-20JC, MACH110-18JI, MACH110-15JC, MACH110-14JI Datasheet

AMD

0

4

8

12

16

20

24

28

32

36

40

43

Output Enable

Output Enable

Asynchronous Reset

Asynchronous Preset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M0

Output

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M2

Output

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cell

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

C0

 

M4

Output

Cell

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

C1

 

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C2

 

 

 

 

I/O

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

Cell

 

 

 

 

 

 

 

 

 

 

 

 

M5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

C3

 

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C4

 

 

 

 

I/O

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

Cell

 

 

 

 

 

 

 

 

 

 

 

 

M6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Allocator

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

C5

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

I/O

I/O

Switch

 

 

 

 

 

 

 

 

 

 

6

 

 

 

Macro

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

M7

Output

 

 

Matrix

 

 

 

 

 

 

 

 

 

 

C7

Logic

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C8

 

 

Output

I/O

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M8

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

C9

 

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C10

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

Cell

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M9

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

C11

 

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C12

 

 

 

 

I/O

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

Cell

 

 

 

 

 

 

 

 

 

 

 

C

 

 

M10

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C14

 

 

 

 

I/O

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

Cell

 

 

 

 

 

 

 

 

 

 

 

C15

 

M

 

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

63

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M12

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

Cell

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M13

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cell

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M14

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cell

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M15

Macro

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cell

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Enable

 

 

 

0

4

8

12

16

20

24

28

32

36

40

43

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14127I-3

Figure 1. MACH110 PAL Block

MACH110-12/15/20

7

AMD

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . .

. . . –65 °C to +150°C

Ambient Temperature

–55 °C to +125°C

With Power Applied . . . . . . . . . . .

Supply Voltage with

 

 

Respect to Ground . . . . . . . . . . .

. . –0.5 V to +7.0 V

DC Input Voltage . . . . . . . . . . . .

–0.5 V to V CC + 0.5

V

DC Output or I/O

 

 

Pin Voltage . . . . . . . . . . . . . . . .

–0.5 V to V CC + 0.5

V

Static Discharge Voltage . . . . . .

. . . . . . . . . . 2001

V

Latchup Current

 

 

(TA = 0°C to 70°C) . . . . . . . . . . . .

. . . . . . . . . 200 mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA)

Operating in Free Air . . . . . . . . . . . . 0°C to +70°C

Supply Voltage (VCC)

with Respect to Ground . . . . . +4.75 V to +5.25 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified

Parameter

 

 

 

 

 

 

Symbol

Parameter Description

Test Conditions

Min

Typ

Max

Unit

 

 

 

 

 

 

 

VOH

Output HIGH Voltage

IOH = –3.2 mA, V CC = Min

2.4

 

 

V

 

 

VIN = VIH or VIL

 

 

 

 

VOL

Output LOW Voltage

IOL = 16 mA, VCC = Min

 

 

0.5

V

 

 

VIN = VIH or VIL

 

 

 

 

 

 

 

 

 

 

 

VIH

Input HIGH Voltage

Guaranteed Input Logical HIGH

2.0

 

 

V

 

 

Voltage for all Inputs (Note 1)

 

 

 

 

 

 

 

 

 

 

 

VIL

Input LOW Voltage

Guaranteed Input Logical LOW

 

 

0.8

V

 

 

Voltage for all Inputs (Note 1)

 

 

 

 

 

 

 

 

 

 

 

IIH

Input HIGH Current

VIN = 5.25 V, VCC = Max (Note 2)

 

 

10

μA

 

 

 

 

 

 

 

IIL

Input LOW Current

VIN = 0 V, VCC = Max (Note 2)

 

 

–10

μA

 

 

 

 

 

 

 

IOZH

Off-State Output Leakage

VOUT = 5.25 V, VCC = Max

 

 

10

μA

 

Current HIGH

VIN = VIH or VIL (Note 2)

 

 

 

 

 

 

 

 

 

 

 

IOZL

Off-State Output Leakage

VOUT = 0 V, VCC = Max

 

 

–10

μA

 

Current LOW

VIN = VIH or VIL (Note 2)

 

 

 

 

 

 

 

 

 

 

 

ISC

Output Short-Circuit Current

VOUT = 0.5 V, VCC = Max (Note 3)

–30

 

–160

mA

 

 

 

 

 

 

 

ICC

Supply Current (Typical)

VCC = 5 V, TA=25°C,

 

95

 

mA

 

 

f = 25 MHz (Note 4)

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.

2.I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).

3.Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

4.Measured with a 16-bit up/down counter program. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.

8

MACH110-12/15/20 (Com'l)

 

 

 

 

 

AMD

CAPACITANCE (Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

 

 

 

Symbol

Parameter Description

Test Conditions

Typ

 

Unit

 

 

 

 

 

 

 

CIN

Input Capacitance

VIN = 2.0 V

VCC = 5.0 V, TA = 25°C

6

 

pF

 

 

 

 

 

 

 

COUT

Output Capacitance

VOUT = 2.0 V

f = 1 MHz

8

 

pF

 

 

 

 

 

 

 

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)

Parameter

 

 

 

 

 

 

-12

-15

 

-20

 

 

Symbol

Parameter Description

 

 

Min

Max

Min

 

Max

Min

 

Max

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPD

Input, I/O, or Feedback to Combinatorial

 

 

12

 

 

15

 

 

20

ns

 

Output (Note 3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tS

Setup Time from Input, I/O, or Feedback

D-type

7

 

10

 

 

13

 

 

ns

to Clock

 

 

 

T-type

8

 

11

 

 

14

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tH

Hold Time

 

 

 

 

0

 

0

 

 

0

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCO

Clock to Output (Note 3)

 

 

 

8

 

 

10

 

 

12

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWL

Clock Width

 

 

 

LOW

6

 

6

 

 

8

 

 

ns

tWH

 

 

 

 

 

HIGH

6

 

6

 

 

8

 

 

ns

 

 

 

External Feedback

 

1/(tS + tCO)

D-type

66.7

 

50

 

 

40

 

 

MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Maximum

 

T-type

62.5

 

47.6

 

 

38.5

 

 

MHz

 

 

 

 

 

 

 

 

 

 

fMAX

 

 

 

 

D-type

76.9

 

66.6

 

 

47.6

 

 

MHz

Frequency

 

Internal Feedback (fCNT)

 

 

 

 

 

 

(Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

T-type

71.4

 

55.5

 

 

43.5

 

 

MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

No Feedback

 

1/(tWL + tWH)

 

83.3

 

83.3

 

 

62.5

 

 

MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAR

Asynchronous Reset to Registered Output

 

 

16

 

 

20

 

 

25

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

tARW

Asynchronous Reset Width (Note 1)

 

 

12

 

15

 

 

20

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

tARR

Asynchronous Reset Recovery Time (Note 1)

 

8

 

10

 

 

15

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

tAP

Asynchronous Preset to Registered Output

 

 

16

 

 

20

 

 

25

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

tAPW

Asynchronous Preset Width (Note 1)

 

12

 

15

 

 

20

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

tAPR

Asynchronous Preset Recovery Time (Note 1)

 

8

 

10

 

 

15

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

tEA

Input, I/O, or Feedback to Output Enable (Note 3)

 

 

12

 

 

15

 

 

20

ns

 

 

 

 

 

 

 

 

 

 

 

 

tER

Input, I/O, or Feedback to Output Disable (Note 3)

 

 

12

 

 

15

 

 

20

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.

2.See Switching Test Circuit, for test conditions.

3.Parameters measured with 16 outputs switching.

MACH110-12/15/20 (Com'l)

9

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