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AMD Geode™ LX Processors
Data Book
February 2009
Publication ID: 33234H
AMD Geode™ LX Processors Data Book
© 2009 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice.
Contacts
www.amd.com
Trademarks
AMD, the AMD Arrow logo, AMD Athlon, Geode, GeodeLink, 3DNow!, and combinations thereof, are trademarks of Advanced Micro Devices, Inc.
Linux is a registered trademark of Linus Torvalds.
WinBench is a registered trademark of Ziff Davis, Inc.
Windows is a registered trademark of Microsoft Corporation in the United States and/or other jurisdictions.
Pentium is a registered trademark and MMX is a trademark of Intel Corporation in the United States and/or other jurisdictions.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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AMD Geode™ LX Processors Data Book |
Contents |
33234H |
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Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 GeodeLink™ Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 GeodeLink™ Interface Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 GeodeLink™ Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 Graphics Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6 Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7 Video Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.8 Video Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.9 GeodeLink™ PCI Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.10 Security Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.0 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Bootstrap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.0 GeodeLink™ Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1 MSR Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2 GLIU Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.0 CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1 Core Processor Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.2 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3 Application Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.4 System Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.5 CPU Core Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
AMD Geode™ LX Processors Data Book |
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33234H |
Contents |
6.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.1 |
GeodeLink™ Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
210 |
6.2 |
GeodeLink™ Memory Controller Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
219 |
6.3 |
Graphics Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
237 |
6.4 |
Graphics Processor Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
254 |
6.5 |
Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
278 |
6.6 |
Display Controller Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
300 |
6.7 |
Video Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
388 |
6.8 |
Video Processor Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
412 |
6.9 |
Video Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
462 |
6.10 |
Video Input Port Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
482 |
6.11 |
Security Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
510 |
6.12 |
Security Block Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
513 |
6.13 |
GeodeLink™ Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
533 |
6.14 |
GeodeLink™ Control Processor Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
539 |
6.15 |
GeodeLink™ PCI Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
566 |
6.16 |
GeodeLink™ PCI Bridge Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
572 |
7.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
7.1 Electrical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
7.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
7.3 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
7.4 DC Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
7.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
7.6 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
8.0 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
8.1 General Instruction Set Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 8.2 CPUID Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 8.3 Processor Core Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 8.4 MMX™, FPU, and AMD 3DNow!™ Technology Instructions Sets . . . . . . . . . . . . . . . . . . . . . . 658
9.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
9.1 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Appendix A Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
A.1 Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
A.2 Data Book Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
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AMD Geode™ LX Processors Data Book |
List of Figures |
33234H |
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List of Figures
Figure 1-1. |
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 11 |
Figure 3-1. |
Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 21 |
Figure 3-2. |
BGU481 Ball Assignment Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 25 |
Figure 4-1. |
GeodeLink™ Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 46 |
Figure 6-1. |
Integrated Functions Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
209 |
Figure 6-2. |
GLMC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
210 |
Figure 6-3. |
HOI Addressing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
211 |
Figure 6-4. |
HOI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
211 |
Figure 6-5. |
LOI Addressing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
212 |
Figure 6-6. |
LOI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
212 |
Figure 6-7. |
Request Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
215 |
Figure 6-8. |
DDR Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
216 |
Figure 6-9. |
DDR Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
217 |
Figure 6-10. |
Graphics Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
237 |
Figure 6-11. |
14-Bit Repeated Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
244 |
Figure 6-12. |
Display Controller High-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
278 |
Figure 6-13. |
GUI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
279 |
Figure 6-14. |
VGA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
280 |
Figure 6-15. |
VGA Frame Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
288 |
Figure 6-16. |
Graphics Controller High-level Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
289 |
Figure 6-17. |
Write Mode Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
290 |
Figure 6-18. |
Read Mode Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
291 |
Figure 6-19. |
Color Compare Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
292 |
Figure 6-20. |
Graphics Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
293 |
Figure 6-21. |
Flicker Filter and Line Buffer Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
295 |
Figure 6-22. |
Interlaced Timing Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
298 |
Figure 6-23. |
Video Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
389 |
Figure 6-24. |
Video Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
390 |
Figure 6-25. |
Downscaler Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
392 |
Figure 6-26. |
Linear Interpolation Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
393 |
Figure 6-27. |
Mixer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
395 |
Figure 6-28. |
Color Key and Alpha-Blending Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
396 |
Figure 6-29. |
VOP Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
398 |
Figure 6-30. |
525-Line NTSC Video Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
399 |
Figure 6-31. |
HBLANK and VBLANK for Lines 20-262, 283-524 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
399 |
Figure 6-32. |
HBLANK and VBLANK for Lines 263, 525 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
400 |
Figure 6-33. |
HBLANK and VBLANK for Lines 1-18, 264-281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
400 |
Figure 6-34. |
HBLANK and VBLANK for Lines 19, 282 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
400 |
Figure 6-35. |
BT.656 8/16 Bit Line Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
403 |
Figure 6-36. |
Flat Panel Display Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
405 |
Figure 6-37. |
Dithered 8x8 Pixel Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
408 |
Figure 6-38. |
N-Bit Dithering Pattern Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
409 |
Figure 6-39. |
VIP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
463 |
Figure 6-40. |
BT.656, 8/16-Bit Line Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
467 |
Figure 6-41. |
525 line, 60 Hz Digital Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
468 |
AMD Geode™ LX Processors Data Book |
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33234H |
List of Figures |
Figure 6-42. |
Ancillary Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 469 |
Figure 6-43. |
Message Passing Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 470 |
Figure 6-44. |
Data Streaming Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 470 |
Figure 6-45. |
BT.601 Mode Default Field Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 471 |
Figure 6-46. |
BT.601 Mode Programmable Field Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 472 |
Figure 6-47. |
BT.601 Mode Horizontal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 472 |
Figure 6-48. |
BT.601 Mode Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 473 |
Figure 6-49. |
YUV 4:2:2 to YUV 4:2:0 Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 474 |
Figure 6-50. |
Dual Buffer for Message Passing and Data Streaming Modes . . . . . . . . . . . . . . . |
. . . . . . . 476 |
Figure 6-51. |
Example VIP YUV 4:2:2 SAV/EAV Packets Stored in System Memory in a Linear Buffer . 477 |
|
Figure 6-52. |
Example VIP YUV 4:2:0 Planar Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 478 |
Figure 6-53. |
Example VIP 8/16and 10-bit Ancillary Packets Stored in System Memory . . . . . |
. . . . . . . 479 |
Figure 6-54. |
Security Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 510 |
Figure 6-55. |
GLCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 533 |
Figure 6-56. |
Processor Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 536 |
Figure 6-57. |
GIO Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 537 |
Figure 6-58. |
GLPCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 566 |
Figure 6-59. |
Atomic MSR Accesses Across the PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 568 |
Figure 6-60. |
Simple Round-Robin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 570 |
Figure 6-61. |
Weighted Round-Robin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 570 |
Figure 7-1. |
VMEMLX Power Split . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 600 |
Figure 7-2. |
Drive Level and Measurement Points for Switching Characteristics . . . . . . . . . . . |
. . . . . . . 607 |
Figure 7-3. |
Drive Level and Measurement Points for Switching Characteristics . . . . . . . . . . . |
. . . . . . . 608 |
Figure 7-4. |
Power Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 609 |
Figure 7-5. |
Drive Level and Measurement Points for Switching Characteristics . . . . . . . . . . . |
. . . . . . . 609 |
Figure 7-6. |
Drive Level and Measurement Points for Switching Characteristics . . . . . . . . . . . |
. . . . . . . 610 |
Figure 7-7. |
Drive Level and Measurement Points for Switching Characteristics . . . . . . . . . . . |
. . . . . . . 611 |
Figure 7-8. |
DDR Write Timing Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 615 |
Figure 7-9. |
DDR Read Timing Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 616 |
Figure 9-1. |
BGU481 Top/Side View/Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 675 |
Figure 9-2. |
BGU481 Bottom View/Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 676 |
Figure A-1. |
AMD Geode™ LX Processors OPN Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 677 |
6 |
AMD Geode™ LX Processors Data Book |
List of Tables |
33234H |
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|
List of Tables
Table 2-1. |
Graphics Processor Feature Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 17 |
Table 3-1. |
Video Signal Definitions Per Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 22 |
Table 3-2. |
Buffer Type Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 23 |
Table 3-3. |
Bootstrap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 24 |
Table 3-4. |
Ball Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 24 |
Table 3-5. |
Ball Assignments - Sorted by Ball Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 26 |
Table 3-6. |
Ball Assignments - Sorted Alphabetically by Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . |
. 30 |
Table 3-7. |
Signal Behavior During and After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 43 |
Table 4-1. |
MSR Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 45 |
Table 4-2. |
MSR Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 47 |
Table 4-3. |
GLIU Memory Descriptor Address Hit and Routing Description . . . . . . . . . . . . . . . . . . . . . |
. 48 |
Table 4-4. |
GLIU I/O Descriptor Address Hit and Routing Description . . . . . . . . . . . . . . . . . . . . . . . . . |
. 49 |
Table 4-5. |
GeodeLink™ Device Standard MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 50 |
Table 4-6. |
GLIU Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 50 |
Table 4-7. |
GLIU Statistic and Comparator MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 51 |
Table 4-8. |
GLIU P2D Descriptor MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 53 |
Table 4-9. |
GLIU Reserved MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 53 |
Table 4-10. |
GLIU IOD Descriptor MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 54 |
Table 5-1. |
Initialized Core Register Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 89 |
Table 5-2. |
Application Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 91 |
Table 5-3. |
Segment Register Selection Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 92 |
Table 5-4. |
EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 93 |
Table 5-5. |
System Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 94 |
Table 5-6. |
Control Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 95 |
Table 5-7. |
CR4 Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 96 |
Table 5-8. |
CR3 Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 96 |
Table 5-9. |
CR2 Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 96 |
Table 5-10. |
CR0 Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 96 |
Table 5-11. |
Effects of Various Combinations of EM, TS, and MP Bits . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 98 |
Table 5-12. |
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 99 |
Table 5-13. |
CPU Core Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 99 |
Table 5-14. |
XC_HIST_MSR Exception Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
126 |
Table 5-15. |
Region Properties Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
170 |
Table 5-16. |
Read Operations vs. Region Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
170 |
Table 5-17. |
Write Operations vs. Region Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
170 |
Table 6-1. |
LOI - 2 DIMMs, Same Size, 1 DIMM Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
213 |
Table 6-2. |
LOI - 2 DIMMs, Same Size, 2 DIMM Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
213 |
Table 6-3. |
Non-Auto LOI - 1 or 2 DIMMs, Different Sizes, 1 DIMM Bank . . . . . . . . . . . . . . . . . . . . . . . |
214 |
Table 6-4. |
Non-Auto LOI - 1 or 2 DIMMs, Different Sizes, 2 DIMM Banks . . . . . . . . . . . . . . . . . . . . . . |
214 |
Table 6-5. |
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
219 |
Table 6-6. |
GLMC Specific MSR Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
219 |
Table 6-7. |
Graphics Processor Feature Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
238 |
Table 6-8. |
BLT Command Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
239 |
Table 6-9. |
Vector Command Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
240 |
Table 6-10. |
LUT (Lookup Table) Load Command Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
240 |
AMD Geode™ LX Processors Data Book |
7 |
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33234H |
List of Tables |
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|
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Table 6-11. |
Data Only Command Buffer Structure . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . 240 |
Table 6-12. |
Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 241 |
Table 6-13. |
Pixel Ordering for 4-Bit Pixels . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 243 |
Table 6-14. |
Example Vector Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 244 |
Table 6-15. |
Example Vector Length . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 244 |
Table 6-16. |
Example of Monochrome Pattern . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 247 |
Table 6-17. |
Example of 8-Bit Color Pattern (3:3:2 Format) . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 248 |
Table 6-18. |
Example of 16-Bit Color Pattern (5:6:5 Format) . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 248 |
Table 6-19. |
32-bpp 8:8:8:8 Color Data Format . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 249 |
Table 6-20. |
16-bpp Color Data Format . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 249 |
Table 6-21. |
8-bpp 3:3:2 Color Data Format . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 249 |
Table 6-22. |
Monochrome Data Format . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 249 |
Table 6-23. |
Example of Byte-Packed Monochrome Source Data . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 250 |
Table 6-24. |
Example of Unpacked Monochrome Source Data . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 250 |
Table 6-25. |
GP_RASTER_MODE Bit Patterns . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 251 |
Table 6-26. |
Common Raster Operations . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 251 |
Table 6-27. |
Alpha Blending Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 252 |
Table 6-28. |
Standard GeodeLink™ Device MSRs Summary . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 254 |
Table 6-29. |
Graphics Processor Configuration Register Summary . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 254 |
Table 6-30. |
PAT_COLOR Usage for Color Patterns . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 264 |
Table 6-31. |
PAT_DATA Usage for Color Patterns . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 265 |
Table 6-32. |
Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 281 |
Table 6-33. |
Cursor Display Encodings . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 283 |
Table 6-34. |
Icon Display Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 283 |
Table 6-35. |
Cursor/Color Key/Alpha Interaction . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 284 |
Table 6-36. |
Video Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 286 |
Table 6-37. |
YUV 4:2:0 Video Data Ordering . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 287 |
Table 6-38. |
YUV 4:2:2 Video Data Ordering . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 287 |
Table 6-39. |
VGA Text Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 288 |
Table 6-40. |
Text Mode Attribute Byte Format . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 288 |
Table 6-41. |
VGA Graphics Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 288 |
Table 6-42. |
Programming Image Sizes . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 297 |
Table 6-43. |
Vertical Timing in Number of Lines . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 298 |
Table 6-44. |
Timing Register Settings for Interlaced Modes . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 299 |
Table 6-45. |
Standard GeodeLink™ Device MSRs Summary . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 300 |
Table 6-46. |
DC Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 300 |
Table 6-47. |
DC Configuration Control Register Summary . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 300 |
Table 6-48. |
VGA Block Configuration Register Summary . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 303 |
Table 6-49. |
VGA Block Standard Register Summary . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 303 |
Table 6-50. |
VGA Block Extended Register Summary . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 304 |
Table 6-51. |
VGA Sequencer Registers Summary . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 358 |
Table 6-52. |
Font Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 360 |
Table 6-53. |
CRTC Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 361 |
Table 6-54. |
CRTC Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 362 |
Table 6-55. |
CRTC Memory Addressing Modes . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 371 |
Table 6-56. |
Graphics Controller Registers Summary . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 373 |
Table 6-57. |
Attribute Controller Registers Summary . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 378 |
Table 6-58. |
Video DAC Registers Summary . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 382 |
Table 6-59. |
Extended Registers Summary . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 384 |
Table 6-60. |
Truth Table for Alpha-Blending . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 397 |
Table 6-61. |
VOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 401 |
Table 6-62. |
SAV/EAV Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 402 |
Table 6-63. |
Protection Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 402 |
Table 6-64. |
SAV VIP Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 404 |
Table 6-65. |
VOP Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . 404 |
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8 |
|
AMD Geode™ LX Processors Data Book - |
List of Tables |
33234H |
|
Table 6-66. |
Panel Output Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . 406 |
Table 6-67. |
Register Settings for Dither Enable/Disable Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 410 |
Table 6-68. |
Display RGB Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 411 |
Table 6-69. |
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 412 |
Table 6-70. |
Video Processor Module Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 412 |
Table 6-71. |
Video Processor Module Configuration Control Registers Summary . . . . . . . . . . . . . . . . |
. 412 |
Table 6-72. |
VIP Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 462 |
Table 6-73. |
SAV/EAV Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 466 |
Table 6-74. |
VIP Data Types / Memory Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 475 |
Table 6-75. |
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 482 |
Table 6-76. |
VIP Configuration/Control Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 482 |
Table 6-77. |
EEPROM Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 512 |
Table 6-78. |
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 513 |
Table 6-79. |
Security Block Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 513 |
Table 6-80. |
Security Block Configuration/Control Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . |
. 513 |
Table 6-81. |
TAP Control Instructions (25-Bit IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 534 |
Table 6-82. |
TAP Instruction Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 534 |
Table 6-83. |
GIO_PCI Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 537 |
Table 6-84. |
CIS Signaling Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 538 |
Table 6-85. |
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 539 |
Table 6-86. |
GLCP Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 539 |
Table 6-87. |
Bootstrap Bit Settings and Reset State of GLCP_SYS_RSTPLL (PW1 and IRQ13 = 0) |
. . 556 |
Table 6-88. |
Bootstrap Bit Settings and Reset State of GLCP_SYS_RSTPLL (PW1 and IRQ13 vary) . |
. 557 |
Table 6-89. |
Format for Accessing the Internal PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . |
. 569 |
Table 6-90. |
PCI Device to AD Bus Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 570 |
Table 6-91. |
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 572 |
Table 6-92. |
GLPCI Specific Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 572 |
Table 6-93. |
Region Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 586 |
Table 7-1. |
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 597 |
Table 7-2. |
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 598 |
Table 7-3. |
AMD Geode LX 900@1.5W Processor DC Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 600 |
Table 7-4. |
AMD Geode LX 800@0.9W Processor DC Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 601 |
Table 7-5. |
AMD Geode LX 700@0.8W Processor DC Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 602 |
Table 7-6. |
AMD Geode LX 600@0.7W Processor DC Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 603 |
Table 7-7. |
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 604 |
Table 7-8. |
System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 608 |
Table 7-9. |
PCI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 609 |
Table 7-10. |
VIP Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 610 |
Table 7-11. |
Flat Panel Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 611 |
Table 7-12. |
CRT Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 612 |
Table 7-13. |
CRT Display Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 612 |
Table 7-14. |
CRT Display Analog (DAC) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 613 |
Table 7-15. |
Memory (DDR) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 614 |
Table 7-16. |
JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 617 |
Table 8-1. |
General Instruction Set Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 619 |
Table 8-2. |
Instruction Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 620 |
Table 8-3. |
Instruction Prefix Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 620 |
Table 8-4. |
w Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 621 |
Table 8-5. |
d Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 621 |
Table 8-6. |
s Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 621 |
Table 8-7. |
eee Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 622 |
Table 8-8. |
mod r/m Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 622 |
Table 8-9. |
General Registers Selected by mod r/m Fields and w Field . . . . . . . . . . . . . . . . . . . . . . . |
. 623 |
Table 8-10. |
reg Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 624 |
Table 8-11. |
sreg2 Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 624 |
AMD Geode™ LX Processors Data Book |
9 |
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|
33234H |
List of Tables |
Table 8-12. |
sreg3 Field (FS and GS Segment Register Selection) . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 624 |
Table 8-13. |
ss Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 625 |
Table 8-14. |
index Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 625 |
Table 8-15. |
mod base Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 626 |
Table 8-16. |
CPUID Instruction with EAX = 00000000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 627 |
Table 8-17. |
CPUID Instruction with EAX = 00000001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 627 |
Table 8-18. |
CPUID Instruction Codes with EAX = 00000000 . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 628 |
Table 8-19. |
CPUID Instruction with EAX = 80000000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 629 |
Table 8-20. |
CPUID Instruction with EAX = 80000001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 629 |
Table 8-21. |
CPUID Instruction Codes with EAX = 80000001h . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 630 |
Table 8-22. |
CPUID Instruction with EAX = 80000002h, 80000003h, or 80000004h . . . . . . . . . |
. . . . . . 631 |
Table 8-23. |
CPUID Instruction with EAX = 80000005h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 632 |
Table 8-24. |
CPUID Instruction with EAX = 80000006h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 632 |
Table 8-25. |
Processor Core Instruction Set Table Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 633 |
Table 8-26. |
Processor Core Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 634 |
Table 8-27. |
MMX™, FPU, and AMD 3DNow!™ Instruction Set Table Legend . . . . . . . . . . . . . |
. . . . . . 658 |
Table 8-28. |
MMX™ Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 660 |
Table 8-29. |
FPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 667 |
Table 8-30. |
AMD 3DNow!™ Technology Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 671 |
Table A-1. |
Valid OPN Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 678 |
Table A-2. |
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 679 |
Table A-3. |
Edits to Current Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 679 |
10 |
AMD Geode™ LX Processors Data Book - |
Overview |
33234H |
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Overview1
1.1General Description
AMD Geode™ LX processors are integrated x86 processors specifically designed to power embedded devices for entertainment, education, and business. Serving the needs of consumers and business professionals alike, it’s an excellent solution for embedded applications, such as thin clients, interactive set-top boxes, single board computers, and mobile computing devices.
Available with a core voltage of 1.2V, 1.25V, or 1.4V it offers extremely low typical power consumption leading to longer battery life and enabling small form-factor, fanless designs.
While the processor core provides maximum compatibility with the vast amount of Internet content available, the intelligent integration of several other functions, including graphics and video datapaths, offers a true system-level multimedia solution.
For implementation details and suggestions for this device, see the supporting documentation (i.e., application notes, schematics, etc.) on the AMD Embedded Developer Support Web site (http://wwwd.amd.com/dev, NDA required).
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System PLL |
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MMU |
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FPU |
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BLT Engine |
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Load/Store |
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LUT |
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DOTREF |
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CPU PLL |
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ROP Unit |
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DOTCLK PLL |
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TLB |
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Bus Controller |
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128 KB L2 cache |
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GeodeLink™ |
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Memory |
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Controller (GLMC) |
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GeodeLink™ Interface Unit 0 |
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64-bit DDR SDRAM |
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DDR |
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Display Controller (DC) |
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Compression Buffer |
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GeodeLink™ |
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Control |
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GeodeLink™ Interface Unit 1 |
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Palette RAM |
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Test/Reset |
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Power Mgmnt |
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Graphics Filter/Scaling |
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Diagnostic |
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HW VGA |
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AMD Geode™ |
Companion I/F |
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RGB |
YUV |
Companion |
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Video Processor (VP) |
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Device |
Security Block |
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Video Input |
GeodeLink™ |
TFT |
Video Scalar |
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128-bit AES |
PCI Bridge |
Controller/ |
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Port (VIP) |
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(CBC/ECB) |
(GLPCI) |
Video |
Video Mixer |
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True |
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Output |
Alpha Blender |
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Port (VOP) |
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Random Number |
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Generator |
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3x8-Bit DAC |
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EEPROM on package |
VIP |
PCI |
TFT/VOP |
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(optional) |
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CRT |
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Figure 1-1. Internal Block Diagram
AMD Geode™ LX Processors Data Book |
11 |
33234H |
Overview |
1.2Features
General Features
■Functional blocks include:
—CPU Core
—GeodeLink™ Control Processor
—GeodeLink Interface Units
—GeodeLink Memory Controller
—Graphics Processor
—Display Controller
—Video Processor
– TFT Controller/Video Output Port
—Video Input Port
—GeodeLink PCI Bridge
—Security Block
■0.13 micron process
■Packaging:
—481-Terminal BGU (Ball Grid Array Cavity Up) with internal heatspreader
■Single packaging option supports all features
■Industrial temperature range available for the LX 800@0.9W processor*
CPU Processor Features
■x86/x87-compatible CPU core
■Performance:
—Processor frequency: up to 600 MHz
—Dhrystone 2.1 MIPs: 150 to 450
—Fully pipelined FPU
■Split I/D cache/TLB (Translation Look-aside Buffer):
—64 KB I-cache/64 KB D-cache
—128 KB L2 cache configurable as I-cache, D-cache, or both
■Efficient prefetch and branch prediction
■Integrated FPU that supports the MMX™ and AMD 3DNow!™ instruction sets
■Fully pipelined single precision FPU hardware with microcode support for higher precisions
GeodeLink™ Control Processor
■JTAG interface:
—ATPG, Full Scan, BIST on all arrays
—1149.1 Boundary Scan compliant
■ICE (in-circuit emulator) interface
■Reset and clock control
■Designed for improved software debug methods and performance analysis
■Power Management:
—LX 900@1.5W processor* (Unterminated): Total Dissipated Power (TDP) 5.1W,
2.6W typical @ 600 MHz max power
—LX 800@0.9W processor* (Unterminated): Total Dissipated Power (TDP) 3.6W,
1.8W typical @ 500 MHz max power
—LX 700@0.8W processor* (Unterminated): Total Dissipated Power (TDP) 3.1W,
1.3W typical @ 433 MHz max power
—LX 600@0.7W processor* (Unterminated): Total Dissipated Power (TDP) 2.8W,
1.2W typical @ 366 MHz max power
—GeodeLink active hardware power management
—Hardware support for standard ACPI software power management
—I/O companion SUSP/SUSPA power controls
—Lower power I/O
—Wakeup on SMI/INTR
■Works in conjunction with the AMD Geode™ CS5536 (USB 2.0) or CS5535 (USB 1.1) companion device
GeodeLink™ Architecture
■High bandwidth packetized uni-directional bus for internal peripherals
■Standardized protocol to allow variants of products to be developed by adding or removing modules
■GeodeLink Control Processor (GLCP) for diagnostics and scan control
■Dual GeodeLink Interface Units (GLIUs) for device interconnect
GeodeLink™ Memory Controller
■Integrated memory controller for low latency to CPU and on-chip peripherals
■64-bit wide DDR SDRAM bus operating frequency:
— 200 MHz, 400 MT/S
■Supports unbuffered DDR DIMMS using up to 2 GB DRAM technology
■Supports up to 2 DIMMS (16 devices max)
2D Graphics Processor
■High performance 2D graphics controller
■Alpha BLT
■Windows® GDI GUI acceleration:
— Hardware support for all Microsoft RDP codes
■Command buffer interface for asynchronous BLTs
■Second pattern channel support
■Hardware screen rotation
*The AMD Geode LX 900@1.5W processor operates at 600 MHz, the AMD Geode LX 800@0.9W processor operates at 500 MHz, the AMD Geode LX 700@0.8W processor operates at 433 MHz and the AMD Geode LX 600@.07W processor operates at 366 MHz. Model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodelxbenchmark.
12 |
AMD Geode™ LX Processors Data Book |
Overview |
33234H |
Display Controller
■Hardware frame buffer compression improves Unified Memory Architecture (UMA) memory efficiency
■CRT resolutions supported:
—Supports up to 1920x1440x32 bpp at 85 Hz
—Supports up to 1600x1200x32 bpp at 100 Hz
■Supports up to 1600x1200x32 bpp at 60 Hz for TFT
■Standard Definition (SD) resolution for Video Output Port (VOP):
—720x482 at 59.94 Hz interlaced for NTSC
—768x576 at 50 Hz interlaced for PAL
■High Definition (HD) resolution for Video Output Port (VOP):
—Up to 1920x1080 at 30 Hz interlaced (1080i HD) (74.25 MHz)
—Up to 1280x720 at 60 Hz progressive (720p HD) (74.25 MHz)
■Supports down to 7.652 MHz Dot Clock (320x240 QVGA)
■Hardware VGA
■Hardware supported 48x64 32-bit cursor with alpha blending
Video Processor
■Supports video scaling, mixing and VOP
■Hardware video up/down scalar
■Graphics/video alpha blending and color key muxing
■Digital VOP (SD and HD) or TFT outputs
■Legacy RGB mode
■VOP supports SD and HD 480p, 480i, 720p, and 1080i
GeodeLink™ PCI Bridge
■PCI 2.2 compliant
■3.3V signaling and 3.3V I/Os
■33 to 66 MHz operation
■32-bit interface
■Supports virtual PCI headers for GeodeLink devices
Video Input Port (VIP)
■VESA 1.1 and 2.0 compliant, 8 or 16-bit
■Video Blanking Interval (VBI) support
■8 or 16-bit 80 MHz SD or HD capable
Security Block
■Serial EEPROM interface for 2K bit unique ID and AES (Advanced Encryption Standard) hidden key storage (EEPROM optional inside package)
■Electronic Code Book (ECB) or Cipher Block Chaining (CBC)128-bit AES hardware support
■True random number generator (TRNG)
■VESA 1.1, 2.0 and BT.601 24-bit (out only), BT.656 compliant
Integrated Analog CRT DAC, System Clock PLLs and
Dot Clock PLL
■Integrated Dot Clock PLL with up to 350 MHz clock
■Integrated 3x8-bit DAC with up to 350 MHz sampling
■Integrated x86 core PLL
■Memory PLL
AMD Geode™ LX Processors Data Book |
13 |
33234H |
Overview |
|
|
14 |
AMD Geode™ LX Processors Data Book |
Architecture Overview |
33234H |
|
|
Architecture Overview2
The CPU Core provides maximum compatibility with the vast amount of Internet content available while the intelligent integration of several other functions, including graphics, makes the AMD Geode™ LX processor a true systemlevel multimedia solution.
The AMD Geode LX processor can be divided into major functional blocks (as shown in Figure 1-1 on page 11):
•CPU Core
•GeodeLink™ Control Processor
•GeodeLink Interface Units
•GeodeLink Memory Controller
•Graphics Processor
•Display Controller
•Video Processor
— TFT Controller/Video Output Port
•Video Input Port
•GeodeLink PCI Bridge
•Security Block
2.1CPU Core
The x86 core consists of an Integer Unit, cache memory subsystem, and an x87 compatible FPU (Floating Point Unit). The Integer Unit contains the instruction pipeline and associated logic. The memory subsystem contains the instruction and data caches, translation look-aside buffers (TLBs), and an interface to the GeodeLink Interface Units (GLIUs).
The instruction set supported by the core is a combination of Intel Pentium® processor, AMD Athlon™ processor, and AMD Geode LX processor specific instructions. Specifically, it supports the Pentium, Pentium Pro, AMD 3DNow!™ technology and MMX™ instructions for the AMD Athlon processor. It supports a subset of the specialized AMD Geode LX processor instructions including special SMM instructions. The CPU Core does not support the entire Katmai New Instruction (KNI) set as implemented in the Pentium 3. It does support the MMX instructions for the AMD Athlon processor, which are a subset of the Pentium 3 KNI instructions.
2.1.1Integer Unit
The Integer Unit consists of a single issue 8-stage pipeline and all the necessary support hardware to keep the pipeline running efficiently.
The instruction pipeline in the integer unit consists of eight stages:
1)Instruction Prefetch - Raw instruction data is fetched from the instruction memory cache.
2)Instruction Pre-decode - Prefix bytes are extracted from raw instruction data. This decode looks-ahead to the next instruction and the bubble can be squashed if the pipeline stalls down stream.
3)Instruction Decode - Performs full decode of instruction data. Indicates instruction length back to the Prefetch Unit, allowing the Prefetch Unit to shift the appropriate number of bytes to the beginning of the next instruction.
4)Instruction Queue - FIFO containing decoded x86 instructions. Allows Instruction Decode to proceed even if the pipeline is stalled downstream. Register reads for data operand address calculations are performed during this stage.
5)Address Calculation #1 - Computes linear address of operand data (if required) and issues request to the Data Memory Cache. Microcode can take over the pipeline and inject a micro-box here if multi-box instructions require additional data operands.
6)Address Calculation #2 - Operand data (if required) is returned and set up to the Execution stage with no bubbles if there was a data cache hit. Segment limit checking is performed on the data operand address. The µROM is read for setup to Execution Unit.
7)Execution Unit - Register and/or data memory fetch fed through the Arithmetic Logic Unit (ALU) for arithmetic or logical operations. µROM always fires for the first instruction box down the pipeline. Microcode can take over the pipeline and insert additional boxes here if the instruction requires multiple Execution Unit stages to complete.
8)Writeback - Results of the Execution Unit stages are written to the register file or to data memory.
AMD Geode™ LX Processors Data Book |
15 |
33234H |
Architecture Overview |
2.1.2Memory Management Unit
The memory management unit (MMU) translates the linear address supplied by the integer unit into a physical address to be used by the cache unit and the internal bus interface unit. Memory management procedures are x86-compati- ble, adhering to standard paging mechanisms.
The MMU also contains a load/store unit that is responsible for scheduling cache and external memory accesses. The load/store unit incorporates two performance-enhancing features:
•Load-store reordering gives memory reads required by the integer unit a priority over writes to external memory.
•Memory-read bypassing eliminates unnecessary memory reads by using valid data from the execution unit.
2.1.3Cache and TLB Subsystem
The cache and TLB subsystem of the CPU Core supplies the integer pipeline with instructions, data, and translated addresses (when necessary). To support the efficient delivery of instructions, the cache and TLB subsystem has a single clock access 64 KB 16-way set associative instruction cache and a 16-entry fully associative TLB. The TLB performs necessary address translations when in protected mode. For data, there is a 64 KB 16-way set associative writeback cache, and a 16-entry fully associative TLB. When there is a miss to the instruction or data TLBs, there is a second level unified (instruction and data) 64-entry 2- way set associative TLB that takes an additional clock to access. When there is a miss to the instruction or data caches or the TLB, the access must go to the GeodeLink Memory Controller (GLMC) for processing. Having both an instruction and a data cache and their associated TLBs improves overall efficiency of the integer unit by enabling simultaneous access to both caches.
The L1 caches are supported by a 128 KB unified L2 victim cache. The L2 cache can be configured to hold data, instructions, or both. The L2 cache is 4-way set associative.
2.1.4Bus Controller Unit
The bus controller unit provides a bridge from the processor to the GLIUs. When external memory access is required, due to a cache miss, the physical address is passed to the bus controller unit, that translates the cycle to a GeodeLink cycle.
2.1.5Floating Point Unit
The Floating Point Unit (FPU) is a pipelined arithmetic unit that performs floating point operations as per the IEEE 754 standard. The instruction sets supported are x87, MMX, and AMD 3DNow! technology. The FPU is a pipelined machine with dynamic scheduling of instructions to minimize stalls due to data dependencies. It performs out of order execution and register renaming. It is designed to support an instruction issue rate of one per clock from the
integer core. The datapath is optimized for single precision arithmetic. Extended precision instructions are handled in microcode and require multiple passes through the pipeline. There is an execution pipeline and a load/store pipeline. This allows load/store operations to execute in parallel with arithmetic instructions.
2.2GeodeLink™ Control Processor
The GeodeLink Control Processor (GLCP) is responsible for reset control, macro clock management, and debug support provided in the Geode LX processor. It contains the JTAG interface and the scan chain control logic. It supports chip reset, including initial PLL control and programming and runtime power management macro clock control.
The JTAG support includes a TAP Controller that is IEEE 1149.1 compliant. CPU control can be obtained through the JTAG interface into the TAP Controller, and all internal registers, including CPU Core registers, can be accessed. In-circuit emulation (ICE) capabilities are supported through this JTAG and TAP Controller interface.
The GLCP also includes the companion device interface. The companion device has several unique signals connected to this module that support Geode LX processor reset, interrupts, and system power management.
2.3GeodeLink™ Interface Units
Together, the two GeodeLink Interface Units (GLIU0 and GLIU1) make up the internal bus derived from the GeodeLink architecture. GLIU0 connects five high bandwidth modules together with a seventh link to GLIU1 that connects to the five low bandwidth modules.
2.4GeodeLink™ Memory Controller
The GeodeLink Memory Controller (GLMC) is the source for all memory needs in a typical Geode LX processor system. The GLMC supports a memory data bus width of 64 bits and supports 200 MHz, 400 MT/S for DDR (Double Data Rate).
The modules that need memory are the CPU Core, Graphics Processor, Display Controller, Video Input Port, and Security Block. Because the GLMC supports memory needs for both the CPU Core and the display subsystem, the GLMC is classically called a UMA (Unified Memory Architecture) subsystem. PCI accesses to main memory are also supported.
Up to four banks, with eight devices maximum in each bank of SDRAM, are supported with up to 512 MB in each bank. Four banks means that one or two DIMM or SODIMM modules can be used in a AMD Geode LX processor system. Some memory configurations have additional restrictions on maximum device quantity.
16 |
AMD Geode™ LX Processors Data Book |
Architecture Overview |
33234H |
2.5Graphics Processor
The Graphics Processor is based on the graphics processor used in the AMD Geode GX processor with several features added to enhance performance and functionality. Like its predecessor, the AMD Geode LX processor’s Graphics Processor is a BitBLT/vector engine that supports pattern generation, source expansion, pattern/source transparency, 256 ternary raster operations, alpha blenders to support alpha-BLTs, incorporated BLT FIFOs, a GeodeLink interface and the ability to throttle BLTs according to video timing. Features added to the Graphics Processor include:
• Command buffer interface
•Hardware accelerated rotation BLTs
•Color depth conversion
•Paletized color
•Full 8x8 color pattern buffer
•Channel 3 - third DMA channel
•Monochrome inversion
Table 2-1 presents a comparison between the Graphics Processor features of the AMD Geode GX and LX processors.
Table 2-1. Graphics Processor Feature Comparison
Feature |
AMD Geode™ GX Processor |
AMD Geode™ LX Processor |
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|
Color Depth |
8, 16, 32 bpp |
8, 16, 32 bpp (A) RGB 4 and 8-bit indexed |
|
|
|
ROPs |
256 (src, dest, pattern) |
256 (2-src, dest and pattern) |
|
|
|
BLT Buffers |
FIFOs in Graphics Processor |
FIFOs in Graphics Processor |
|
|
|
BLT Splitting |
Managed by hardware |
Managed by hardware |
|
|
|
Video Synchronized BLT/Vector |
Throttle by VBLANK |
Throttle by VBLANK |
|
|
|
Bresenham Lines |
Yes |
Yes |
|
|
|
Patterned (stippled) Lines |
No |
Yes |
|
|
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Screen to Screen BLT |
Yes |
Yes |
|
|
|
Screen to Screen BLT with |
Yes |
Yes |
mono expansion |
|
|
|
|
|
Memory to Screen BLT |
Yes (through CPU writes) |
Yes (throttled rep movs writes) |
|
|
|
Accelerated Text |
No |
No |
|
|
|
Pattern Size (Mono) |
8x8 pixels |
8x8 pixels |
|
|
|
Pattern Size (Color) |
8x1 (32 pixels) |
8x8 pixels |
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|
8x2 (16 pixels) |
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8x4 (8 pixels) |
|
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Monochrome Pattern |
Yes |
Yes (with inversion) |
|
|
|
Dithered Pattern (4 color) |
No |
No |
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|
|
Color Pattern |
8, 16, 32 bpp |
8, 16, 32 bpp |
|
|
|
Transparent Pattern |
Monochrome |
Monochrome |
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Solid Fill |
Yes |
Yes |
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Pattern Fill |
Yes |
Yes |
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Transparent Source |
Monochrome |
Monochrome |
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Color Key Source Transparency |
Y with mask |
Y with mask |
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Variable Source Stride |
Yes |
Yes |
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Variable Destination Stride |
Yes |
Yes |
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Destination Write Bursting |
Yes |
Yes |
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Selectable BLT Direction |
Vertical and Horizontal |
Vertical and Horizontal |
|
|
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Alpha BLT |
Yes (constant α or α/pix) |
Yes (constant α, α/pix, or sep. α channel) |
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VGA Support |
Decodes VGA Register |
Decodes VGA Register |
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Pipeline Depth |
2 ops |
Unlimited |
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Accelerated Rotation BLT |
No |
8, 16, 32 bpp |
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|
|
Color Depth Conversion |
No |
5:6:5, 1:5:5:5, 4:4:4:4, 8:8:8:8 |
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|
|
AMD Geode™ LX Processors Data Book |
17 |
|
33234H |
Architecture Overview |
2.6Display Controller
The Display Controller performs the following functions:
1)Retrieves graphics, video, and cursor data.
2)Serializes the streams.
3)Performs any necessary color lookups and output formatting.
4)Interfaces to the Video Processor for driving the display device(s).
The Display Controller consists of a memory retrieval system for rasterized graphics data, a VGA, and a back-end filter. The AMD Geode LX processor’s Display Controller corresponds to the Display Controller function found in the AMD Geode GX processor with additional hardware for graphics filter functions. The VGA provides full hardware compatibility with the VGA graphics standard. The rasterized graphics and the VGA share a single display FIFO and display refresh memory interface to the GeodeLink Memory Controller (GLMC). The VGA uses 8 bpp and syncs, that are expanded to 24 bpp via the color lookup table, and passes the information to the graphics filter for scaling and interlaced display support. The stream is then passed to the Video Processor, which is used for video overlay. The Video Processor forwards this information to the DAC (Dig- ital-to-Analog Converter), that generates the analog red, green, and blue signals, and buffers the sync signals that are then sent to the display. The Video Processor output can also be rendered as YUV data, and can be output on the Video Output Port (VOP).
2.7Video Processor
The Video Processor mixes the graphics and video streams, and outputs either digital RGB data to the internal DACs or the flat panel interface, or digital YUV data via the VOP interface.
The Video Processor delivers high-resolution and truecolor graphics. It can also overlay or blend a scaled truecolor video image on the graphic background.
The Video Processor interfaces with the CPU Core via a GLIU master/slave interface. The Video Processor is a slave only, as it has no memory requirements.
2.7.1CRT Interface
The internal high performance DACs support CRT resolutions up to:
—1920x1440x32 bpp at 85 Hz
—1600x1200x32 bpp at 100 Hz
2.7.2TFT Controller
The TFT Controller converts the digital RGB output of a Video Mixer block to the digital output suitable for driving a TFT flat panel LCD.
The flat panel connects to the RGB port of the Video Mixer. It interfaces directly to industry standard 18-bit or 24-bit active matrix thin film transistor (TFT). The digital RGB or video data that is supplied by the video logic is converted into a suitable format to drive a wide range of panels with variable bits. The LCD interface includes dithering logic to increase the apparent number of colors displayed for use on panels with less than 6 bits per color. The LCD interface also supports automatic power sequencing of panel power supplies.
It supports panels up to a 24-bit interface and up to 1600x1200 resolution.
The TFT Controller interfaces with the CPU Core via a GLIU master/slave interface. The TFT Controller is both a GLIU master and slave.
2.7.3Video Output Port
The VOP receives YUV 4:4:4 encoded data from the Video Processor and formats the data into a video stream that is BT.656 compliant. Output from the VOP goes to either a VIP or a TV encoder. The VOP is BT.656/601 compliant since its output may go directly (or indirectly) to a display.
2.8Video Input Port
The Video Input Port (VIP) receives 8- or 16-bit video or ancillary data, 8-bit message data, or 8-bit raw video and passes it to data buffers located in system memory. The VIP is a DMA engine. The primary operational mode is as a compliant VESA 2.0 slave. The VESA 2.0 specification defines the protocol for receiving video, VBI, and ancillary data. The addition of the message passing and data streaming modes provides additional flexibility in receiving non-VESA 2.0 compliant data streams. Input data is packed into QWORDS, buffered into a FIFO, and sent to system memory over the GLIU. The VIP masters the internal GLIU and transfers the data from the FIFO to system memory. The maximum input data rate (8- or 16-bits) is 150 MHz.
2.9GeodeLink™ PCI Bridge
The GeodeLink PCI Bridge (GLPCI) contains all the necessary logic to support an external PCI interface. The PCI interface is PCI v2.2 specification compliant. The logic includes the PCI and GLIU interface control, read and write FIFOs, and a PCI arbiter.
18 |
AMD Geode™ LX Processors Data Book |
Architecture Overview |
33234H |
2.10Security Block
The AMD Geode LX processor has an on-chip AES 128-bit crypto acceleration block capable of 44 Mbps throughput on either encryption or decryption at a processor speed of 500 MHz. The AES block runs asynchronously to the processor core and is DMA based. The AES block supports both EBC and CBC modes and has an interface for accessing the optional EEPROM memory for storing unique IDs and/or security keys. The AES and EEPROM sections have separate control registers but share a single
set of interrupt registers. The AES module has two key sources: one hidden 128-bit key stored in the “on-package” EEPROM, and a write only 128-bit key (reads as all zeros). The hidden key is loaded automatically by the hardware after reset and is not visible to the processor. The EEPROM can be locked. The initialization vector for the CBC mode can be generated by the True Random Number Generator (TRNG). The TRNG is addressable separately and generates a 32-bit random number.
AMD Geode™ LX Processors Data Book |
19 |
33234H |
Architecture Overview |
|
|
20 |
AMD Geode™ LX Processors Data Book |
Signal Definitions |
33234H |
|
|
Signal Definitions3
This chapter defines the signals and describes the external interface of the AMD Geode™ LX processor. Figure 3-1 shows the pins organized by their functional groupings. Where signals are multiplexed, the default signal name is listed first and is separated by a plus sign (+). Multi-function pins are described in Table 3-1 on page 22.
|
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AD[31:0] |
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SYSREF |
AMD Geode™ |
CBE[3:0]# |
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FRAME# |
|
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DOTREF |
LX Processor |
IRDY# |
PCI |
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System |
INTA# |
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TRDY# |
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Interface |
|||
Interface |
IRQ13 (STRAP) |
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STOP# |
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CIS |
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DEVSEL# |
Signals |
|
Signals |
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|
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SUSPA# (STRAP) |
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PAR |
|
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PW[1:0] (STRAP) |
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REQ[2:0]# |
|
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TDP |
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(STRAP) GNT[2:0]# |
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TDN |
|
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RESET# |
|
|
SDCLK[5:0]P |
|
(Total of 32) VCORE |
Power/Ground |
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|
(Total of 30) VIO |
||
|
SDCLK[5:0]N |
|
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Interface |
|
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(Total of 33) VMEM |
|||
|
MVREF |
|
Signals |
||
|
CKE[1:0] |
|
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(Total of 128) VSS |
|
|
CS[3:0]# |
|
DOTCLK+VOPCLK |
|
|
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RAS[1:0]# |
|
|
||
Memory |
CAS[1:0]# |
|
DRGB[31:26]+VID[15:10] |
|
|
WE[1:0]# |
|
DRGB[25:24]+VID[9:8]+ |
|
||
Interface |
BA[1:0] |
|
MSGSTART+MSGSTOP |
|
|
Signals |
MA[13:0] |
|
|
DRGB[23:16] |
Display (TFT Option) |
|
TLA[1:0] |
|
|
||
|
|
DRBG[15:8]+VOP[15:8] |
|||
|
DQS[7:0] |
|
Interface |
||
|
|
DRGB[7:0]+VOP[7:0] |
|||
|
DQM[7:0] |
|
HSYNC+VOP_HSYNC |
Signals |
|
|
DQ[63:0] |
|
VSYNC+VOP_VSYNC |
|
|
|
|
|
VDDEN+VIP_HSYNC |
|
|
|
VAVDD, CAVDD, MAVDD |
LDEMOD+VIP_VSYNC |
|
||
|
DISPEN+VOP_BLANK |
|
|||
PLL |
VAVSS, CAVSS, MAVSS |
|
|||
|
|
|
|||
Interface |
CLPF |
|
|
|
|
Signals |
MLPF |
|
|
VIPCLK |
VIP |
VLPF |
|
|
|||
|
|
|
|
VID[7:0] |
Interface |
|
|
|
|
VIPSYNC |
Signals |
|
|
|
|
|
|
Internal Test |
TCLK |
|
|
DVREF |
|
|
|
DRSET |
|
||
and |
TMS |
|
(Total of 4) DAVDD |
|
|
TDI |
|
Display (CRT Option) |
|||
Measurement |
TDO |
|
(Total of 4) DAVSS |
||
Interface |
TDBGI |
|
|
RED |
Interface |
Signals |
TDBGO |
|
|
GREEN |
Signals |
|
|
|
|
BLUE |
|
|
|
|
|
HSYNC |
|
|
|
|
|
VSYNC |
|
Figure 3-1. Signal Groups
AMD Geode™ LX Processors Data Book |
21 |
33234H Signal Definitions
Table 3-1. Video Signal Definitions Per Mode
|
|
|
RGB w/16-bit |
ARGB (Note 1) |
TFT w/16-bit VIP |
8- or 16-bit VOP |
Signal Name |
CRT w/16-bit VIP |
VIP |
w/8-bit VIP |
(not 601) |
w/16-bit VIP |
|
|
|
|
|
|
|
|
RED |
|
RED |
|
|
|
|
|
|
|
|
|
|
|
GREEN |
|
GREEN |
|
|
|
|
|
|
|
|
|
|
|
BLUE |
|
BLUE |
|
|
|
|
|
|
|
|
|
|
|
DRGB[31:24] (I/O) |
VID[15:8] (I) |
VID[15:8] (I) |
Alpha |
VID[15:8] (I) |
VID[15:8] (I) |
|
|
|
|
|
|
|
|
DRGB[23:16] (O) |
R[7:0] |
R[7:0] |
R[7:0] |
R[7:0] (Note 2) |
Driven low |
|
|
|
|
|
|
|
|
DRGB[15:8] (O) |
G[7:0] |
G[7:0] |
G[7:0] |
G[7:0] (Note 2) |
VOP[15:8] (O) |
|
|
|
|
|
|
|
|
DRGB[7:0] (O) |
B[7:0] |
B[7:0] |
B[7:0] |
B[7:0] (Note 2) |
VOP[7:0] (O) |
|
|
|
|
|
|
|
|
DOTCLK (O) |
DOTCLK (O) |
DOTCLK (O) |
DOTCLK (O) |
DOTCLK (O) |
VOPCLK (O) |
|
|
|
|
|
|
|
|
HSYNC (O) |
HSYNC (O) |
HSYNC (O) |
HSYNC (O) |
VOP_HSYNC (O) |
VOP_HSYNC (O) |
|
|
|
|
|
|
|
|
VSYNC (O) |
VSYNC (O) |
VSYNC (O) |
VSYNC (O) |
VSYNC (O) |
VOP_VSYNC (O) |
|
|
|
|
|
|
|
|
DISPEN (O) |
|
|
|
DISPEN (O) |
VOP_BLANK (O) |
|
|
|
|
|
|
|
|
VDDEN (I/O) |
VIP_HSYNC (I) |
VIP_HSYNC (I) |
VIP_HSYNC (I) |
VDDEN (O) |
VIP_HSYNC (I) |
|
|
|
|
|
|
|
|
LDEMOD (I/O) |
VIP_VSYNC (I) |
VIP_VSYNC (I) |
VIP_VSYNC (I) |
LDEMOD (O) |
VIP_VSYNC (I) |
|
|
|
|
|
|
|
|
VID[7:0] (I) |
VID[7:0] |
VID[7:0] |
VID[7:0] |
VID[7:0] |
VID[7:0] |
|
|
|
|
|
|
|
|
VIPCLK (I) |
VIPCLK |
VIPCLK |
VIPCLK |
VIPCLK |
VIPCLK |
|
|
|
|
|
|
|
|
VIPSYNC (I) |
VIPSYNC |
VIPSYNC |
VIPSYNC |
VIPSYNC |
VIPSYNC |
|
|
|
|
|
|
|
|
Note 1. |
Alpha RED/GREEN/BLUE: Useful for off-chip graphics digital interfaces. |
|
|
|||
Note 2. |
Pin usage depends on TFT mode. See Section 6.7.7 "Flat Panel Display Controller" on page 405 for details. |
|||||
22 |
AMD Geode™ LX Processors Data Book |
Signal Definitions |
33234H |
3.1Buffer Types
The Ball Assignment tables starting on page 26 include a column labeled “Buffer Type”. The details of each buffer type listed in this column are given in Table 3-2. The column headings in Table 3-2 are identified as follows:
TS: Indicates whether the buffer may be put into the TRISTATE mode. Note some pins that have buffer types that allow TRI-STATE may never actually enter the TRI-STATE mode in practice, since they may be inputs or provide other signals that are always driven. To determine if a particular signal can be put in the TRI-STATE mode, consult the individual signal descriptions in Section 3.4 "Signal Descriptions" on page 33.
OD: Indicates if the buffer is open-drain, or not. Open-drain outputs may be wire ORed together and require a discrete pull-up resistor to operate properly.
5VT: Indicates if the buffer is 5-volt tolerant, or not. If it is 5- volt tolerant, then 5 volt TTL signals may be safely applied to this pin.
PU/PD: Indicates if an internal, programmable pull-up or pull-down resistor may be present.
Current High/Low (mA): This column gives the current source/sink capacities when the voltage at the pin is high, and low. The high and low values are separated by a “/” and values given are in milli-amps (mA).
Rise/Fall @ Load: This column indicates the rise and fall times for the different buffer types at the load capacitance indicated. These measurements are given in two ways: rise/fall time between the 20%-80% voltage levels, or, the rate of change the buffer is capable of, in volts-per-nano- second (V/ns).
Note the presence of “Wire” type buffer in this table. Signals identified as a wire-type are not driven by a buffer, hence no rise/fall time or other measurements are given; these are marked “NA” in Table 3-2. The wire-type connection indicates a direct connection to internal circuits such as power, ground, and analog signals.
Table 3-2. Buffer Type Characteristics
|
|
|
|
|
Current |
|
|
|
|
|
|
High/Low |
|
Name |
TS |
OD |
5VT |
PU/PD |
(mA) |
Rise/Fall @ Load |
|
|
|
|
|
|
|
24/Q3 |
X |
|
|
X |
24/24 |
3 ns @ 50 pF |
|
|
|
|
|
|
|
24/Q5 |
X |
|
|
X |
24/24 |
5 ns @ 50 pF |
|
|
|
|
|
|
|
24/Q7 |
X |
|
|
X |
24/24 |
7 ns @ 50 pF |
|
|
|
|
|
|
|
5V |
X |
|
X |
|
16/16 |
1.25V/ns @ 40 pF |
|
|
|
|
|
|
|
PCI |
X |
|
|
|
0.5/1.5 |
1-4V/ns @ 10 pF |
|
|
|
|
|
|
|
DDRCLK |
|
|
|
|
10/10 |
8.5V/ns @ 15 pF |
|
|
|
|
|
|
|
DDR |
|
|
|
|
|
2.4V/ns @ 50 pF |
|
|
|
|
|
|
|
Wire |
NA |
NA |
|
NA |
NA |
NA |
|
|
|
|
|
|
|
AMD Geode™ LX Processors Data Book |
23 |
33234H |
Signal Definitions |
3.2Bootstrap Options
The bootstrap options shown in Table 3-3 are supported in the AMD Geode LX processor for configuring the system.
|
Table 3-3. Bootstrap Options |
|
Pins |
|
Description |
|
|
|
IRQ13 |
|
0: Normal boot operation, TAP reset |
|
|
active during PCI reset |
|
|
1: Debug stall of CPU after CPU |
|
|
reset, TAP reset active until VIO valid |
PW1 |
|
0: PCI (SYSREF) is 33 MHz |
|
|
1: PCI (SYSREF) is 66 MHz |
|
|
|
PW0, |
|
Select CPU and GeodeLink system |
SUSPA#, |
|
MHz options including a PLL bypass |
GNT[2:0]# |
|
option. Refer to Table 6-87 on page |
|
|
556 for programming. |
|
|
|
3.3Ball Assignments
The tables in this chapter use several common abbreviations. Table 3-4 lists the mnemonics and their meanings.
Table 3-4. Ball Type Definitions
Mnemonic |
Definition |
|
|
A |
Analog |
|
|
I |
Input ball |
|
|
I/O |
Bidirectional ball |
|
|
CAVSS |
Core PLL Ground ball: Analog |
|
|
CAVDD |
Core PLL Power ball: Analog |
DAVSS |
DAC PLL Ground ball: Analog |
|
|
DAVDD |
DAC PLL Power ball: Analog |
MAVSS |
GLIU PLL Ground ball: Analog |
|
|
MAVDD |
GLIU PLL Power ball: Analog |
O |
Output ball |
|
|
VAVSS |
Video PLL Ground ball: Analog |
VAVDD |
Video PLL Power ball: Analog |
|
|
VCORE |
Power ball: 1.2V (Nominal) |
VIO |
I/O Power ball: 3.3V (Nominal) |
VMEM |
Power ball: 2.5V |
VSS |
Ground ball |
# |
The “#” symbol at the end of a signal |
|
name indicates that the active, or |
|
asserted state, occurs when the sig- |
|
nal is at a low voltage level. When “#” |
|
is not present after the signal name, |
|
the signal is asserted when at a high |
|
voltage level. |
|
|
24 |
AMD Geode™ LX Processors Data Book |
Signal Definitions |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
33234H |
|
|
|
|
|
|
|
||||||
|
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
|
28 |
29 |
30 |
31 |
|
A |
VSS |
VMEM |
VSS |
DQ21 |
VSS |
DQM2 |
DQ22 |
VSS |
DQ28 |
DQS3 |
VSS |
DQ26 DQ31 |
VMEM |
DQ32 |
VSS |
DQ37 |
VMEM |
DQM4 |
DQ39 |
VSS |
DQ40 |
DQ41 |
VSS |
DQ42 |
DQ43 |
VSS |
|
WE1# |
VSS |
VMEM |
VSS |
A |
|
|
|
|
|||||||||||||||||||||||||||||||
B |
VMEM |
VSS |
VSS |
DQ17 |
VMEM |
DQ18 |
DQ23 |
VMEM |
DQ24 |
DQM3 |
VMEM |
DQ27 |
TLA1 |
VSS |
TLA0 |
DQ36 |
DQ33 |
VSS |
DQ34 |
DQ38 |
VMEM |
DQ35 |
DQS5 |
VMEM |
DQ46 |
DQ47 |
VMEM |
|
CS0# |
VSS |
VSS |
VMEM |
B |
|
|
|
|||||||||||||||||||||||||||||||
C |
VSS |
VSS |
VMEM |
VSS |
MA12 |
DQS2 |
VMEM |
DQ19 |
DQ29 |
DQ25 |
DQ30 |
VSS |
MA3 |
VMEM |
MA2 |
MA0 |
MA1 |
VMEM |
DQS4 |
BA1 |
VSS |
DQ44 |
DQ45 |
DQM5 |
VMEM RAS0# |
WE0# |
VSS |
VMEM |
VSS |
VSS |
C |
||
|
|
||||||||||||||||||||||||||||||||
D |
DQ20 |
DQ16 |
VSS |
VMEM |
MA11 |
MA9 |
VSS |
MA7 |
MA8 |
VSS |
MA5 |
MA6 |
MA4 |
VSS |
VCORE |
VSS |
VCORE |
VSS |
MA10 SDK5P SDK5N |
VSS |
SDK4P SDK4N |
VSS |
BA0 |
RAS1# VMEM |
VSS |
CS3# |
DQ48 |
D |
|||||
E |
VSS |
VMEM |
DQ11 |
CKE0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CAS0# CAS1# VMEM |
VSS |
E |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
||||||||
F |
DQ15 |
DQ14 |
DQ10 |
CKE1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS1# |
CS2# |
MA13 |
DQ49 |
F |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
||||||||
G |
DQ13 DQM1 |
VMEM |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
VMEM |
DQ52 |
DQ53 |
G |
|
|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
H |
VMEM |
VSS |
DQS1 SDK1N |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SDK3N DQM6 |
VSS |
VMEM |
H |
||
J |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
J |
||||||||
DQ9 |
DQ8 |
DQ12 SDK1P |
|
|
|
|
|
|
AMD Geode™ |
|
|
|
|
|
|
SDK3P DQS6 |
DQ55 |
DQ54 |
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||||||||||
K |
DQ7 |
DQ3 |
VMEM |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
VMEM |
DQ50 |
DQ51 |
K |
||||||||||||
L |
|
|
|
|
|
|
|
|
|
|
|
|
L |
||||||||||||||||||||
VMEM |
VSS |
DQ6 |
SDK0N |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||||
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SDK2N DQ60 |
VSS |
VMEM |
|||||||
M |
DQM0 |
DQS0 |
DQ2 |
SDK0P |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SDK2P DQ61 |
DQ57 |
DQ56 |
M |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
N |
DQ5 |
DQ1 |
VSS |
VMEM |
|
|
|
|
|
|
|
|
VCORE VCORE |
VSS |
VSS |
VSS |
VCORE VCORE |
|
|
|
|
|
|
|
|
|
VSS |
VMEM |
DQM7 DQS7 |
N |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
P |
MVREF DQ0 |
DQ4 |
VSS |
|
|
|
|
|
|
|
|
VCORE VCORE |
VSS |
VSS |
VSS |
VCORE VCORE |
|
|
|
|
|
|
|
|
|
VSS |
VMEM |
DQ62 |
VSS |
P |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
R |
VSS |
VSS |
VSS |
VSS |
|
|
|
|
|
|
|
|
VSS |
VSS |
VSS |
VSS |
VSS |
VSS |
VSS |
|
|
|
|
|
|
|
|
|
VCORE |
DQ63 |
DQ58 |
DQ59 |
R |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
T |
VCORE VCORE VCORE VCORE |
|
|
|
|
|
|
|
|
VSS |
VSS |
VSS |
VSS |
VSS |
VSS |
VSS |
|
|
|
|
|
|
|
|
|
VSS |
VSS |
VSS |
VSS |
T |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
U |
DAVDD BLUE DAVSS VCORE |
|
|
|
|
|
|
|
|
VSS |
VSS |
VSS |
VSS |
VSS |
VSS |
VSS |
|
|
|
|
|
|
|
|
|
VCORE |
VCORE |
VCORE VCORE |
U |
||||
V |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
V |
|||||||||||||||
DAVDD GREEN DAVSS DAVDD |
|
|
|
|
|
|
|
|
VCORE VCORE |
VSS |
VSS |
VSS |
VCORE VCORE |
|
|
|
|
|
|
|
|
|
VCORE |
MLPF MAVSS MAVDD |
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
W |
DVREF DAVSS |
RED |
DAVDD |
|
|
|
|
|
|
|
|
VCORE VCORE |
VSS |
VSS |
VSS |
VCORE VCORE |
|
|
|
|
|
|
|
|
|
VSS |
CLPF CAVSS CAVDD |
W |
|||||
Y |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Y |
|||||||||||||||
DRSET DAVSS |
VIO |
VSS |
|
|
|
|
|
|
LX Processor |
|
|
|
|
|
|
|
VCORE |
VSS RESET# SYREF |
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||||||
AA |
VAVDD |
VAVSS |
VLPF |
TMS |
|
|
|
|
|
|
|
|
|
|
|
|
|
s |
|
VSS |
VIO |
AA |
|||||||||||
|
|
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GNT0# REQ0# |
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AB |
DOTREF TDBGI TDI |
TDBGO |
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s |
s |
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AB |
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REQ2# IRQ13 GNT1# REQ1# |
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AC |
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VIO |
VSS |
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(Top View) |
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VSS |
VIO |
s |
s |
AC |
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TDO |
TCLK |
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GNT2# SUPA# |
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AD |
VIO |
VSS |
VSYNC LDEMOD |
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INTA# |
AD31 |
VSS |
VIO |
AD |
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AE |
DOTCLK VDEN HSYNC DISPEN |
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AD27 |
CIS |
AD29 |
AD30 |
AE |
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AF |
DRB17 DRB16 |
VIO |
VSS |
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VSS |
VIO |
AD26 |
AD28 |
AF |
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AG |
VIO |
VSS |
DRB18 DRB19 |
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AD25 |
AD24 |
VSS |
VIO |
AG |
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AH |
DRB20 DRB21 DRB22 |
VSS |
DRB11 |
VSS |
DRB0 |
DRB6 |
VSS |
DRB29 DRB24 |
VSS |
VID3 |
VSS |
VCORE |
VSS |
VCORE |
VSS |
AD1 |
VSS |
AD5 |
AD11 |
VSS |
AD14 |
IRDY# |
VSS |
CBE2# |
VSS |
AD23 |
AD22 |
CBE3# |
AH |
||||
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AJ |
DRB23 DRB8 |
VIO |
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VIO |
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VIO |
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VIO |
|
VIO |
|
VSS |
s |
VIO |
|
VIO |
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VIO |
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VIO |
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VIO |
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AJ |
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DRB12 DRB15 |
DRB3 |
DRB7 |
DRB28 DRB25 |
VID4 |
VID0 |
PW1 |
AD0 |
AD6 |
CBE0# |
AD15 STOP# |
PAR |
|
AD16 |
AD19 |
AD21 |
|
||||||||||||||||
AK |
VIO |
VSS |
DRB9 |
DRB14 |
VSS |
DRB1 |
DRB4 |
VSS |
DRB31 DRB26 |
VSS |
VID7 |
VID5 |
VSS |
VID1 |
VSS |
TDN |
VSS |
AD4 |
AD3 |
VSS |
AD8 |
AD10 |
VSS DEVSL# TRDY# |
VSS |
|
AD17 |
AD20 |
VSS |
VIO |
AK |
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AL |
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s |
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AL |
|
VSS |
VIO |
DRB10 DRB13 |
VIO |
DRB2 |
DRB5 |
VIO |
DRB30 DRB27 |
VIO |
VIPCLK VID6 VIPSYNC VID2 |
VSS |
TDP |
PW0 |
AD7 |
AD2 |
VIO |
AD9 |
AD12 |
VIO |
AD13 |
CBE1# |
VIO |
FRAME# AD18 |
VIO |
VSS |
|
|||||||
|
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
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28 |
29 |
30 |
31 |
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Note: |
Signal names have been abbreviated in this figure due to space constraints. |
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|||||||||||||||||||||
= GND Ball
= PWR Ball
S
= Strap Option Ball
= Multiplexed Ball
Figure 3-2. BGU481 Ball Assignment Diagram
AMD Geode™ LX Processors Data Book |
25 |
33234H |
Signal Definitions |
Table 3-5. Ball Assignments - Sorted by Ball Number
Ball |
Signal Name |
Type |
Buffer |
No. |
(Note 1) |
(PD) |
Type |
|
|
|
|
A1 |
VSS |
GND |
--- |
A2 |
VMEM |
PWR |
--- |
A3 |
VSS |
GND |
--- |
A4 |
DQ21 |
I/O |
DDR |
|
|
|
|
A5 |
VSS |
GND |
--- |
A6 |
DQM2 |
I/O |
DDR |
|
|
|
|
A7 |
DQ22 |
I/O |
DDR |
|
|
|
|
A8 |
VSS |
GND |
--- |
A9 |
DQ28 |
I/O |
DDR |
|
|
|
|
A10 |
DQS3 |
I/O |
DDR |
|
|
|
|
A11 |
VSS |
GND |
--- |
A12 |
DQ26 |
I/O |
DDR |
|
|
|
|
A13 |
DQ31 |
I/O |
DDR |
|
|
|
|
A14 |
VMEM |
PWR |
--- |
A15 |
DQ32 |
I/O |
DDR |
|
|
|
|
A16 |
VSS |
GND |
--- |
A17 |
DQ37 |
I/O |
DDR |
|
|
|
|
A18 |
VMEM |
PWR |
--- |
A19 |
DQM4 |
I/O |
DDR |
|
|
|
|
A20 |
DQ39 |
I/O |
DDR |
|
|
|
|
A21 |
VSS |
GND |
--- |
A22 |
DQ40 |
I/O |
DDR |
|
|
|
|
A23 |
DQ41 |
I/O |
DDR |
|
|
|
|
A24 |
VSS |
GND |
--- |
A25 |
DQ42 |
I/O |
DDR |
|
|
|
|
A26 |
DQ43 |
I/O |
DDR |
|
|
|
|
A27 |
VSS |
GND |
--- |
A28 |
WE1# |
I/O |
DDR |
|
|
|
|
A29 |
VSS |
GND |
--- |
A30 |
VMEM |
PWR |
--- |
A31 |
VSS |
GND |
--- |
B1 |
VMEM |
PWR |
--- |
B2 |
VSS |
GND |
--- |
B3 |
VSS |
GND |
--- |
B4 |
DQ17 |
I/O |
DDR |
|
|
|
|
B5 |
VMEM |
PWR |
--- |
B6 |
DQ18 |
I/O |
DDR |
|
|
|
|
B7 |
DQ23 |
I/O |
DDR |
|
|
|
|
B8 |
VMEM |
PWR |
--- |
B9 |
DQ24 |
I/O |
DDR |
|
|
|
|
B10 |
DQM3 |
I/O |
DDR |
|
|
|
|
B11 |
VMEM |
PWR |
--- |
B12 |
DQ27 |
I/O |
DDR |
|
|
|
|
B13 |
TLA1 |
I/O |
DDR |
|
|
|
|
B14 |
VSS |
GND |
--- |
B15 |
TLA0 |
I/O |
DDR |
|
|
|
|
B16 |
DQ36 |
I/O |
DDR |
|
|
|
|
B17 |
DQ33 |
I/O |
DDR |
|
|
|
|
B18 |
VSS |
GND |
--- |
Ball |
Signal Name |
Type |
Buffer |
No. |
(Note 1) |
(PD) |
Type |
|
|
|
|
B19 |
DQ34 |
I/O |
DDR |
|
|
|
|
B20 |
DQ38 |
I/O |
DDR |
|
|
|
|
B21 |
VMEM |
PWR |
--- |
B22 |
DQ35 |
I/O |
DDR |
|
|
|
|
B23 |
DQS5 |
I/O |
DDR |
|
|
|
|
B24 |
VMEM |
PWR |
--- |
B25 |
DQ46 |
I/O |
DDR |
|
|
|
|
B26 |
DQ47 |
I/O |
DDR |
|
|
|
|
B27 |
VMEM |
PWR |
--- |
B28 |
CS0# |
I/O |
DDR |
|
|
|
|
B29 |
VSS |
GND |
--- |
B30 |
VSS |
GND |
--- |
B31 |
VMEM |
PWR |
--- |
C1 |
VSS |
GND |
--- |
C2 |
VSS |
GND |
--- |
C3 |
VMEM |
PWR |
--- |
C4 |
VSS |
GND |
--- |
C5 |
MA12 |
I/O |
DDR |
|
|
|
|
C6 |
DQS2 |
I/O |
DDR |
|
|
|
|
C7 |
VMEM |
PWR |
--- |
C8 |
DQ19 |
I/O |
DDR |
|
|
|
|
C9 |
DQ29 |
I/O |
DDR |
|
|
|
|
C10 |
DQ25 |
I/O |
DDR |
|
|
|
|
C11 |
DQ30 |
I/O |
DDR |
|
|
|
|
C12 |
VSS |
GND |
--- |
C13 |
MA3 |
I/O |
DDR |
|
|
|
|
C14 |
VMEM |
PWR |
--- |
C15 |
MA2 |
I/O |
DDR |
|
|
|
|
C16 |
MA0 |
I/O |
DDR |
|
|
|
|
C17 |
MA1 |
I/O |
DDR |
|
|
|
|
C18 |
VMEM |
PWR |
--- |
C19 |
DQS4 |
I/O |
DDR |
|
|
|
|
C20 |
BA1 |
I/O |
DDR |
|
|
|
|
C21 |
VSS |
GND |
--- |
C22 |
DQ44 |
I/O |
DDR |
|
|
|
|
C23 |
DQ45 |
I/O |
DDR |
|
|
|
|
C24 |
DQM5 |
I/O |
DDR |
|
|
|
|
C25 |
VMEM |
PWR |
--- |
C26 |
RAS0# |
I/O |
DDR |
|
|
|
|
C27 |
WE0# |
I/O |
DDR |
|
|
|
|
C28 |
VSS |
GND |
--- |
C29 |
VMEM |
PWR |
--- |
C30 |
VSS |
GND |
--- |
C31 |
VSS |
GND |
--- |
D1 |
DQ20 |
I/O |
DDR |
|
|
|
|
D2 |
DQ16 |
I/O |
DDR |
|
|
|
|
D3 |
VSS |
GND |
--- |
D4 |
VMEM |
PWR |
--- |
D5 |
MA11 |
I/O |
DDR |
|
|
|
|
D6 |
MA9 |
I/O |
DDR |
|
|
|
|
Ball |
Signal Name |
Type |
Buffer |
No. |
(Note 1) |
(PD) |
Type |
|
|
|
|
D7 |
VSS |
GND |
--- |
D8 |
MA7 |
I/O |
DDR |
|
|
|
|
D9 |
MA8 |
I/O |
DDR |
|
|
|
|
D10 |
VSS |
GND |
--- |
D11 |
MA5 |
I/O |
DDR |
|
|
|
|
D12 |
MA6 |
I/O |
DDR |
|
|
|
|
D13 |
MA4 |
I/O |
DDR |
|
|
|
|
D14 |
VSS |
GND |
--- |
D15 |
VCORE |
PWR |
--- |
D16 |
VSS |
GND |
--- |
D17 |
VCORE |
PWR |
--- |
D18 |
VSS |
GND |
--- |
D19 |
MA10 |
I/O |
DDR |
|
|
|
|
D20 |
SDCLK5P |
O |
DDRCLK |
|
|
|
|
D21 |
SDCLK5N |
O |
DDRCLK |
|
|
|
|
D22 |
VSS |
GND |
--- |
D23 |
SDCLK4P |
O |
DDRCLK |
|
|
|
|
D24 |
SDCLK4N |
O |
DDRCLK |
|
|
|
|
D25 |
VSS |
GND |
--- |
D26 |
BA0 |
I/O |
DDR |
|
|
|
|
D27 |
RAS1# |
I/O |
DDR |
|
|
|
|
D28 |
VMEM |
PWR |
--- |
D29 |
VSS |
GND |
--- |
D30 |
CS3# |
I/O |
DDR |
|
|
|
|
D31 |
DQ48 |
I/O |
DDR |
|
|
|
|
E1 |
VSS |
GND |
--- |
E2 |
VMEM |
PWR |
--- |
E3 |
DQ11 |
I/O |
DDR |
|
|
|
|
E4 |
CKE0 |
I/O |
DDR |
|
|
|
|
E28 |
CAS0# |
I/O |
DDR |
|
|
|
|
E29 |
CAS1# |
I/O |
DDR |
|
|
|
|
E30 |
VMEM |
PWR |
--- |
E31 |
VSS |
GND |
--- |
F1 |
DQ15 |
I/O |
DDR |
|
|
|
|
F2 |
DQ14 |
I/O |
DDR |
|
|
|
|
F3 |
DQ10 |
I/O |
DDR |
|
|
|
|
F4 |
CKE1 |
I/O |
DDR |
|
|
|
|
F28 |
CS1# |
I/O |
DDR |
|
|
|
|
F29 |
CS2# |
I/O |
DDR |
|
|
|
|
F30 |
MA13 |
I/O |
DDR |
|
|
|
|
F31 |
DQ49 |
I/O |
DDR |
|
|
|
|
G1 |
DQ13 |
I/O |
DDR |
|
|
|
|
G2 |
DQM1 |
I/O |
DDR |
|
|
|
|
G3 |
VMEM |
PWR |
--- |
G4 |
VSS |
GND |
--- |
G28 |
VSS |
GND |
--- |
G29 |
VMEM |
PWR |
--- |
G30 |
DQ52 |
I/O |
DDR |
|
|
|
|
G31 |
DQ53 |
I/O |
DDR |
|
|
|
|
H1 |
VMEM |
PWR |
--- |
26 |
AMD Geode™ LX Processors Data Book |
Signal Definitions |
33234H |
Table 3-5. Ball Assignments - Sorted by Ball Number (Continued)
Ball |
Signal Name |
Type |
Buffer |
No. |
(Note 1) |
(PD) |
Type |
|
|
|
|
H2 |
VSS |
GND |
--- |
H3 |
DQS1 |
I/O |
DDR |
|
|
|
|
H4 |
SDCLK1N |
O |
DDRCLK |
|
|
|
|
H28 |
SDCLK3N |
O |
DDRCLK |
|
|
|
|
H29 |
DQM6 |
I/O |
DDR |
|
|
|
|
H30 |
VSS |
GND |
--- |
H31 |
VMEM |
PWR |
--- |
J1 |
DQ9 |
I/O |
DDR |
|
|
|
|
J2 |
DQ8 |
I/O |
DDR |
|
|
|
|
J3 |
DQ12 |
I/O |
DDR |
|
|
|
|
J4 |
SDCLK1P |
O |
DDRCLK |
|
|
|
|
J28 |
SDCLK3P |
O |
DDRCLK |
|
|
|
|
J29 |
DQS6 |
I/O |
DDR |
|
|
|
|
J30 |
DQ55 |
I/O |
DDR |
|
|
|
|
J31 |
DQ54 |
I/O |
DDR |
|
|
|
|
K1 |
DQ7 |
I/O |
DDR |
|
|
|
|
K2 |
DQ3 |
I/O |
DDR |
|
|
|
|
K3 |
VMEM |
PWR |
--- |
K4 |
VSS |
GND |
--- |
K28 |
VSS |
GND |
--- |
K29 |
VMEM |
PWR |
--- |
K30 |
DQ50 |
I/O |
DDR |
|
|
|
|
K31 |
DQ51 |
I/O |
DDR |
|
|
|
|
L1 |
VMEM |
PWR |
--- |
L2 |
VSS |
GND |
--- |
L3 |
DQ6 |
I/O |
DDR |
|
|
|
|
L4 |
SDCLK0N |
O |
DDRCLK |
|
|
|
|
L28 |
SDCLK2N |
O |
DDRCLK |
|
|
|
|
L29 |
DQ60 |
I/O |
DDR |
|
|
|
|
L30 |
VSS |
GND |
--- |
L31 |
VMEM |
PWR |
--- |
M1 |
DQM0 |
I/O |
DDR |
|
|
|
|
M2 |
DQS0 |
I/O |
DDR |
|
|
|
|
M3 |
DQ2 |
I/O |
DDR |
|
|
|
|
M4 |
SDCLK0P |
O |
DDRCLK |
|
|
|
|
M28 |
SDCLK2P |
O |
DDRCLK |
|
|
|
|
M29 |
DQ61 |
I/O |
DDR |
|
|
|
|
M30 |
DQ57 |
I/O |
DDR |
|
|
|
|
M31 |
DQ56 |
I/O |
DDR |
|
|
|
|
N1 |
DQ5 |
I/O |
DDR |
|
|
|
|
N2 |
DQ1 |
I/O |
DDR |
|
|
|
|
N3 |
VSS |
GND |
--- |
N4 |
VMEM |
PWR |
--- |
N13 |
VCORE |
PWR |
--- |
N14 |
VCORE |
PWR |
--- |
N15 |
VSS |
GND |
--- |
N16 |
VSS |
GND |
--- |
N17 |
VSS |
GND |
--- |
N18 |
VCORE |
PWR |
--- |
N19 |
VCORE |
PWR |
--- |
Ball |
Signal Name |
Type |
Buffer |
No. |
(Note 1) |
(PD) |
Type |
|
|
|
|
N28 |
VSS |
GND |
--- |
N29 |
VMEM |
PWR |
--- |
N30 |
DQM7 |
I/O |
DDR |
|
|
|
|
N31 |
DQS7 |
I/O |
DDR |
|
|
|
|
P1 |
MVREF |
I |
--- |
|
|
|
|
P2 |
DQ0 |
I/O |
DDR |
|
|
|
|
P3 |
DQ4 |
I/O |
DDR |
|
|
|
|
P4 |
VSS |
GND |
--- |
P13 |
VCORE |
PWR |
--- |
P14 |
VCORE |
PWR |
--- |
P15 |
VSS |
GND |
--- |
P16 |
VSS |
GND |
--- |
P17 |
VSS |
GND |
--- |
P18 |
VCORE |
PWR |
--- |
P19 |
VCORE |
PWR |
--- |
P28 |
VSS |
GND |
--- |
P29 |
VMEM |
PWR |
--- |
P30 |
DQ62 |
I/O |
DDR |
|
|
|
|
P31 |
VSS |
GND |
--- |
R1 |
VSS |
GND |
--- |
R2 |
VSS |
GND |
--- |
R3 |
VSS |
GND |
--- |
R4 |
VSS |
GND |
--- |
R13 |
VSS |
GND |
--- |
R14 |
VSS |
GND |
--- |
R15 |
VSS |
GND |
--- |
R16 |
VSS |
GND |
--- |
R17 |
VSS |
GND |
--- |
R18 |
VSS |
GND |
--- |
R19 |
VSS |
GND |
--- |
R28 |
VCORE |
PWR |
--- |
R29 |
DQ63 |
I/O |
DDR |
|
|
|
|
R30 |
DQ58 |
I/O |
DDR |
|
|
|
|
R31 |
DQ59 |
I/O |
DDR |
|
|
|
|
T1 |
VCORE |
PWR |
--- |
T2 |
VCORE |
PWR |
--- |
T3 |
VCORE |
PWR |
--- |
T4 |
VCORE |
PWR |
--- |
T13 |
VSS |
GND |
--- |
T14 |
VSS |
GND |
--- |
T15 |
VSS |
GND |
--- |
T16 |
VSS |
GND |
--- |
T17 |
VSS |
GND |
--- |
T18 |
VSS |
GND |
--- |
T19 |
VSS |
GND |
--- |
T28 |
VSS |
GND |
--- |
T29 |
VSS |
GND |
--- |
T30 |
VSS |
GND |
--- |
Ball |
Signal Name |
Type |
Buffer |
No. |
(Note 1) |
(PD) |
Type |
|
|
|
|
T31 |
VSS |
GND |
--- |
U1 |
DAVDD |
APWR |
--- |
U2 |
BLUE |
A |
--- |
|
|
|
|
U3 |
DAVSS |
AGND |
--- |
U4 |
VCORE |
PWR |
--- |
U13 |
VSS |
GND |
--- |
U14 |
VSS |
GND |
--- |
U15 |
VSS |
GND |
--- |
U16 |
VSS |
GND |
--- |
U17 |
VSS |
GND |
--- |
U18 |
VSS |
GND |
--- |
U19 |
VSS |
GND |
--- |
U28 |
VCORE |
PWR |
--- |
U29 |
VCORE |
PWR |
--- |
U30 |
VCORE |
PWR |
--- |
U31 |
VCORE |
PWR |
--- |
V1 |
DAVDD |
APWR |
--- |
V2 |
GREEN |
A |
--- |
|
|
|
|
V3 |
DAVSS |
AGND |
--- |
V4 |
DAVDD |
APWR |
--- |
V13 |
VCORE |
PWR |
--- |
V14 |
VCORE |
PWR |
--- |
V15 |
VSS |
GND |
--- |
V16 |
VSS |
GND |
--- |
V17 |
VSS |
GND |
--- |
V18 |
VCORE |
PWR |
--- |
V19 |
VCORE |
PWR |
--- |
V28 |
VCORE |
PWR |
--- |
V29 |
MLPF |
A |
--- |
|
|
|
|
V30 |
MAVSS |
AGND |
--- |
V31 |
MAVDD |
APWR |
--- |
W1 |
DVREF |
A |
--- |
|
|
|
|
W2 |
DAVSS |
AGND |
--- |
W3 |
RED |
A |
--- |
|
|
|
|
W4 |
DAVDD |
APWR |
--- |
W13 |
VCORE |
PWR |
--- |
W14 |
VCORE |
PWR |
--- |
W15 |
VSS |
GND |
--- |
W16 |
VSS |
GND |
--- |
W17 |
VSS |
GND |
--- |
W18 |
VCORE |
PWR |
--- |
W19 |
VCORE |
PWR |
DDR |
W28 |
VSS |
GND |
--- |
W29 |
CLPF |
A |
--- |
|
|
|
|
W30 |
CAVSS |
AGND |
--- |
W31 |
CAVDD |
APWR |
--- |
Y1 |
DRSET |
A |
--- |
|
|
|
|
AMD Geode™ LX Processors Data Book |
27 |
33234H |
Signal Definitions |
Table 3-5. Ball Assignments - Sorted by Ball Number (Continued)
Ball |
Signal Name |
Type |
Buffer |
No. |
(Note 1) |
(PD) |
Type |
|
|
|
|
Y2 |
DAVSS |
AGND |
--- |
Y3 |
VIO |
PWR |
--- |
Y4 |
VSS |
GND |
--- |
Y28 |
VCORE |
PWR |
--- |
Y29 |
VSS |
GND |
--- |
Y30 |
RESET# |
I |
PCI |
|
|
|
|
Y31 |
SYSREF |
I |
PCI |
|
|
|
|
AA1 |
VAVDD |
APWR |
--- |
AA2 |
VAVSS |
AGND |
--- |
AA3 |
VLPF |
A |
--- |
|
|
|
|
AA4 |
TMS |
I |
24/Q7 |
|
|
|
|
AA28 |
GNT0# |
I/O |
PCI |
|
|
|
|
AA29 |
REQ0# |
I |
PCI |
|
|
|
|
AA30 |
VSS |
GND |
--- |
AA31 |
VIO |
PWR |
--- |
AB1 |
DOTREF |
I |
PCI |
|
|
|
|
AB2 |
TDBGI |
I |
24/Q7 |
|
|
|
|
AB3 |
TDI |
I |
24/Q7 |
|
|
|
|
AB4 |
TDBGO |
O (PD) |
24/Q3 |
|
|
|
|
AB28 |
REQ2# |
I/O |
PCI |
|
|
|
|
AB29 |
IRQ13 |
I/O (PD) |
24/Q5 |
|
|
|
|
AB30 |
GNT1# |
I/O |
PCI |
|
|
|
|
AB31 |
REQ1# |
I/O |
PCI |
|
|
|
|
AC1 |
TDO |
O |
24/Q5 |
|
|
|
|
AC2 |
TCLK |
I |
24/Q7 |
|
|
|
|
AC3 |
VIO |
PWR |
--- |
AC4 |
VSS |
GND |
--- |
AC28 |
VSS |
GND |
--- |
AC29 |
VIO |
PWR |
--- |
AC30 |
GNT2# |
I/O |
PCI |
|
|
|
|
AC31 |
SUSPA# |
I/O |
24/Q5 |
|
|
|
|
AD1 |
VIO |
PWR |
--- |
AD2 |
VSS |
GND |
--- |
AD3 |
VSYNC |
O (PD) |
5V |
|
|
|
|
|
VOP_VSYNC |
O |
|
|
|
|
|
AD4 |
LDEMOD |
I/O (PD) |
24/Q5 |
|
|
|
|
|
VIP_VSYNC |
I |
|
|
|
|
|
AD28 |
INTA# |
I/O (PD) |
24/Q5 |
|
|
|
|
AD29 |
AD31 |
I/O |
PCI |
|
|
|
|
AD30 |
VSS |
GND |
--- |
AD31 |
VIO |
PWR |
--- |
AE1 |
DOTCLK |
O (PD) |
24/Q3 |
|
|
|
|
|
VOPCLK |
O |
|
|
|
|
|
AE2 |
VDDEN |
I/O (PD) |
24/Q5 |
|
|
|
|
|
VIP_HSYNC |
I |
|
|
|
|
|
AE3 |
HSYNC |
O (PD) |
5V |
|
|
|
|
|
VOP_HSYNC |
O |
|
|
|
|
|
AE4 |
DISPEN |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP_BLANK |
O |
|
|
|
|
|
AE28 |
AD27 |
I/O |
PCI |
|
|
|
|
Ball |
Signal Name |
Type |
Buffer |
No. |
(Note 1) |
(PD) |
Type |
|
|
|
|
AE29 |
CIS |
I/O |
24/Q7 |
|
|
|
|
AE30 |
AD29 |
I/O |
PCI |
|
|
|
|
AE31 |
AD30 |
I/O |
PCI |
|
|
|
|
AF1 |
DRGB17 |
O (PD) |
24/Q5 |
|
|
|
|
AF2 |
DRGB16 |
O (PD) |
24/Q5 |
|
|
|
|
AF3 |
VIO |
PWR |
--- |
AF4 |
VSS |
GND |
--- |
AF28 |
VSS |
GND |
--- |
AF29 |
VIO |
PWR |
--- |
AF30 |
AD26 |
I/O |
PCI |
|
|
|
|
AF31 |
AD28 |
I/O |
PCI |
|
|
|
|
AG1 |
VIO |
PWR |
--- |
AG2 |
VSS |
GND |
--- |
AG3 |
DRGB18 |
O (PD) |
24/Q5 |
|
|
|
|
AG4 |
DRGB19 |
O (PD) |
24/Q5 |
|
|
|
|
AG28 |
AD25 |
I/O |
PCI |
|
|
|
|
AG29 |
AD24 |
I/O |
PCI |
|
|
|
|
AG30 |
VSS |
GND |
--- |
AG31 |
VIO |
PWR |
--- |
AH1 |
DRGB20 |
O (PD) |
24/Q5 |
|
|
|
|
AH2 |
DRGB21 |
O (PD) |
24/Q5 |
|
|
|
|
AH3 |
DRGB22 |
O (PD) |
24/Q5 |
|
|
|
|
AH4 |
VSS |
GND |
--- |
AH5 |
DRGB11 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP12 |
O |
|
|
|
|
|
AH6 |
VSS |
GND |
--- |
AH7 |
DRGB0 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP7 |
O |
|
|
|
|
|
AH8 |
DRGB6 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP1 |
O |
|
|
|
|
|
AH9 |
VSS |
GND |
--- |
AH10 |
DRGB29 |
I/O (PD) |
24/Q5 |
|
|
|
|
|
VID13 |
I |
|
|
|
|
|
AH11 |
DRGB24 |
I/O (PD) |
24/Q5 |
|
|
|
|
|
MSGSTART |
I |
|
|
|
|
|
|
VID8 |
I |
|
|
|
|
|
AH12 |
VSS |
GND |
--- |
AH13 |
VID3 |
I/O (PD) |
24/Q7 |
|
|
|
|
AH14 |
VSS |
GND |
--- |
AH15 |
VCORE |
PWR |
--- |
AH16 |
VSS |
GND |
--- |
AH17 |
VCORE |
PWR |
--- |
AH18 |
VSS |
GND |
--- |
AH19 |
AD1 |
I/O |
PCI |
|
|
|
|
AH20 |
VSS |
GND |
--- |
AH21 |
AD5 |
I/O |
PCI |
|
|
|
|
AH22 |
AD11 |
I/O |
PCI |
|
|
|
|
AH23 |
VSS |
GND |
--- |
AH24 |
AD14 |
I/O |
PCI |
|
|
|
|
AH25 |
IRDY# |
I/O |
PCI |
|
|
|
|
Ball |
Signal Name |
Type |
Buffer |
No. |
(Note 1) |
(PD) |
Type |
|
|
|
|
AH26 |
VSS |
GND |
--- |
AH27 |
CBE2# |
I/O |
PCI |
|
|
|
|
AH28 |
VSS |
GND |
--- |
AH29 |
AD23 |
I/O |
PCI |
|
|
|
|
AH30 |
AD22 |
I/O |
PCI |
|
|
|
|
AH31 |
CBE3# |
I/O |
PCI |
|
|
|
|
AJ1 |
DRGB23 |
O (PD) |
24/Q5 |
|
|
|
|
AJ2 |
DRGB8 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP15 |
O |
|
|
|
|
|
AJ3 |
VIO |
PWR |
--- |
AJ4 |
DRGB12 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP11 |
O |
|
|
|
|
|
AJ5 |
DRGB15 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP8 |
O |
|
|
|
|
|
AJ6 |
VIO |
PWR |
--- |
AJ7 |
DRGB3 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP4 |
O |
|
|
|
|
|
AJ8 |
DRGB7 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP0 |
O |
|
|
|
|
|
AJ9 |
VIO |
PWR |
--- |
AJ10 |
DRGB28 |
I/O (PD) |
24/Q5 |
|
|
|
|
|
VID12 |
O |
|
|
|
|
|
AJ11 |
DRGB25 |
I/O (PD) |
24/Q5 |
|
|
|
|
|
MSGSTOP |
I |
|
|
|
|
|
|
VID9 |
I |
|
|
|
|
|
AJ12 |
VIO |
PWR |
--- |
AJ13 |
VID4 |
I/O (PD) |
24/Q7 |
|
|
|
|
AJ14 |
VIO |
PWR |
--- |
AJ15 |
VID0 |
I/O (PD) |
24/Q7 |
|
|
|
|
AJ16 |
VSS |
GND |
--- |
AJ17 |
PW1 |
I/O |
24/Q7 |
|
|
|
|
AJ18 |
VIO |
PWR |
--- |
AJ19 |
AD0 |
I/O |
PCI |
|
|
|
|
AJ20 |
VIO |
PWR |
--- |
AJ21 |
AD6 |
I/O |
PCI |
|
|
|
|
AJ22 |
CBE0# |
I/O |
PCI |
|
|
|
|
AJ23 |
VIO |
PWR |
--- |
AJ24 |
AD15 |
I/O |
PCI |
|
|
|
|
AJ25 |
STOP# |
I/O |
PCI |
|
|
|
|
AJ26 |
VIO |
PWR |
--- |
AJ27 |
PAR |
I/O |
PCI |
|
|
|
|
AJ28 |
AD16 |
I/O |
PCI |
|
|
|
|
AJ29 |
VIO |
PWR |
--- |
AJ30 |
AD19 |
I/O |
PCI |
|
|
|
|
AJ31 |
AD21 |
I/O |
PCI |
|
|
|
|
AK1 |
VIO |
PWR |
--- |
AK2 |
VSS |
GND |
--- |
AK3 |
DRGB9 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP14 |
O |
|
|
|
|
|
28 |
AMD Geode™ LX Processors Data Book |
Signal Definitions |
33234H |
Table 3-5. Ball Assignments - Sorted by Ball Number (Continued)
Ball |
Signal Name |
Type |
Buffer |
No. |
(Note 1) |
(PD) |
Type |
|
|
|
|
AK4 |
DRGB14 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP9 |
O |
|
|
|
|
|
AK5 |
VSS |
GND |
--- |
AK6 |
DRGB1 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP6 |
O |
|
|
|
|
|
AK7 |
DRGB4 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP3 |
O |
|
|
|
|
|
AK8 |
VSS |
GND |
--- |
AK9 |
DRGB31 |
I/O (PD) |
24/Q5 |
|
|
|
|
|
VID15 |
I |
|
|
|
|
|
AK10 |
DRGB26 |
I/O (PD) |
24/Q5 |
|
|
|
|
|
VID10 |
I |
|
|
|
|
|
AK11 |
VSS |
GND |
--- |
AK12 |
VID7 |
I/O (PD) |
24/Q7 |
|
|
|
|
AK13 |
VID5 |
I/O (PD) |
24/Q7 |
|
|
|
|
AK14 |
VSS |
GND |
--- |
AK15 |
VID1 |
I/O (PD) |
24/Q7 |
|
|
|
|
AK16 |
VSS |
GND |
--- |
AK17 |
TDN |
A |
A |
|
|
|
|
AK18 |
VSS |
GND |
--- |
AK19 |
AD4 |
I/O |
PCI |
|
|
|
|
AK20 |
AD3 |
I/O |
PCI |
|
|
|
|
AK21 |
VSS |
GND |
--- |
AK22 |
AD8 |
I/O |
PCI |
|
|
|
|
AK23 |
AD10 |
I/O |
PCI |
|
|
|
|
Ball |
Signal Name |
Type |
Buffer |
No. |
(Note 1) |
(PD) |
Type |
|
|
|
|
AK24 |
VSS |
GND |
--- |
AK25 |
DEVSEL# |
I/O |
PCI |
|
|
|
|
AK26 |
TRDY# |
I/O |
PCI |
|
|
|
|
AK27 |
VSS |
GND |
--- |
AK28 |
AD17 |
I/O |
PCI |
|
|
|
|
AK29 |
AD20 |
I/O |
PCI |
|
|
|
|
AK30 |
VSS |
GND |
--- |
AK31 |
VIO |
PWR |
--- |
AL1 |
VSS |
GND |
--- |
AL2 |
VIO |
PWR |
--- |
AL3 |
DRGB10 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP13 |
O |
|
|
|
|
|
AL4 |
DRGB13 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP10 |
O |
|
|
|
|
|
AL5 |
VIO |
PWR |
--- |
AL6 |
DRGB2 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP5 |
O |
|
|
|
|
|
AL7 |
DRGB5 |
O (PD) |
24/Q5 |
|
|
|
|
|
VOP2 |
O |
|
|
|
|
|
AL8 |
VIO |
PWR |
--- |
AL9 |
DRGB30 |
I/O (PD) |
24/Q5 |
|
|
|
|
|
VID14 |
I |
|
|
|
|
|
AL10 |
DRGB27 |
I/O (PD) |
24/Q5 |
|
|
|
|
|
VID11 |
I |
|
|
|
|
|
Ball |
Signal Name |
Type |
Buffer |
No. |
(Note 1) |
(PD) |
Type |
|
|
|
|
AL11 |
VIO |
PWR |
--- |
AL12 |
VIPCLK |
I/O (PD) |
5V |
|
|
|
|
AL13 |
VID6 |
I/O (PD) |
24/Q7 |
|
|
|
|
AL14 |
VIPSYNC |
I/O (PD) |
5V |
|
|
|
|
AL15 |
VID2 |
I/O (PD) |
24/Q7 |
|
|
|
|
AL16 |
VSS |
GND |
--- |
AL17 |
TDP |
A |
--- |
|
|
|
|
AL18 |
PW0 |
I/O |
24/Q7 |
|
|
|
|
AL19 |
AD7 |
I/O |
PCI |
|
|
|
|
AL20 |
AD2 |
I/O |
PCI |
|
|
|
|
AL21 |
VIO |
PWR |
--- |
AL22 |
AD9 |
I/O |
PCI |
|
|
|
|
AL23 |
AD12 |
I/O |
PCI |
|
|
|
|
AL24 |
VIO |
PWR |
--- |
AL25 |
AD13 |
I/O |
PCI |
|
|
|
|
AL26 |
CBE1# |
I/O |
PCI |
|
|
|
|
AL27 |
VIO |
PWR |
--- |
AL28 |
FRAME# |
I/O |
PCI |
|
|
|
|
AL29 |
AD18 |
I/O |
PCI |
|
|
|
|
AL30 |
VIO |
PWR |
--- |
AL31 |
VSS |
GND |
--- |
Note 1.The primary signal name is listed first.
AMD Geode™ LX Processors Data Book |
29 |
33234H Signal Definitions
Table 3-6. Ball Assignments - Sorted Alphabetically by Signal Name
Signal Name |
Ball No. |
|
Signal Name |
Ball No. |
|
Signal Name |
Ball No. |
|
|
|
|
|
|
|
|
AD0 |
AJ19 |
|
CS1# |
F28 |
|
DQ39 |
A20 |
|
|
|
|
|
|
|
|
AD1 |
AH19 |
|
CS2# |
F29 |
|
DQ40 |
A22 |
|
|
|
|
|
|
|
|
AD2 |
AL20 |
|
CS3# |
D30 |
|
DQ41 |
A23 |
|
|
|
|
|
|
|
|
AD3 |
AK20 |
|
DAVDD |
U1, V1, V4, W4 |
|
DQ42 |
A25 |
AD4 |
AK19 |
|
DAVSS |
U3, V3, Y2, W2 |
|
DQ43 |
A26 |
AD5 |
AH21 |
|
DEVSEL# |
AK25 |
|
DQ44 |
C22 |
|
|
|
|
|
|
|
|
AD6 |
AJ21 |
|
DISPEN |
AE4 |
|
DQ45 |
C23 |
|
|
|
|
|
|
|
|
AD7 |
AL19 |
|
DOTCLK |
AE1 |
|
DQ46 |
B25 |
|
|
|
|
|
|
|
|
AD8 |
AK22 |
|
DOTREF |
AB1 |
|
DQ47 |
B26 |
|
|
|
|
|
|
|
|
AD9 |
AL22 |
|
DQ0 |
P2 |
|
DQ48 |
D31 |
|
|
|
|
|
|
|
|
AD10 |
AK23 |
|
DQ1 |
N2 |
|
DQ49 |
F31 |
|
|
|
|
|
|
|
|
AD11 |
AH22 |
|
DQ2 |
M3 |
|
DQ50 |
K30 |
|
|
|
|
|
|
|
|
AD12 |
AL23 |
|
DQ3 |
K2 |
|
DQ51 |
K31 |
|
|
|
|
|
|
|
|
AD13 |
AL25 |
|
DQ4 |
P3 |
|
DQ52 |
G30 |
|
|
|
|
|
|
|
|
AD14 |
AH24 |
|
DQ5 |
N1 |
|
DQ53 |
G31 |
|
|
|
|
|
|
|
|
AD15 |
AJ24 |
|
DQ6 |
L3 |
|
DQ54 |
J31 |
|
|
|
|
|
|
|
|
AD16 |
AJ28 |
|
DQ7 |
K1 |
|
DQ55 |
J30 |
|
|
|
|
|
|
|
|
AD17 |
AK28 |
|
DQ8 |
J2 |
|
DQ56 |
M31 |
|
|
|
|
|
|
|
|
AD18 |
AL29 |
|
DQ9 |
J1 |
|
DQ57 |
M30 |
|
|
|
|
|
|
|
|
AD19 |
AJ30 |
|
DQ10 |
F3 |
|
DQ58 |
R30 |
|
|
|
|
|
|
|
|
AD20 |
AK29 |
|
DQ11 |
E3 |
|
DQ59 |
R31 |
|
|
|
|
|
|
|
|
AD21 |
AJ31 |
|
DQ12 |
J3 |
|
DQ60 |
L29 |
|
|
|
|
|
|
|
|
AD22 |
AH30 |
|
DQ13 |
G1 |
|
DQ61 |
M29 |
|
|
|
|
|
|
|
|
AD23 |
AH29 |
|
DQ14 |
F2 |
|
DQ62 |
P30 |
|
|
|
|
|
|
|
|
AD24 |
AG29 |
|
DQ15 |
F1 |
|
DQ63 |
R29 |
|
|
|
|
|
|
|
|
AD25 |
AG28 |
|
DQ16 |
D2 |
|
DQM0 |
M1 |
|
|
|
|
|
|
|
|
AD26 |
AF30 |
|
DQ17 |
B4 |
|
DQM1 |
G2 |
|
|
|
|
|
|
|
|
AD27 |
AE28 |
|
DQ18 |
B6 |
|
DQM2 |
A6 |
|
|
|
|
|
|
|
|
AD28 |
AF31 |
|
DQ19 |
C8 |
|
DQM3 |
B10 |
|
|
|
|
|
|
|
|
AD29 |
AE30 |
|
DQ20 |
D1 |
|
DQM4 |
A19 |
|
|
|
|
|
|
|
|
AD30 |
AE31 |
|
DQ21 |
A4 |
|
DQM5 |
C24 |
|
|
|
|
|
|
|
|
AD31 |
AD29 |
|
DQ22 |
A7 |
|
DQM6 |
H29 |
|
|
|
|
|
|
|
|
BA0 |
D26 |
|
DQ23 |
B7 |
|
DQM7 |
N30 |
|
|
|
|
|
|
|
|
BA1 |
C20 |
|
DQ24 |
B9 |
|
DQS0 |
M2 |
|
|
|
|
|
|
|
|
BLUE |
U2 |
|
DQ25 |
C10 |
|
DQS1 |
H3 |
|
|
|
|
|
|
|
|
CAS0# |
E28 |
|
DQ26 |
A12 |
|
DQS2 |
C6 |
|
|
|
|
|
|
|
|
CAS1# |
E29 |
|
DQ27 |
B12 |
|
DQS3 |
A10 |
|
|
|
|
|
|
|
|
CAVDD |
W31 |
|
DQ28 |
A9 |
|
DQS4 |
C19 |
CAVSS |
W30 |
|
DQ29 |
C9 |
|
DQS5 |
B23 |
CBE0# |
AJ22 |
|
DQ30 |
C11 |
|
DQS6 |
J29 |
|
|
|
|
|
|
|
|
CBE1# |
AL26 |
|
DQ31 |
A13 |
|
DQS7 |
N31 |
|
|
|
|
|
|
|
|
CBE2# |
AH27 |
|
DQ32 |
A15 |
|
DRGB0 |
AH7 |
|
|
|
|
|
|
|
|
CBE3# |
AH31 |
|
DQ33 |
B17 |
|
DRGB1 |
AK6 |
|
|
|
|
|
|
|
|
CIS |
AE29 |
|
DQ34 |
B19 |
|
DRGB2 |
AL6 |
|
|
|
|
|
|
|
|
CKE0 |
E4 |
|
DQ35 |
B22 |
|
DRGB3 |
AJ7 |
|
|
|
|
|
|
|
|
CKE1 |
F4 |
|
DQ36 |
B16 |
|
DRGB4 |
AK7 |
|
|
|
|
|
|
|
|
CLPF |
W29 |
|
DQ37 |
A17 |
|
DRGB5 |
AL7 |
|
|
|
|
|
|
|
|
CS0# |
B28 |
|
DQ38 |
B20 |
|
DRGB6 |
AH8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
30 |
|
|
|
|
AMD Geode™ LX Processors Data Book |
||
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