Data Sheet
August 1999
LG1600FXH Clock and Data Regenerator
Features
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Integrated clock recovery and data retiming |
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Surface-mount package |
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Single ECL supply |
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Robust FPLL design |
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Operation up to BER = 1e–3 |
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SONET/SDH compatible loss of signal alarm |
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High effective Q allows long run lengths |
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Jitter tolerance exceeding ITU-T/Bellcore |
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Low clock jitter generation: typical <0.005 UI |
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Standard and custom data rates |
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0.50 Gbits/s—5.5 Gbits/s |
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Complementary 50 Ω I/Os |
Figure 1. LG1600FXH Open View |
Applications |
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SONET/SDH receiver terminals and regenerators |
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OC-12 through OC-96/STM-4 through STM-32 |
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SONET/SDH test equipment |
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Proprietary bit rate systems |
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Digital video transmission |
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Clock doublers and quadruplers |
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Data Sheet |
LG1600FXH Clock and Data Regenerator |
August 1999 |
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Functional Description
The LG1600FXH Clock and Data Regenerator (CDR) is a compact, single device solution to clock recovery and data retiming in high-speed communication systems such as fiber-optic data links and long-span fiberoptic regenerators and terminals. Using frequency and phase-lock loop (FPLL) techniques, the device regenerates clean clock and error-free data signals from a nonreturn-to-zero (NRZ) data input, corrupted by jitter and intersymbol interference. The LG1600FXH exceeds ITU-T/Bellcore jitter tolerance requirements for SONET/SDH systems.
The device houses two integrated circuits on an alumina substrate inside a hermetically sealed 3 cm ×
3 cm (1.2 in. × 1.2 in.) surface-mount package: a GaAs IC that contains the high-speed part of an FPLL as well as a highly sensitive decision circuit; and a silicon bipolar IC that contains a loop filter, acquisition, and signal detect circuitry.
The two ac-coupled complementary data inputs can be driven differentially as well as single ended. A dc feedback voltage V–FB maintains a data input threshold V–TH (decision level) that is optimum for a wide range of 50% duty cycle input levels (connect to V–TH). If needed, the user can supply an external threshold to compensate for different mark densities or distorted input signals (see Figure 10).
Regenerated clock and data are available from complementary outputs that can either be ac coupled, to provide 50 Ω output match, or dc coupled with 50 Ω to ground at the receiving end.
The second-order PLL filter bandwidth is set by the user with an external resistor between pin 11 and ground (required). An internal capacitor provides sufficient PLL damping for most applications. In critical applications, PLL damping can be increased using an external capacitor between pins 9 and 11.
The device is powered by a single –5.2 V ECL compatible supply and typically consumes 1.5 W.
The LG1600FXH comes in standard bit rates, but can be factory tuned for any rate between 500 Mbits/s and 5500 Mbits/s.
A test fixture (TF1004A) with SMA connectors is available to allow quick evaluation of the LG1600FXH.
Theory of Operation
A digital regenerator has the task of retransmitting a bit stream that is received from a remote source with the same fidelity at which it was originally transmitted.
Two basic properties of the digital signal need to be restored: the timing of the transitions between the bits and the value of each bit.
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VREF |
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LOS |
12-3225(F)r.6
Figure 2. LG1600FXH Block Diagram
2 |
Lucent Technologies Inc. |
Data Sheet |
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August 1999 |
LG1600FXH Clock and Data Regenerator |
Theory of Operation (continued)
Consequently, the timing information that is present in the data needs to be extracted and a decision as to the value of each bit must be made. Both timing instant and decision levels are critical, since the economics of data transmission dictate the largest distance possible between transmitter and receiver. A practically closed data eye can therefore be expected at the output of the receiver, allowing only a small decision window.
An added complication in nonreturn-to-zero (NRZ) systems is the absence of clock component in the data signal itself. Practical clock recovery circuits have used a combination of nonlinear processing to extract a spectral component at the clock frequency and narrowband filtering using a SAW filter or dielectric resonator. The relative bandwidth of such a filter must be on the order of a few tenths of a percent to minimize the data pattern dependence of the resulting clock. Temperature behavior of the passband characteristics, such as group delay, must be tightly matched to that of the data path. These extreme requirements make such a discrete design very difficult to manufacture at Gbits/s data rates.
The LG1600FXH clock and data regenerator relies on phase-lock loop techniques, rather than passive filtering. The filter properties of a PLL are determined at low frequencies where parasitic elements play only a minor roll and stability is easily maintained. Furthermore, the reference frequency is determined by the data rate itself, rather than by the physical properties of a bandpass filter.
Although PLLs can eliminate some of the shortcomings of passive bandpass filters used in clock recovery circuits, care was taken in the design of the LG1600FXH to preserve desired properties such as linearity of the jitter characteristics. A linear jitter transfer makes it a lot easier for the system designer to predict the overall performance of a link.
As a result, the architecture chosen for the device is not basically different from the conventional clock recovery circuit. A transition detector extracts a pulse train from the incoming data signal which is used as a reference signal for a PLL. The transition pulse train can be seen as a clock signal that is modulated with the instantaneous transition density of the data signal. The PLL locks onto the frequency and phase of this pulse train and freewheels during times when transitions are absent. The LG1600FXH features dual phase detectors; one driven by an in-phase clock which is also driving the decision circuit flip-flop, the other is driven by a quadrature clock. The phase detectors produce a zero output when their respective clocks are centered with respect to the transition pulses.
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TRANSITION |
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12-3226(F)r.3 |
Figure 3. Frequency and Phase Detector
For a transition pulse of half the width of the bit period, the timing diagram of Figure 4 shows how the in-phase clock ends up in the center of the data eye when the quadrature-phase detector output is forced to zero by the loop. The (patented) transition detector is comprised of an (active) circulator, a shorted stub, and an exclusive-OR gate. The circulator/stub combination produces a delayed version of the data. A transition at the input of the circuit results in an output pulse from the exclusive-OR gate whose width equals the return delay of the stub. The stub is tuned for a given bit rate and can be adjusted so that the in-phase clock is exactly centered in the error-free phase range of the retiming flip-flop.
T
1/2 T
1/4 T
DATA
DELAYED
DATA
TRANSITION
PULSE
0° CLOCK
90° CLOCK
12-3227(F)r.2
Figure 4. Timing Diagram
Lucent Technologies Inc. |
3 |
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Data Sheet |
LG1600FXH Clock and Data Regenerator |
August 1999 |
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Theory of Operation (continued)
FPD OUT
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PHASE |
12-3228(F)r.4
Figure 5. Frequency and Phase Detector
Characteristics
The frequency detector is not a separate function but an integral part of the phase-lock loop. Any transition between frequency and phase acquisition is completely avoided. Figure 5 shows the output characteristics of the FPD, which is essentially an extended range phase detector. The two quadrature clock phases are used to produce hysteresis, which extends the phase detector range to ±270°. The extended range gives the phase detector a static frequency sensitivity as demonstrated in Figure 6. For clock frequencies lower than the bit rate (the phase is increasing), the top trajectory of the diagram in Figure 6 is followed. When the VCO frequency exceeds the bit rate, the lower trajectory applies. Since the linear part of the phase detector produces a netzero output, in the first instance, positive pulses are fed into the loop filter increasing the VCO frequency, while in the latter case, the FPD produces negative pulses.
The wide, 540° range of the phase detector is also responsible for the high jitter tolerance of the LG1600FXH and an associated immunity to cycle slip under high jitter conditions. The clock can be momentarily misaligned as much as 270° but still return to its original position. This property is extremely important in synchronous systems, since a cycle slip would cause misalignment of the demultiplexer following the circuit resulting in a loss of frame condition. The LG1600FXH can handle bit error rates up to 1e–3 as a result of lowfrequency jitter.
FPD
OUT
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A. fck < fB
FPD
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B. fck > fB
12-3229(F)r.4
Figure 6. Frequency Detector Operation
PLL Dimensioning
The LG1600FXH CDR employs a heavily damped second order phase-lock loop. A linear model of this PLL is depicted in Figure 7. The conventional secondorder equation describing the jitter transfer of the PLL is shown below:
ϕo |
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where ϕi and ϕo denote the input and output phase, respectively, ς is the PLL damping ratio and ωn is the natural frequency. For most clock recovery applications a very high damping is required, that renders the PLL essentially as a first-order system with a slight peaking that is generally undesirable. The second-order equation above does not provide much insight into the peaking and bandwidth parameters.
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12-3230(F)r.5 |
Figure 7. Phase-Lock Loop Linear Model
4 |
Lucent Technologies Inc. |
Data Sheet |
|
August 1999 |
LG1600FXH Clock and Data Regenerator |
Theory of Operation (continued)
A more useful expression of the PLL characteristics is the following*:
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The jitter transfer is now directly expressed in the physical loop gain pole product, ωb, and the loop filter time constant, τ. Damping ratio, ς, and natural frequency, ωn, simply relate to these two parameters as follows:
V = 0.5wbt and
wn = wn ¤ t
*Wolaver, D.H., Phase-Locked Loop Circuit Design, Prentice Hall, 1991.
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Rx (Ω)
A. LG1600FXH0622 (Cx = 0.15 μF)
For moderate damping ς > 2.5 (ωbτ < 0.1), the –3 dB bandwidth of the PLL can be approximated by the loop gain pole product:
JBW ≈ ωb = KdRxKo
while the jitter peaking can be expressed in terms of the product of PLL bandwidth and loop filter time constant:
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As the last two expressions make clear, the PLL bandwidth is controlled by the value of the external resistor (see Figure 8), while the peaking depends both on the resistor value (quadratically) and total loop filter capacitance.
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B. LG1600FXH2488 (Cx = 0)
12-3231(F)r.4—12-3232(F)r.4
Figure 8. Jitter Bandwidth vs. External Resistor Value
Lucent Technologies Inc. |
5 |
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Data Sheet |
LG1600FXH Clock and Data Regenerator |
August 1999 |
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Pin Information
The pinout for the LG1600FXH is shown in Figure 9.
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NIC |
GND GND |
V+FB GND GND GND GND V+IN |
GND GND GND GND V–IN GND |
GND |
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GND |
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3 |
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49 |
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DNC |
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4 |
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48 |
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V–FB |
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GND |
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GND |
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GND |
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VREF |
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GND |
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44 |
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GND |
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CEXT |
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9 |
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43 |
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V+OUT |
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GND |
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10 |
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42 |
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GND |
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REXT |
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11 |
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41 |
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GND |
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GND |
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12 |
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40 |
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GND |
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GND |
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13 |
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39 |
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GND |
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LOS |
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14 |
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38 |
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V–OUT |
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GND |
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15 |
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37 |
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GND |
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GND |
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16 |
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36 |
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GND |
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DNC |
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17 |
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35 |
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VSS |
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18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 |
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NIC |
GND GND |
GND GND GND GND GND V–CLKO |
GND GND GND GND V+CLKO GND |
GND |
GND |
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12-3233(F)r.1
Figure 9. Pin Diagram
6 |
Lucent Technologies Inc. |