Acer aspire 3690 Schematics
A
1 1
B
C
D
E
Compal Confidential
2 2
HBL51 Schematics Document
Intel Yonah Processor with 945GM/945PM + DDRII + ICH7M
3 3
2005-11-03
REV: 0.2
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
Cover Page
HBL51 LA-3081P
E
147Wednesday, November 09, 2005
0.2
of
A
B
C
D
E
Compal Confidential
Thermal Sensor
F75383M
page 4
Memory BUS(DDRII)
Dual Channel
1.8V DDRII 400/533
New Card
page 29
Socket
Model Nam e : H BL50
Fan Control
page 47
File Name : LA-2921
1 1
DVI-D Conn.
page 17
DVI
LCD Conn.
page 15
LVDS
CRT & TV-out
page 16
CH7307C SDVO
page 17
H_A#(3..31)
Yonah
uPGA-478 Package
page 4,5
PSB
533/667MHz
Intel 945PM/GM
uFCBGA-1466
page 6,7,8,9,10,11
H_D#(0..63)
DMI
PCI Express
2 2
IDSEL:AD16
(PIRQE#,
GNT#2,
REQ#2)
IEEE 1394
VT6311S
page 30
IDSEL:AD18
(PIRQG/H#,
GNT#3,
REQ#3)
Mini PCI
socket
(WLAN)
(TV-Tuner)
page 28
1394 Conn.
page 30
3.3V 33 MHz
IDSEL:AD17
(PIRQF#,
GNT#3,
REQ#3)
LAN (10/100)
BCM4401E
page 26
RJ45
page 27
PCI BUS
IDSEL:AD20
(PIRQA#,
GNT#2,
REQ#2)
CardBus
ENE CB714
Slot 0
page 25
page 24
6 in 1
socket
page 25
Intel ICH7-M
BGA-652
page 18,19,20,21
3.3V 48MHz
3.3V 24.576MHz/48Mhz
3.3V ATA-100
S-ATA
port 0
S-ATA HDD
Conn.
page 22
USB port 1
IDE
port 0
SATA-to-IDE
SPIF3811-HV096
page 22
LPC BUS
3 3
RTC CKT.
page 35
Power On/Off CKT.
page 35
DC/DC Int erface CKT.
page 40
Switch/B Conn.
USB port4, 6
page 34
LCM Conn.
page 34
ENE KB910Q
Touch Pad
page 35
EC I/O Bu ffer
page 33
page 32
Int.KBD
page 33
BIOS
page 33
Super I/O
SMsC LPC47N207
page 31
FIR
TFDU6102-TR3
page 31
TPM1.2
SLB9635 TT 1.2
page 31
Clock Generator
ICS9LPRS325
page 14
200pin DDRII-SO-DIMM X2
BANK 0, 1, 2, 3
LAN(GbE)
BCM5789
page 26
MINI CARD x2
page 28
HD Audio
CDROM
Conn.
page 23
HDD
Conn.
page 22
page 12,13
USB conn x4
USB port 3, 7
MDC 1.5
Conn
page 42
Audio AMP
Phone Jack x3
page 29
USB port 0, 2
HDA Codec
ALC883
page 37
page 37
Bluetooth
Conn
page 36
Subwoofer
page 37
page 34
USB port5
Power Circuit DC/DC
page 40,41,42,43
4 4
44,45,46,47
A
MEDIA/B Conn.
page 34
CIR
page 34
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
Block Diagrams
HBL51 LA-3081P
E
247Wednesday, November 09, 2005
0.2
of
A
Voltage Rails
Power Plane Description
VIN
1 1
2 2
B+
+CPU_CORE
+0.9VS 0.9V switched power rail for DDR terminator
+1.05VS
+1.5VS
+1.8V
+1.8VS 1.8V switched power rail
+2.5VS
+3VALW
+3VS
+5VALW
+5VS
+VSB VSB always on power rail ON ON *
+RT C V C C RTC power
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.05V switched power rail
1.5V switched power rail
1.8V power rail for DDR
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
B
S1 S3 S5
N/A N/A N/A
ON OFF
ON OFF
ON OFF OFF
ON OFF OFF
ON
ON
ON
ON
ON
ON
ON
ON
N/AN/AN/A
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON ON*
OFF
OFF
ON*
ON
OFFON
OFF
ONON
C
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SIGNAL
SLP_S1# SLP_S3#
HIGH HIGH HIGH HIGH
LOW
LOW
LOW LOW LOW LOW
SLP_S4# SLP_S5# +VALW +V +VS Clock
LOW
HIGH
LOWLOWLOW
D
HIGHHIGHHIGH
HIGH
HIGH
Board ID / SK U I D T ab l e for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
100K +/- 5%Ra/Rc/Re
Rb / Rd / Rf V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
Vtyp
ONONON ON
ON
ON
OFF
OFF
V
ON
OFF
OFF
OFF
AD_BID
ON
ON
ON
ON
AD_BID
0 V 0 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
2.200 V
3.300 V
2.341 V
3.300 V
E
LOW
OFF
OFF
OFF
max
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
Device IDSEL # REQ # / GN T # Interrupts
CardBus(SD)
1394
LAN(10/100)
Mini-PCI(WLAN/TV-Tuner)
AD20
AD16 0
AD17
AD18
2
3
1
PIRQA/PIRQB
PIRQE
PIRQF
PIRQG/PORQH
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
BTO Option Table
BTO Item BOM Structure
UMA's DVI 7307@
LAN(10/100)
LAN(GIGA)
MINI CARD1
MINI CARD2
SATA-to-IDE 8040@
PATA PATA@
GRAPEVINE
4401@
5789@
MINI1@
MINI2@
GRA@
MEDIA/B MEDIA@
EC SM Bus1 address
3 3
Device
Smart Battery
EEPROM(24C16/02)
GMT G781-1
Address Address
1010 000X b
1001 101X b
EC SM Bus2 address
Device
Fintek F75383M
1001 100X b0001 011X b
SKU ID Table
SKU ID
0
1
2
3
SKU
GM
4
5
ICH7M SM Bus address
Device
Clock Generator
(ICS9LPRS325AKLFT_MLF72)
DDR DIMM0
DDR DIMM2
4 4
Address
1101 001Xb
1001 000Xb
1001 010Xb
6
7
CIR CIR@
FIR FIR@
GENEVA
GEN@
LCM LCM@
TVOUT TVOUT@
1394
6311S@
CARDREADER 4IN1@
Sub-woofer SUB@
5789&5787 8789@
4401&5789 0189@
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
Notes List
HBL51 LA-3081P
E
347Wednesday, November 09, 2005
0.2
of
5
4
3
2
1
H_A#[3..31](6)
D D
H_REQ#[0..4](6)
C C
H_RS#[0..2](6)
B B
A A
H_A#[3..31]
H_REQ#[0..4]
H_ADSTB#0(6)
H_ADSTB#1(6)
CLK_CPU_BCLK(14)
CLK_CPU_BCLK#(14)
H_ADS#(6)
H_BNR#(6)
H_BPRI#(6)
H_BR0#(6)
H_DEFER#(6)
H_DRDY#(6)
H_HIT#(6)
H_HITM#(6)
H_LOCK#(6)
H_RESET#(6)
H_RS#[0..2]
H_TRDY#(6)
PAD
T5
PAD
T3
PAD
T1
PAD
T4
ITP_DBRESET#(20)
H_DBSY#(6)
H_DPSLP#(19)
H_DPRSTP#(19,47)
H_DPWR#(6)
PAD
T2
H_PWRGOOD(19)
H_CPUSLP#(6)
H_THERMTRIP#(6,19)
Layout Note:
THERMDA & THERMDC Trace / Space = 10 / 10 mil
5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_IERR#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_DBRRESET#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#
H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
THERMDA
THERMDC
JP18A
J4
A3#
L4
A4#
M3
A5#
K5
A6#
M1
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L1
A13#
P4
A14#
P1
A15#
R1
A16#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U2
A23#
R4
A24#
T5
ADDR GROUP
A25#
T3
A26#
W3
A27#
W5
A28#
Y4
A29#
W2
A30#
Y1
A31#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L5
REQ4#
L2
ADSTB0#
V4
ADSTB1#
A22
BCLK0
A21
H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1
F3
F4
G3
G2
AD4
AD3
AD1
AC4
C20
E1
B5
E5
D24
AC2
AC1
D21
D6
D7
AC5
AA6
AB3
C26
D25
AB5
AB6
A24
A25
C7
HOST CLK
BCLK1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
CONTROL
HITM#
IERR#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
THERMAL
THERMDA
DIODE
THERMDC
THERMTRIP#
FOX_PZ47903-2741-42_YONAH
4
YONAH
MISC
DATA GROUP
LEGACY CPU
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
H_D#1
F24
H_D#2
E26
H_D#3
H22
H_D#4
F23
H_D#5
G25
H_D#6
E25
H_D#7
E23
H_D#8
K24
H_D#9
G24
H_D#10
J24
H_D#11
J23
H_D#12
H26
H_D#13
F26
H_D#14
K22
H_D#15
H25
H_D#16
N22
H_D#17
K25
H_D#18
P26
H_D#19
R23
H_D#20
L25
H_D#21
L22
H_D#22
L23
H_D#23
M23
H_D#24
P25
H_D#25
P22
H_D#26
P23
H_D#27
T24
H_D#28
R24
H_D#29
L26
H_D#30
T25
H_D#31
N24
H_D#32
AA23
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
W25
H_D#37
U23
H_D#38
U25
H_D#39
U22
H_D#40
AB25
H_D#41
W22
H_D#42
Y23
H_D#43
AA26
H_D#44
Y26
H_D#45
Y22
H_D#46
AC26
H_D#47
AA24
H_D#48
AC22
H_D#49
AC23
H_D#50
AB22
H_D#51
AA21
H_D#52
AB21
H_D#53
AC25
H_D#54
AD20
H_D#55
AE22
H_D#56
AF23
H_D#57
AD24
H_D#58
AE21
H_D#59
AD21
H_D#60
AE25
H_D#61
AF25
H_D#62
AF22
H_D#63
AF26
J26
M26
V23
AC20
H23
M24
W24
AD23
G22
N25
Y25
AE24
A6
A5
C4
B3
C6
B4
D5
A3
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
H_DINV#0 (6)
H_DINV#1 (6)
H_DINV#2 (6)
H_DINV#3 (6)
H_DSTBN#0 (6)
H_DSTBN#1 (6)
H_DSTBN#2 (6)
H_DSTBN#3 (6)
H_DSTBP#0 (6)
H_DSTBP#1 (6)
H_DSTBP#2 (6)
H_DSTBP#3 (6)
H_A20M# (19)
H_FERR# (19)
H_IGNNE# (19)
H_INIT# (19)
H_INTR (19)
H_NMI (19)
H_STPCLK# (19)
H_SMI# (19)
3
2005/06/20 2006/06/20
H_D#0
E22
H_D#[0..63]
Compal Secret Data
Deciphered Date
H_D#[0..63] (6)
2200P_0402_50V7K
C625
+3VS
C624
0.1U_0402_16V4Z
1 2
ITP_TCK
U37
1
VDD
2
D+
3
DTHERM#4GND
ADM1032ARMZ-2REEL_MSOP8
F75383M_MSOP8
R15 56_0402_5%
R17 56_0402_5%
R16 56_0402_5%
R500 75_0402_5%
R18 56_0402_5%
R501 56_0402_5%
R19 56_0402_5%
R20 56_0402_5%
R513 1K_0402_5%@
R512 51_0402_5%
Title
Size Document Number Rev
Custom
Date: Sheet
8
SCLK
7
SDATA
6
ALERT#
5
12
12
12
12
12
12
12
12
12
12
HBL51 LA-3081P
EC_SMB_CK2 (32)
EC_SMB_DA2 (32)
+1.05VS
Compal Electronics, Inc.
Yonah (1/2)
447Wednesday, November 09, 2005
1
0.2
of
1
THERMDA
2
THERMDC
ITP_TDI
ITP_TDO
ITP_TMS
H_PROCHOT#
ITP_BPM#5
H_IERR#
ITP_TRST#
TEST1
TEST2
2
5
Layout Note:
Route VCCSENSE and VSSSENSE traces at 27.4Ohms
with 50 mil spacing.
Place PU and PD wihin 1 inch of CPU.
+CPU_CORE
D D
+1.5VS
10U_0805_10V4Z
C C
R510 2K_0402_1%
VCCSENSE(47)
R499 100_0402_1%
1 2
R498 100_0402_1%
1 2
VSSSENSE(47)
20mils
1
1
2
+1.05VS
C626
0.01U_0402_16V7K
2
12
PSI#(47)
CPU_VID0(47)
CPU_VID1(47)
CPU_VID2(47)
CPU_VID3(47)
CPU_VID4(47)
CPU_VID5(47)
CPU_VID6(47)
CPU_BSEL0(14)
CPU_BSEL1(14)
CPU_BSEL2(14)
+CPU_CORE
C628
Layout Note:
Place C14 near Pin B26
R511
1K_0402_1%
1 2
+1.05VS
VCCSENSE
VSSSENSE
GTL_REF0
COMP0
COMP1
COMP2
COMP3
BSEL2 B SEL1 BSEL0 BCLK
01
01
B B
0
R515 27.4_0402_1%
1 2
R514 54.9_0402_1%
1 2
R13 27.4_0402_1%
1 2
R14 54.9_0402_1%
1 2
133
166
1
COMP0
COMP1
COMP2
COMP3
JP18B
AF7
VCCSENSE
AE7
VSSSENSE
B26
VCCA
K6
VCCP
J6
VCCP
M6
VCCP
N6
VCCP
T6
VCCP
R6
VCCP
K21
VCCP
J21
VCCP
M21
VCCP
N21
VCCP
T21
VCCP
R21
VCCP
V21
VCCP
W21
VCCP
V6
VCCP
G21
VCCP
AE6
PSI#
AD6
VID0
AF5
VID1
AE5
VID2
AF4
VID3
AE3
VID4
AF2
VID5
AE2
VID6
AD26
GTLREF
B22
BSEL0
B23
BSEL1
C21
BSEL2
R26
COMP0
U26
COMP1
U1
COMP2
V1
COMP3
E7
VCC
AB20
VCC
AA20
VCC
AF20
VCC
AE20
VCC
AB18
VCC
AB17
VCC
AA18
VCC
AA17
VCC
AD18
VCC
AD17
VCC
AC18
VCC
AC17
VCC
AF18
VCC
AF17
VCC
D2
RSVD
F6
RSVD
D3
RSVD
C1
RSVD
AF1
RSVD
D22
RSVD
C23
RSVD
C24
RSVD
AA1
RSVD
AA4
RSVD
AB2
RSVD
AA3
RSVD
M4
RSVD
N5
RSVD
T2
RSVD
V3
RSVD
B2
RSVD
C3
RSVD
T22
RSVD
B25
RSVD
FOX_PZ47903-2741-42_YONAH
TRACE CLOSELY CPU < 0.5'
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)
COMP1, COMP3 layout : Space 25mils (55Ohms)
4
YONAH
POWER, GROUNG, RESERVED SIGNALS AND NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1
+CPU_CORE
1
2
22U_0805_6.3V6M
+CPU_CORE
1
2
22U_0805_6.3V6M
+CPU_CORE
1
2
22U_0805_6.3V6M
+CPU_CORE
1
2
22U_0805_6.3V6M
C13
220U_D2_2VMR15
3
+CPU_CORE
2005/11/02
1
+
2
3 x 330uF(9mOhm/3)
@
C614
330U_D2E_2.5VM_R9
South Side Secondary
+CPU_CORE
1
+
2
3 x 330uF(9mOhm/3)
2005/11/02
C620
330U_D2E_2.5VM_R9
North Side Secondary
22U_0805_6.3V6M
1
C31
C623
C611
C21
C33
2
22U_0805_6.3V6M
(Place these capacitors on South side,Secondary Layer)
22U_0805_6.3V6M
1
C618
2
22U_0805_6.3V6M
(Place these capacitors on South side,Secondary Layer)
22U_0805_6.3V6M
1
C607
2
22U_0805_6.3V6M
(Place these capacitors on North side,Secondary Layer)
22U_0805_6.3V6M
1
C19
2
22U_0805_6.3V6M
+CPU-CORE
Decoupling
SPCAP,Polymer
MLCC 0805 X5R
+1.05VS
0.1U_0402_16V4Z
1
1
+
2
C34
2
22U_0805_6.3V6M
1
C35
2
22U_0805_6.3V6M
1
C616
2
22U_0805_6.3V6M
1
C29
2
22U_0805_6.3V6M
1
C622
2
(Place these capacitors on North side,Secondary Layer)
C,uF ESR, mohm ESL,nH
6X330uF 9m ohm/6 1.8nH/6
32X22uF 3m ohm/32 0.6nH/32
0.1U_0402_16V4Z
1
1
C38
C36
2
2
0.1U_0402_16V4Z
1
+
C609
330U_D2E_2.5VM_R9
2
2005/11/02
1
+
C608
@
330U_D2E_2.5VM_R9
2
1
C32
2
22U_0805_6.3V6M
1
C613
2
22U_0805_6.3V6M
1
C27
2
22U_0805_6.3V6M
1
C617
2
22U_0805_6.3V6M
0.1U_0402_16V4Z
1
C37
2
0.1U_0402_16V4Z
22U_0805_6.3V6M
1
C30
2
22U_0805_6.3V6M
1
C22
2
22U_0805_6.3V6M
1
C25
2
22U_0805_6.3V6M
1
C615
2
1
C16
2
1
+
C621
330U_D2E_2.5VM_R9
2
1
+
C619
330U_D2E_2.5VM_R9
2
1
C28
2
22U_0805_6.3V6M
1
C20
2
1
C23
2
1
C612
2
22U_0805_6.3V6M
0.1U_0402_16V4Z
1
C18
2
0.1U_0402_16V4Z
1
C17
@
2
22U_0805_6.3V6M
1
C26
2
22U_0805_6.3V6M
1
C610
2
1
C15
@
2
0.1U_0402_16V4Z
2
+CPU_CORE
1
C24
2
1
C606
2
JP18C
AE18
VCC
AE17
VCC
AB15
VCC
AA15
VCC
AD15
VCC
AC15
VCC
AF15
VCC
AE15
VCC
AB14
VCC
AA13
VCC
AD14
VCC
AC13
VCC
AF14
VCC
AE13
VCC
AB12
VCC
AA12
VCC
AD12
VCC
AC12
VCC
AF12
VCC
AE12
VCC
AB10
VCC
AB9
VCC
AA10
VCC
AA9
VCC
AD10
VCC
AD9
VCC
AC10
VCC
AC9
VCC
AF10
VCC
AF9
VCC
AE10
POWER, GROUND
VCC
AE9
VCC
AB7
VCC
AA7
VCC
AD7
VCC
AC7
VCC
B20
VCC
A20
VCC
F20
VCC
E20
VCC
B18
VCC
B17
VCC
A18
VCC
A17
VCC
D18
VCC
D17
VCC
C18
VCC
C17
VCC
F18
VCC
F17
VCC
E18
VCC
E17
VCC
B15
VCC
A15
VCC
D15
VCC
C15
VCC
F15
VCC
E15
VCC
B14
VCC
A13
VCC
D14
VCC
C13
VCC
F14
VCC
E13
VCC
B12
VCC
A12
VCC
D12
VCC
C12
VCC
F12
VCC
E12
VCC
B10
VCC
B9
VCC
A10
VCC
A9
VCC
D10
VCC
D9
VCC
C10
VCC
C9
VCC
F10
VCC
F9
VCC
E10
VCC
E9
VCC
B7
VCC
A7
VCC
F7
VCC
FOX_PZ47903-2741-42_YONAH
YONAH
1
K1
VSS
J2
VSS
M2
VSS
N1
VSS
T1
VSS
R2
VSS
V2
VSS
W1
VSS
A26
VSS
D26
VSS
C25
VSS
F25
VSS
B24
VSS
A23
VSS
D23
VSS
E24
VSS
B21
VSS
C22
VSS
F22
VSS
E21
VSS
B19
VSS
A19
VSS
D19
VSS
C19
VSS
F19
VSS
E19
VSS
B16
VSS
A16
VSS
D16
VSS
C16
VSS
F16
VSS
E16
VSS
B13
VSS
A14
VSS
D13
VSS
C14
VSS
F13
VSS
E14
VSS
B11
VSS
A11
VSS
D11
VSS
C11
VSS
F11
VSS
E11
VSS
B8
VSS
A8
VSS
D8
VSS
C8
VSS
F8
VSS
E8
VSS
G26
VSS
K26
VSS
J25
VSS
M25
VSS
N26
VSS
T26
VSS
R25
VSS
V25
VSS
W26
VSS
H24
VSS
G23
VSS
K23
VSS
L24
VSS
P24
VSS
N23
VSS
T23
VSS
U24
VSS
Y24
VSS
W23
VSS
H21
VSS
J22
VSS
M22
VSS
L21
VSS
P21
VSS
R22
VSS
V22
VSS
U21
VSS
Y21
VSS
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Yonah (2/2)
HBL51 LA-3081P
1
547Wednesday, November 09, 2005
0.2
of
5
945GM(A-1)(QJ15)[ES2]: SA000005970
945GM(A-2)(QK44)[ES3]: SA000005980
945PM(A-2)(QK46)[ES3]: SA00000UV10
H_D#[0..63](4)
D D
C C
+1.05VS
R532
R530
B B
A A
1 2
54.9_0402_1%
1 2
54.9_0402_1%
R531
24.9_0402_1%
+1.05VS
R60
1 2
12
R53
12
100_0402_1%
200_0603_1%
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1
12
R529
24.9_0402_1%
Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.
H_VREF
1
C66
2
0.1U_0402_16V4Z
5
U40A
F1
HD0#
J1
HD1#
H1
HD2#
J6
HD3#
H3
HD4#
K2
HD5#
G1
HD6#
G2
HD7#
K9
HD8#
K1
HD9#
K7
HD10#
J8
HD11#
H4
HD12#
J3
HD13#
K11
HD14#
G4
HD15#
T10
HD16#
W11
HD17#
T3
HD18#
U7
HD19#
U9
HD20#
U11
HD21#
T11
HD22#
W9
HD23#
T1
HD24#
T8
HD25#
T4
HD26#
W7
HD27#
U5
HD28#
T9
HD29#
W6
HD30#
T5
HD31#
AB7
HD32#
AA9
HD33#
W4
HD34#
W3
HD35#
Y3
HD36#
Y7
HD37#
W5
HD38#
Y10
HD39#
AB8
HD40#
W2
HD41#
AA4
HD42#
AA7
HD43#
AA2
HD44#
AA6
HD45#
AA10
HD46#
Y8
HD47#
AA1
HD48#
AB4
HD49#
AC9
HD50#
AB11
HD51#
AC11
HD52#
AB3
HD53#
AC2
HD54#
AD1
HD55#
AD9
HD56#
AC1
HD57#
AD7
HD58#
AC6
HD59#
AB5
HD60#
AD10
HD61#
AD4
HD62#
AC8
HD63#
J13
HVREF0
K13
HVREF1
E1
HXRCOMP
E2
HXSCOMP
Y1
HYRCOMP
U1
HYSCOMP
E4
HXSWING
W1
HYSWING
CALISTOGA_FCBGA1466~D
HADSTB#0
HADSTB#1
HOST
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HCPURST#
HCPUSLP#
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HCLKN
HCLKP
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HRS0#
HRS1#
HRS2#
12
R528
R44
1 2
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
D8
G8
B8
F8
A8
B9
C13
AG1
AG2
K4
T7
Y5
AC4
K3
T6
AA5
AC5
J7
W8
U3
AB10
B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3
B4
E6
D6
221_0603_1%
100_0402_1%
4
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#
H_RS#0
H_RS#1
H_RS#2
H_SWNG0
1
C48
2
0.1U_0402_16V4Z
4
H_DSTBN#0 (4)
H_DSTBN#1 (4)
H_DSTBN#2 (4)
H_DSTBN#3 (4)
H_DSTBP#0 (4)
H_DSTBP#1 (4)
H_DSTBP#2 (4)
H_DSTBP#3 (4)
+1.05VS+1.05VS
12
R527
221_0603_1%
R526
1 2
100_0402_1%
H_A#[3..31] (4)
H_REQ#[0..4] (4)
H_ADSTB#0 (4)
H_ADSTB#1 (4)
CLK_MCH_BCLK# (14)
CLK_MCH_BCLK (14)
H_DINV#0 (4)
H_DINV#1 (4)
H_DINV#2 (4)
H_DINV#3 (4)
H_RESET# (4)
H_ADS# (4)
H_TRDY# (4)
H_DPWR# (4)
H_DRDY# (4)
H_DEFER# (4)
H_HITM# (4)
H_HIT# (4)
H_LOCK# (4)
H_BR0# (4)
H_BNR# (4)
H_BPRI# (4)
H_DBSY# (4)
H_CPUSLP# (4)
H_RS#[0..2] (4)
H_SWNG1
1
C641
2
0.1U_0402_16V4Z
3
U40B
AE35
AF39
AG35
AH39
AC35
AE39
AF35
AG39
AE37
AF41
AG37
AH41
AC37
AE41
AF37
AG41
AY35
AR1
AW7
AW40
AW35
AT1
AY7
AY40
AU20
AT20
BA29
AY29
AW13
AW12
AY21
AW21
AL20
AF10
BA13
BA12
AY20
AU21
AV9
AT9
AK1
AK41
G28
F25
H26
G6
AH33
AH34
K28
CALISTOGA_FCBGA1466~D
Deciphered Date
PAD
PAD
1
2
C46
0.1U_0402_16V4Z
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3
DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
M_OCDOCMP0
M_OCDOCMP1
SMRCOMPN
SMRCOMPP
PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
GMCH_PWROK
PLTRST_R#
+1.8V
R577
100_0402_1%
1 2
R578
100_0402_1%
1 2
Compal Secret Data
DMI_ITX_MRX_N0(20)
DMI_ITX_MRX_N1(20)
DMI_ITX_MRX_N2(20)
DMI_ITX_MRX_N3(20)
DMI_ITX_MRX_P0(20)
DMI_ITX_MRX_P1(20)
DMI_ITX_MRX_P2(20)
DMI_ITX_MRX_P3(20)
DMI_MTX_IRX_N0(20)
DMI_MTX_IRX_N1(20)
DMI_MTX_IRX_N2(20)
DMI_MTX_IRX_N3(20)
DMI_MTX_IRX_P0(20)
DMI_MTX_IRX_P1(20)
DMI_MTX_IRX_P2(20)
DMI_MTX_IRX_P3(20)
DDRA_CLK0(12)
DDRA_CLK1(12)
DDRB_CLK0(13)
DDRB_CLK1(13)
DDRA_CLK0#(12)
DDRA_CLK1#(12)
DDRB_CLK0#(13)
DDRB_CLK1#(13)
DDRA_CKE0(12)
DDRA_CKE1(12)
DDRB_CKE0(13)
DDRB_CKE1(13)
DDRA_SCS#0(12)
DDRA_SCS#1(12)
DDRB_SCS#0(13)
DDRB_SCS#1(13)
T17
T6
DDRA_ODT0(12)
DDRA_ODT1(12)
R47 80.6_0402_1%
R46 80.6_0402_1%
PLT_RST#(18,20,23,26,31,32)
3
DDRB_ODT0(13)
DDRB_ODT1(13)
1 2
1 2
SMVREF
PM_BMBUSY#(20)
PM_EXTTS#0(12,13)
H_THERMTRIP#(4,19)
1 2
R128 100_0402_1%
MCH_ICH_SYNC#(18)
Layout Note:
SMVREF trace
width and spacing
is 20/20.
SMVREF
2005/06/20 2006/06/20
+1.8V
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SM_RCOMPN
SM_RCOMPP
SM_VREF0
SM_VREF1
PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#
ICH_SYNC#
GMCH_PWROK
2
DMI
PM_DPRSLPVR(20,47)
2
DDR MUXING
PM
R127 0_0402_5%@
1 2
R130 0_0402_5%
1 2
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG
CFG17
CFG18
CFG19
CFG20
G_CLKP
G_CLKN
D_REF_CLKN
D_REF_CLKP
CLKNC
D_REF_SSCLKN
D_REF_SSCLKP
CLK_REQ#
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED
VGATE
SYS_PWROK
1 2
R121 0_0402_5%
Size Document Number Rev
Date: Sheet
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
Title
B
MCH_CLKSEL1
K18
MCH_CLKSEL2
J18
CFG3
F18
CFG4
E15
CFG5
F15
CFG6
E18
CFG7
D19
CFG8
D16
CFG9
G16
CFG10
E16
CFG11
D15
CFG12
G15
CFG13
K15
CFG14
C15
CFG15
H16
CFG16
G18
CFG17
H15
CFG18
J25
CFG19
K27
CFG20
J26
CLK_MCH_3GPLL
AG33
CLK_MCH_3GPLL#
AF33
CLK_DREF_96M#
A27
CLK_DREF_96M
A26
CLK_DREF_SSC#
C40
CLK_DREF_SSC
D41
MCH_CLKREQ#
H32
A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1
T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35
VGATE (14,20,47)
SYS_PWROK (20,35)
PM_EXTTS#0
PM_EXTTS#1
MCH_CLKSEL0
K16
1
Description at page10
MCH_CLKSEL0 (14)
MCH_CLKSEL1 (14)
MCH_CLKSEL2 (14)
PAD
T15
PAD
T8
CFG5 (10)
PAD
T14
CFG7 (10)
PAD
T11
CFG9 (10)
PAD
T12
CFG11 (10)
CFG12 (10)
CFG13 (10)
PAD
T7
PAD
T13
CFG16 (10)
PAD
T9
CFG18 (10)
CFG19 (10)
CFG20 (10)
CLK_MCH_3GPLL (14)
CLK_MCH_3GPLL# (14)
CLK_DREF_96M# (14)
CLK_DREF_96M (14)
CLK_DREF_SSC# (14)
CLK_DREF_SSC (14)
MCH_CLKREQ# (14)
R111
10K_0402_5%
1 2
R100
10K_0402_5%
1 2
+3VS
@
Compal Electronics, Inc.
Calistoga (1/6)
HBL51 LA-3081P
1
647Wednesday, November 09, 2005
0.2
of
5
4
3
2
1
DDRA_SDQ[0..63](12)
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7
DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
SA_RCVENIN#
SA_RCVENOUT#
DDRA_SMA[0..13](12)
AU12
AV14
BA20
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4
AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5
AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12
AY13
AW14
AY14
AK23
AK24
U40D
SA_BS0
SA_BS1
SA_BS2
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_WE#
SA_RCVENIN#
SA_RCVENOUT#
CALISTOGA_FCBGA1466~D
D D
DDRA_SBS0#(12)
DDRA_SBS1#(12)
DDRA_SBS2#(12)
DDRA_SDM[0..7](12) DDRB_SDM[0..7](13)
DDRA_SDQS0(12)
DDRA_SDQS1(12)
DDRA_SDQS2(12)
C C
B B
DDRA_SDQS3(12)
DDRA_SDQS4(12)
DDRA_SDQS5(12)
DDRA_SDQS6(12)
DDRA_SDQS7(12)
DDRA_SDQS0#(12)
DDRA_SDQS1#(12)
DDRA_SDQS2#(12)
DDRA_SDQS3#(12)
DDRA_SDQS4#(12)
DDRA_SDQS5#(12)
DDRA_SDQS6#(12)
DDRA_SDQS7#(12)
DDRA_SCAS#(12)
DDRA_SRAS#(12)
DDRA_SWE#(12)
PAD
T18
PAD
T19
check layout check layout
DDRA_SDQ[0..63]
DDRA_SMA[0..13]
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
DDR SYS MEMORY A
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRB_SBS0#(13)
DDRB_SBS1#(13)
DDRB_SBS2#(13)
DDRB_SDQS0(13)
DDRB_SDQS1(13)
DDRB_SDQS2(13)
DDRB_SDQS3(13)
DDRB_SDQS4(13)
DDRB_SDQS5(13)
DDRB_SDQS6(13)
DDRB_SDQS7(13)
DDRB_SDQS0#(13)
DDRB_SDQS1#(13)
DDRB_SDQS2#(13)
DDRB_SDQS3#(13)
DDRB_SDQS4#(13)
DDRB_SDQS5#(13)
DDRB_SDQS6#(13)
DDRB_SDQS7#(13)
DDRB_SCAS#(13)
DDRB_SRAS#(13)
DDRB_SWE#(13)
PAD
T10
PAD
T16
DDRB_SDQ[0..63](13)
DDRB_SMA[0..13](13)
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7
DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
SB_RCVENIN#
SB_RCVENOUT#
U40E
AT24
SB_BS0
AV23
SB_BS1
AY28
SB_BS2
AK36
SB_DM0
AR38
SB_DM1
AT36
SB_DM2
BA31
SB_DM3
AL17
SB_DM4
AH8
SB_DM5
BA5
SB_DM6
AN4
SB_DM7
AM39
SB_DQS0
AT39
SB_DQS1
AU35
SB_DQS2
AR29
SB_DQS3
AR16
SB_DQS4
AR10
SB_DQS5
AR7
SB_DQS6
AN5
SB_DQS7
AM40
SB_DQS0#
AU39
SB_DQS1#
AT35
SB_DQS2#
AP29
SB_DQS3#
AP16
SB_DQS4#
AT10
SB_DQS5#
AT7
SB_DQS6#
AP5
SB_DQS7#
AY23
SB_MA0
AW24
SB_MA1
AY24
SB_MA2
AR28
SB_MA3
AT27
SB_MA4
AT28
SB_MA5
AU27
SB_MA6
AV28
SB_MA7
AV27
SB_MA8
AW27
SB_MA9
AV24
SB_MA10
BA27
SB_MA11
AY27
SB_MA12
AR23
SB_MA13
AR24
SB_CAS#
AU23
SB_RAS#
AR27
SB_WE#
AK16
SB_RCVENIN#
AK18
SB_RCVENOUT#
CALISTOGA_FCBGA1466~D
DDRB_SDQ[0..63]
DDRB_SMA[0..13]
DDR SYS MEMORY B
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Calistoga (2/6)
HBL51 LA-3081P
1
747Wednesday, November 09, 2005
0.2
of
5
D D
4
3
2
1
U40C
TV_IREF
CRT_IREF
H27
SDVOCTRL_DATA
H28
SDVOCTRL_CLK
B37
LA_DATA0
B34
LA_DATA1
A36
LA_DATA2
C37
LA_DATA#0
B35
LA_DATA#1
A37
LA_DATA#2
F30
LB_DATA0
D29
LB_DATA1
F28
LB_DATA2
G30
LB_DATA#0
D30
LB_DATA#1
F29
LB_DATA#2
A32
LA_CLK
A33
LA_CLK#
E26
LB_CLK
E27
LB_CLK#
D32
LBKLT_CTL
J30
LBKLT_EN
H30
LCTLA_CLK
H29
LCTLB_DATA
G26
LDDC_CLK
G25
LDDC_DATA
F32
LVDD_EN
B38
LIBG
C35
LVBG
C33
LVREFH
C32
LVREFL
A16
TVDAC_A
C18
TVDAC_B
A19
TVDAC_C
J20
TV_IREF
B16
TV_IRTNA
B18
TV_IRTNB
B19
TV_IRTNC
J29
TV_DCONSEL1
K30
TV_DCONSEL0
C26
DDCCLK
C25
DDCDATA
H23
VSYNC
G23
HSYNC
E23
BLUE
D23
BLUE#
C22
GREEN
B22
GREEN#
A21
RED
B21
RED#
J22
CRT_IREF
CALISTOGA_FCBGA1466~D
EXP_COMPI
EXP_COMPO
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
LVDS
TV CRT
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
PCI-EXPRESS GRAPHICS
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
Security Classification
SDVO_SDAT(17)
SDVO_SCLK(17)
TXOUT0+(15)
TXOUT1+(15)
TXOUT2+(15)
TXOUT0-(15)
TXOUT1-(15)
TXOUT2-(15)
TZOUT0+(15)
TZOUT1+(15)
TZOUT2+(15)
TZOUT0-(15)
TZOUT1-(15)
TZOUT2-(15)
TXCLK+(15)
TXCLK-(15)
TZCLK+(15)
R567 150_0402_1%
R565 150_0402_1%
R564 150_0402_1%
I2CC_SCL
I2CC_SDA
LCTLB_DATA
LCTLA_CLK
GMCH_CRT_CLK
GMCH_CRT_DATA
TZCLK-(15)
I2CC_SCL(15)
I2CC_SDA(15)
GMCH_ENVDD(15)
12
12
12
LBKLT_EN
LIBG
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
C C
B B
A A
ENBKL(32)
R108 0_0402_5%
1 2
GMCH_TV_COMPS(16)
GMCH_TV_LUMA(16)
GMCH_TV_CRMA(16)
GMCH_CRT_CLK(16)
GMCH_CRT_DATA(16)
GMCH_CRT_VSYNC(16)
GMCH_CRT_HSYNC(16)
GMCH_CRT_B(16)
GMCH_CRT_G(16)
GMCH_CRT_R(16)
+3VS
R122 10K_0402_5%
1 2
R104 10K_0402_5%
1 2
R125 10K_0402_5%
1 2
R117 10K_0402_5%
1 2
R107 4.7K_0402_5%
1 2
R94 4.7K_0402_5%
1 2
R109 100K_0402_5%
1 2
R576 1.5K_0402_1%
1 2
R541 150_0402_1%
1 2
R544 150_0402_1%
1 2
R563 150_0402_1%
1 2
LBKLT_EN
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
GMCH_CRT_CLK
GMCH_CRT_DATA
TVOUT@
TVOUT@
TVOUT@
TXOUT0+
TXOUT1+
TXOUT2+
TXOUT0TXOUT1TXOUT2-
TZOUT0+
TZOUT1+
TZOUT2+
TZOUT0TZOUT1TZOUT2-
TXCLK+
TXCLKTZCLK+
TZCLK-
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
I2CC_SCL
I2CC_SDA
GMCH_ENVDD
LIBG
1 2
R82 4.99K_0402_1%
TVOUT@
1 2
R91 255_0402_1%
10mils
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
PEG_COMP
D40
D38
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40
10mils
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P3
2005/06/20 2006/06/20
1 2
R138 24.9_0402_1%
T32 PAD
T33 PAD
T34 PAD
T35 PAD
T36 PAD
T37 PAD
T38 PAD
T39 PAD
T40 PAD
T41 PAD
T42 PAD
T43 PAD
T44 PAD
T45 PAD
T46 PAD
T47 PAD
T48 PAD
T49 PAD
T50 PAD
T51 PAD
T52 PAD
T53 PAD
T54 PAD
T55 PAD
T56 PAD
T57 PAD
T58 PAD
T59 PAD
T60 PAD
T61 PAD
T62 PAD
T63 PAD
T64 PAD
T65 PAD
T66 PAD
T67 PAD
T68 PAD
T69 PAD
T70 PAD
T71 PAD
T72 PAD
T73 PAD
T74 PAD
T75 PAD
T76 PAD
T77 PAD
T78 PAD
T79 PAD
T80 PAD
T81 PAD
T82 PAD
T83 PAD
T84 PAD
T85 PAD
C695 0.1U_0402_16V4Z
1 2
7307@
C209 0.1U_0402_16V4Z7307@
1 2
C239 0.1U_0402_16V4Z7307@
1 2
C241 0.1U_0402_16V4Z7307@
1 2
C234 0.1U_0402_16V4Z
1 2
7307@
Compal Secret Data
Deciphered Date
+1.5VS_PCIE
C696 0.1U_0402_16V4Z7307@
1 2
C216 0.1U_0402_16V4Z7307@
1 2
C240 0.1U_0402_16V4Z7307@
1 2
C242 0.1U_0402_16V4Z7307@
1 2
C235 0.1U_0402_16V4Z7307@
1 2
2
SDVO_INT# (17)
SDVO_INT (17)
SDVOB_R# (17)
SDVOB_R (17)
SDVOB_G# (17)
SDVOB_G (17)
SDVOB_B# (17)
SDVOB_B (17)
SDVOB_CLK# (17)
SDVOB_CLK (17)
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
Calistoga (3/6)
HBL51 LA-3081P
847Wednesday, November 09, 2005
1
of
0.2
5
4
3
2
1
4.7U_0805_10V4Z
C633
R101
10_0402_5%@
1 2
R93
10_0402_5%@
1 2
+2.5VS
+1.05VS
(800mA)
1
+
C629
2
1
1
C67
2
2
2.2U_0805_10V6K
MCH_A6
1
C643
2
0.47U_0603_16V4Z
MCH_D2
1
+1.5VS
C632
MCH_AB1
1
2
0.47U_0603_16V4Z
2
0.22U_0603_16V7K
U40H
AC14
VTT0
AB14
VTT1
W14
VTT2
V14
VTT3
T14
VTT4
R14
VTT5
P14
VTT6
N14
VTT7
M14
VTT8
L14
VTT9
AD13
VTT10
AC13
VTT11
AB13
VTT12
AA13
VTT13
Y13
VTT14
W13
VTT15
V13
VTT16
U13
VTT17
T13
VTT18
R13
VTT19
N13
VTT20
M13
VTT21
L13
VTT22
AB12
VTT23
AA12
VTT24
Y12
VTT25
W12
VTT26
V12
VTT27
U12
VTT28
T12
VTT29
R12
VTT30
P12
VTT31
N12
VTT32
M12
VTT33
L12
VTT34
R11
VTT35
P11
VTT36
N11
VTT37
M11
VTT38
R10
VTT39
P10
VTT40
N10
VTT41
M10
VTT42
P9
VTT43
N9
VTT44
M9
VTT45
R8
VTT46
P8
VTT47
N8
VTT48
M8
VTT49
P7
VTT50
N7
VTT51
M7
VTT52
R6
VTT53
P6
VTT54
M6
VTT55
A6
VTT56
R5
VTT57
P5
VTT58
N5
VTT59
M5
VTT60
P4
VTT61
N4
VTT62
M4
VTT63
R3
VTT64
P3
VTT65
N3
VTT66
M3
VTT67
R2
VTT68
P2
VTT69
M2
VTT70
D2
VTT71
AB1
VTT72
R1
VTT73
P1
VTT74
N1
VTT75
M1
VTT76
AG14
VCCAUX32
AF14
VCCAUX33
AE14
VCCAUX34
Y14
VCCAUX35
AF13
VCCAUX36
AE13
VCCAUX37
AF12
VCCAUX38
AE12
VCCAUX39
AD12
VCCAUX40
CALISTOGA_FCBGA1466~D
P O W E R
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCD_HMPLL0
VCCD_HMPLL1
VCCDQ_TVDAC
4
VCC_SYNC
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_LVDS
VSSA_LVDS
VCCA_MPLL
VCCA_TVBG
VSSA_TVBG
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCD_TVDAC
VCCHV0
VCCHV1
VCCHV2
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
H22
B30
C30
A30
AB41
AJ41
L41
N41
R41
V41
Y41
AC33
G41
H41
E21
F21
G21
B26
C39
AF1
A38
B39
AF2
H20
G20
E19
F19
C20
D20
E20
F20
AH1
AH2
A28
B28
C28
D21
H19
A23
B23
B25
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14
(60mA)
(70mA)
(50mA)
(50mA)
(45mA)
(10mA)
(45mA)
(150mA)
(24mA)
1 2
C117
0.1U_0402_16V4Z
+2.5VS
W=60 mils
(1500mA)
(20mA)
(40mA)
C739
220U_D2_2VMR15
+1.5VS_3GPLL
+2.5VS
(2mA)
+2.5VS_CRTDAC
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+2.5VS
+1.5VS_MPLL
+3VS_TVBG
(120mA)
+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC
+1.5VS
+1.5VS_TVDAC
1
C111
2
0.1U_0402_16V4Z
+1.5VS
1
C68
2
+2.5VS
+1.5VS_PCIE
1
+
C712
2
1
2
1
C722
2
10U_0805_10V4Z
10U_0805_10V4Z
MBK1608301YZF_0603
1
C118
2
0.022U_0402_16V7K
1
2
C106
0_0805_5%
L8
0.1U_0402_16V4Z
C195
R580
0.01U_0402_16V7K
1
2
12
12
+2.5VS
2005/09/21
1
+
C927
220U_D2_4VM
2
+2.5VS
+1.5VS
1
C180
2
0.1U_0402_16V4Z
1
C194
2
0.1U_0402_16V4Z
close pin G41
CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Calistoga
close pin A38
+3VS+3VS_TVBG
R90
0_0603_5%
12
+3VS
1
1
C108
2
2
0.022U_0402_16V7K
C127
0.1U_0402_16V4Z
1
2
10U_0805_10V4Z
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
C109
0.1U_0402_16V4Z
2005/06/20 2006/06/20
PCI-E/MEM/PSB PLL decoupling
1
C141
2
0.1U_0402_16V4Z
+1.5VS_MPLL
45mA Max. 45mA Max.
1
C637
2
0.1U_0402_16V4Z
Compal Secret Data
Deciphered Date
+1.5VS_DPLLA +1.5VS_DPLLB
1
C683
2
0.1U_0402_16V4Z
1
C105
2
1
C93
2
R112
0_0603_5%
12
1
2
R517
0_0603_5%
2
@
12
C139
1
2
10U_0805_10V4Z
C636
10U_0805_10V4Z
L46
MBK1608301YZF_0603
1
+
C687
330U_D2E_2.5VM
2
MBK1608301YZF_0603
1
2
0.022U_0402_16V7K
MBK1608301YZF_0603
1
2
0.022U_0402_16V7K
+1.5VS+1.5VS_3GPLL
1
C140
2
0.1U_0402_16V4Z
12
L7
C92
0.1U_0402_16V4Z
L4
C107
0.1U_0402_16V4Z
+1.5VS_TVDAC +1.5VS
C119
L45
MBK1608301YZF_0603
1
1
+
C196
12
+3VS+3VS_TVDACC
12
1
1
2
2
0.1U_0402_16V4Z
+1.5VS_HPLL
1
C638
2
0.1U_0402_16V4Z
Title
Size Document Number Rev
B
Date: Sheet
C690
330U_D2E_2.5VM
2
2
0.1U_0402_16V4Z
MBK1608301YZF_0603
1
1
C84
2
2
0.022U_0402_16V7K
R568
0_0603_5%
12
C94
@
0.022U_0402_16V7K
R516
0_0603_5%
1
C631
2
10U_0805_10V4Z
Compal Electronics, Inc.
HBL51 LA-3081P
12
+3VS+3VS_TVDACA+3VS+3VS_TVDACB
L5
12
C85
0.1U_0402_16V4Z
1
C672
2
0.1U_0402_16V4Z
12
+1.5VS+1.5VS
Calistoga (4/6)
1
+1.5VS+1.5VS
1
+
C49
220U_D2_4VM
2
947Wednesday, November 09, 2005
of
0.2
D7
RB751V_SOD323@
+1.05VS +2.5VS
+1.5VS +3VS
D D
C C
B B
A A
2 1
D6
RB751V_SOD323@
2 1
220U_D2_2VMR15
C627
1
C630
2
0.22U_0603_16V7K
5
5
4
3
2
1
Strap Pin Table
CFG[3:17] have internal pull up
+1.05VS
(3500mA)
D D
1
C639
2
0.22U_0603_16V7K
1
C45
2
10U_0805_10V4Z
C C
220U_D2_2VMR15
220U_D2_2VMR15
B B
1
1
C42
C640
2
2
0.22U_0603_16V7K
0.22U_0603_16V7K
1
1
C44
C43
2
2
1U_0603_10V4Z
10U_0805_10V4Z
1
+
C41
2
1
+
C40
@
2
+1.05VS
U40F
AD27
VCC_NCTF0
AC27
VCC_NCTF1
AB27
VCC_NCTF2
AA27
VCC_NCTF3
Y27
VCC_NCTF4
W27
VCC_NCTF5
V27
VCC_NCTF6
U27
VCC_NCTF7
T27
VCC_NCTF8
R27
VCC_NCTF9
AD26
VCC_NCTF10
AC26
VCC_NCTF11
AB26
VCC_NCTF12
AA26
VCC_NCTF13
Y26
VCC_NCTF14
W26
VCC_NCTF15
V26
VCC_NCTF16
U26
VCC_NCTF17
T26
VCC_NCTF18
R26
VCC_NCTF19
AD25
VCC_NCTF20
AC25
VCC_NCTF21
AB25
VCC_NCTF22
AA25
VCC_NCTF23
Y25
VCC_NCTF24
W25
VCC_NCTF25
V25
VCC_NCTF26
U25
VCC_NCTF27
T25
VCC_NCTF28
R25
VCC_NCTF29
AD24
VCC_NCTF30
AC24
VCC_NCTF31
AB24
VCC_NCTF32
AA24
VCC_NCTF33
Y24
VCC_NCTF34
W24
VCC_NCTF35
V24
VCC_NCTF36
U24
VCC_NCTF37
T24
VCC_NCTF38
R24
VCC_NCTF39
AD23
VCC_NCTF40
V23
VCC_NCTF41
U23
VCC_NCTF42
T23
VCC_NCTF43
R23
VCC_NCTF44
AD22
VCC_NCTF45
V22
VCC_NCTF46
U22
VCC_NCTF47
T22
VCC_NCTF48
R22
VCC_NCTF49
AD21
VCC_NCTF50
V21
VCC_NCTF51
U21
VCC_NCTF52
T21
VCC_NCTF53
R21
VCC_NCTF54
AD20
VCC_NCTF55
V20
VCC_NCTF56
U20
VCC_NCTF57
T20
VCC_NCTF58
R20
VCC_NCTF59
AD19
VCC_NCTF60
V19
VCC_NCTF61
U19
VCC_NCTF62
T19
VCC_NCTF63
AD18
VCC_NCTF64
AC18
VCC_NCTF65
AB18
VCC_NCTF66
AA18
VCC_NCTF67
Y18
VCC_NCTF68
W18
VCC_NCTF69
V18
VCC_NCTF70
U18
VCC_NCTF71
T18
VCC_NCTF72
M19
VCC100
L19
VCC101
N18
VCC102
M18
VCC103
L18
VCC104
P17
VCC105
N17
VCC106
M17
VCC107
N16
VCC108
M16
VCC109
L16
VCC110
CALISTOGA_FCBGA1466~D
VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
P O W E R
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107
AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
+1.5VS
MCH_AV1
MCH_AJ1
+1.8V
1
1
C634
C635
2
2
0.47U_0603_16V4Z
0.47U_0603_16V4Z
Place near pin AV1 & AJ1
A A
+1.05VS
U40G
AA33
VCC0
W33
VCC1
P33
VCC2
N33
VCC3
L33
VCC4
J33
VCC5
AA32
VCC6
Y32
VCC7
W32
VCC8
V32
VCC9
P32
VCC10
N32
VCC11
M32
VCC12
L32
VCC13
J32
VCC14
AA31
VCC15
W31
VCC16
V31
VCC17
T31
VCC18
R31
VCC19
P31
VCC20
N31
VCC21
M31
VCC22
AA30
VCC23
Y30
VCC24
W30
VCC25
V30
VCC26
U30
VCC27
T30
VCC28
R30
VCC29
P30
VCC30
N30
VCC31
M30
VCC32
L30
VCC33
AA29
VCC34
Y29
VCC35
W29
VCC36
V29
VCC37
U29
VCC38
R29
VCC39
P29
VCC40
M29
VCC41
L29
VCC42
AB28
VCC43
AA28
VCC44
Y28
VCC45
V28
VCC46
U28
VCC47
T28
VCC48
R28
VCC49
P28
VCC50
N28
VCC51
M28
VCC52
L28
VCC53
P27
VCC54
N27
VCC55
M27
VCC56
L27
VCC57
P26
VCC58
N26
VCC59
L26
VCC60
N25
VCC61
M25
VCC62
L25
VCC63
P24
VCC64
N24
VCC65
M24
VCC66
AB23
VCC67
AA23
VCC68
Y23
VCC69
P23
VCC70
N23
VCC71
M23
VCC72
L23
VCC73
AC22
VCC74
AB22
VCC75
Y22
VCC76
W22
VCC77
P22
VCC78
N22
VCC79
M22
VCC80
L22
VCC81
AC21
VCC82
AA21
VCC83
W21
VCC84
N21
VCC85
M21
VCC86
L21
VCC87
AC20
VCC88
AB20
VCC89
Y20
VCC90
W20
VCC91
P20
VCC92
N20
VCC93
M20
VCC94
L20
VCC95
AB19
VCC96
AA19
VCC97
Y19
VCC98
N19
VCC99
CALISTOGA_FCBGA1466~D
P O W E R
VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99
AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
+1.8V
MCH_AT41
MCH_AM41
1
1
C718
C717
2
2
0.47U_0603_16V4Z
0.47U_0603_16V4Z
Place near pin AT41 & AM41
1
1
C75
2
2
0.1U_0402_16V4Z
1
C679
2
0.47U_0603_16V4Z
Place near pin BA23
1
1
C720
C719
2
2
10U_0805_10V4Z
10U_0805_10V4Z
1
C650
2
0.47U_0603_16V4Z
Place near pin BA15
CFG[2:0]
CFG5
CFG7
CFG9
CFG11
PSB 4X CLK Enable 1 = Calistoga
CFG[13:12]
CFG16
1
1
C86
C121
2
0.1U_0402_16V4Z
C129
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CFG18
CFG19
SDVO_CTRLDATA
CFG20
(PCIE/SDVO select)
1
+
C735
220U_D2_4VM
2
CFG[19:18] have internal pull down
011 = 667MT/s FSB
001 = 533MT/s FSB
0 = DMI x 2
1 = DMI x 4
0 = Reserved
1 = Mobile Yonah CPU
0 = Lane Reversal Enable
1 = Normal Operation
(Default)
*
(Default)
*
(Default)
*
0 = Reserved
*
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)
0 = 1.05V
1 = 1.5V
0 = Normal Operation
1 = DMI Lane Reversal Enable
0 = No SDVO Device Present
*
(Default)
(Default)
1 = SDVO Device Present
0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.
R58 2.2K_0402_5%@
CFG5(6)
R81 2.2K_0402_5%@
CFG7(6)
R67 2.2K_0402_5%@
CFG9(6)
CFG11(6)
CFG12(6)
CFG13(6)
CFG16(6)
CFG18(6)
CFG19(6)
CFG20(6)
R57 2.2K_0402_5%@
R59 2.2K_0402_5%@
R69 2.2K_0402_5%@
R68 2.2K_0402_5%@
R92 1K_0402_5%@
R95 1K_0402_5%@
R118 1K_0402_5%@
*
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
*
*
(Default)
(Default)
*
(Default)
*
+3VS
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Calistoga (5/6)
HBL51 LA-3081P
10 47Wednesday, November 09, 2005
1
0.2
of
5
4
3
2
1
U40I
AC41
VSS0
AA41
VSS1
W41
VSS2
T41
VSS3
P41
VSS4
M41
D D
C C
B B
A A
VSS5
J41
VSS6
F41
VSS7
AV40
VSS8
AP40
VSS9
AN40
VSS10
AK40
VSS11
AJ40
VSS12
AH40
VSS13
AG40
VSS14
AF40
VSS15
AE40
VSS16
B40
VSS17
AY39
VSS18
AW39
VSS19
AV39
VSS20
AR39
VSS21
AN39
VSS22
AJ39
VSS23
AC39
VSS24
AB39
VSS25
AA39
VSS26
Y39
VSS27
W39
VSS28
V39
VSS29
T39
VSS30
R39
VSS31
P39
VSS32
N39
VSS33
M39
VSS34
L39
VSS35
J39
VSS36
H39
VSS37
G39
VSS38
F39
VSS39
D39
VSS40
AT38
VSS41
AM38
VSS42
AH38
VSS43
AG38
VSS44
AF38
VSS45
AE38
VSS46
C38
VSS47
AK37
VSS48
AH37
VSS49
AB37
VSS50
AA37
VSS51
Y37
VSS52
W37
VSS53
V37
VSS54
T37
VSS55
R37
VSS56
P37
VSS57
N37
VSS58
M37
VSS59
L37
VSS60
J37
VSS61
H37
VSS62
G37
VSS63
F37
VSS64
D37
VSS65
AY36
VSS66
AW36
VSS67
AN36
VSS68
AH36
VSS69
AG36
VSS70
AF36
VSS71
AE36
VSS72
AC36
VSS73
C36
VSS74
B36
VSS75
BA35
VSS76
AV35
VSS77
AR35
VSS78
AH35
VSS79
AB35
VSS80
AA35
VSS81
Y35
VSS82
W35
VSS83
V35
VSS84
T35
VSS85
R35
VSS86
P35
VSS87
N35
VSS88
M35
VSS89
L35
VSS90
J35
VSS91
H35
VSS92
G35
VSS93
F35
VSS94
D35
VSS95
AN34
VSS96
AK34
VSS97
AG34
VSS98
AF34
VSS99
CALISTOGA_FCBGA1466~D
P O W E R
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
U40J
AN21
VSS200
AL21
VSS201
AB21
VSS202
Y21
VSS203
P21
VSS204
K21
VSS205
J21
VSS206
H21
VSS207
C21
VSS208
AW20
VSS209
AR20
VSS210
AM20
VSS211
AA20
VSS212
K20
VSS213
B20
VSS214
A20
VSS215
AN19
VSS216
AC19
VSS217
W19
VSS218
K19
VSS219
G19
VSS220
C19
VSS221
AH18
VSS222
P18
VSS223
H18
VSS224
D18
VSS225
A18
VSS226
AY17
VSS227
AR17
VSS228
AP17
VSS229
AM17
VSS230
AK17
VSS231
AV16
VSS232
AN16
VSS233
AL16
VSS234
J16
VSS235
F16
VSS236
C16
VSS237
AN15
VSS238
AM15
VSS239
AK15
VSS240
N15
VSS241
M15
VSS242
L15
VSS243
B15
VSS244
A15
VSS245
BA14
VSS246
AT14
VSS247
AK14
VSS248
AD14
VSS249
AA14
VSS250
U14
VSS251
K14
VSS252
H14
VSS253
E14
VSS254
AV13
VSS255
AR13
VSS256
AN13
VSS257
AM13
VSS258
AL13
VSS259
AG13
VSS260
P13
VSS261
F13
VSS262
D13
VSS265
B13
VSS264
AY12
VSS263
AC12
VSS266
K12
VSS267
H12
VSS268
E12
VSS269
AD11
VSS270
AA11
VSS271
Y11
VSS272
J11
VSS273
D11
VSS274
B11
VSS275
AV10
VSS276
AP10
VSS277
AL10
VSS278
AJ10
VSS279
CALISTOGA_FCBGA1466~D
P O W E R
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
Calistoga (6/6)
HBL51 LA-3081P
11 47Wednesday, November 09, 2005
1
0.2
of
5
+DIMM_VREF
DDRA_SDQ4 DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQS0#(7)
DDRA_SDQS0(7)
D D
DDRA_SDQS1#(7)
DDRA_SDQS1(7)
DDRA_SDQS2#(7)
DDRA_SDQS2(7)
DDRA_CKE0(6)
C C
DDRA_SBS2#(7)
DDRA_SBS0#(7)
DDRA_SWE#(7)
DDRA_SCAS#(7)
DDRA_SCS#1(6)
DDRA_ODT1(6)
DDRA_SDQS4#(7)
DDRA_SDQS4(7)
B B
DDRA_SDQS6#(7)
DDRA_SDQS6(7)
D_CK_SDATA(13,14)
D_CK_SCLK(13,14)
A A
DDRA_SDQS0#
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ8
DDRA_SDQ14
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQ9
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ29
DDRA_SDQ24 DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
DDRA_SCS#1
DDRA_ODT1
DDRA_SDQ37
DDRA_SDQ36
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ35
DDRA_SDQ32
DDRA_SDQ40
DDRA_SDQ44
DDRA_SDM5
DDRA_SDQ41
DDRA_SDQ46
DDRA_SDQ49
DDRA_SDQ48
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ54
DDRA_SDQ50
DDRA_SDQ61
DDRA_SDM7
DDRA_SDQ59
DDRA_SDQ58
D_CK_SDATA
D_CK_SCLK
+3VS
+1.8V +1.8V
JP22
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203
P-TWO_A5692A-A0G16-N
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND1
***
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
BA1
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
SA1
204
DIMM0 STD H:9.2mm (BOT)
4
DDRA_SDQ6
DDRA_SDM0
DDRA_SDQ5
DDRA_SDQ7
DDRA_SDQ13
DDRA_SDQ12
DDRA_SDM1
DDRA_SDQ11
DDRA_SDQ10
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ23
DDRA_SDQ22
DDRA_SDQ28
DDRA_SDQS3#
DDRA_SDQS3
DDRA_SDQ31
DDRA_SDQ30
DDRA_CKE1DDRA_CKE0
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS#0
DDRA_ODT0
DDRA_SMA13
DDRA_SDQ39
DDRA_SDQ38
DDRA_SDM4
DDRA_SDQ34
DDRA_SDQ33
DDRA_SDQ45
DDRA_SDQ43
DDRA_SDQS5#
DDRA_SDQS5
DDRA_SDQ47
DDRA_SDQ42
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ51
DDRA_SDQ55
DDRA_SDQ57DDRA_SDQ60
DDRA_SDQ56
DDRA_SDQS7#
DDRA_SDQS7
DDRA_SDQ62
DDRA_SDQ63
R23 10K_0402_5%
1 2
R21 10K_0402_5%
1 2
R119
DDRA_CLK0 (6)
DDRA_CLK0# (6)
0_0402_5%
1 2
DDRA_CKE1 (6)
DDRA_SBS1# (7)
DDRA_SRAS# (7)
DDRA_SCS#0 (6)
DDRA_ODT0 (6)
DDRA_CLK1 (6)
DDRA_CLK1# (6)
DDRA_SDQS3# (7)
DDRA_SDQS3 (7)
DDRA_SDQS5# (7)
DDRA_SDQS5 (7)
DDRA_SDQS7# (7)
DDRA_SDQS7 (7)
PM_EXTTS#0 (6,13)
3
+DIMM_VREF
DDRA_SMA[0..13](7)
DDRA_SDQ[0..63](7)
DDRA_SDM[0..7](7)
DDRA_CKE0
DDRA_SBS2#
RP41 56_0404_4P2R_5%
DDRA_SMA12
DDRA_SMA9
RP39 56_0404_4P2R_5%
DDRA_SMA8
DDRA_SMA5
RP37 56_0404_4P2R_5%
DDRA_SMA3
DDRA_SMA1
RP35 56_0404_4P2R_5%
DDRA_SMA10
DDRA_SBS0#
RP33 56_0404_4P2R_5%
DDRA_SWE#
DDRA_SCAS#
RP31 56_0404_4P2R_5%
DDRA_SCS#1
DDRA_ODT1
RP29 56_0404_4P2R_5%
DDRA_CKE1
DDRA_SMA11
RP12 56_0404_4P2R_5%
DDRA_SMA7
DDRA_SMA6
RP10 56_0404_4P2R_5%
DDRA_SMA4
DDRA_SMA2
RP8 56_0404_4P2R_5%
DDRA_SMA0
DDRA_SBS1#
RP6 56_0404_4P2R_5%
DDRA_SRAS#
DDRA_SCS#0
RP4 56_0404_4P2R_5%
DDRA_ODT0
DDRA_SMA13
RP2 56_0404_4P2R_5%
20mils
1
C281
0.1U_0402_16V4Z
2
DDRA_SMA[0..13]
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1
C294
2.2U_0805_10V6K
2
+0.9VS
+1.8V
12
12
R153
1K_0402_1%
R156
1K_0402_1%
2
+1.8V
1
C71
2.2U_0805_10V6K
2
+1.8V
1
C115
0.1U_0402_16V4Z
2
+0.9VS
1
C645
0.1U_0402_16V4Z
2
+0.9VS
1
C671
0.1U_0402_16V4Z
2
+0.9VS
1
C80
0.1U_0402_16V4Z
2
1
1
C53
2.2U_0805_10V6K
2
1
C113
0.1U_0402_16V4Z
2
1
C648
0.1U_0402_16V4Z
2
1
C678
0.1U_0402_16V4Z
2
1
C88
0.1U_0402_16V4Z
2
1
C123
2.2U_0805_10V6K
2
1
C62
0.1U_0402_16V4Z
2
1
C653
0.1U_0402_16V4Z
2
1
C104
0.1U_0402_16V4Z
2
1
C95
0.1U_0402_16V4Z
2
1
C125
2.2U_0805_10V6K
2
1
C63
0.1U_0402_16V4Z
2
1
C660
0.1U_0402_16V4Z
2
1
C69
0.1U_0402_16V4Z
2
1
C54
2.2U_0805_10V6K
2
1
C667
0.1U_0402_16V4Z
2
1
C76
0.1U_0402_16V4Z
2
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
DDRII-SODIMM0
HBL51 LA-3081P
1
12 47Wednesday, November 09, 2005
0.2
of
A
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND1
***
NC/CKE1
NC/A15
NC/A14
NC/A13
JP21
+DIMM_VREF
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQS0#(7)
DDRB_SDQS0(7)
1 1
DDRB_SDQS1#(7)
DDRB_SDQS1(7)
DDRB_SDQS2#(7)
DDRB_SDQS2(7)
DDRB_CKE0(6)
2 2
DDRB_SBS2#(7)
DDRB_SBS0#(7)
DDRB_SWE#(7)
DDRB_SCAS#(7)
DDRB_SCS#1(6)
DDRB_ODT1(6)
DDRB_SDQS4#(7)
DDRB_SDQS4(7)
3 3
DDRB_SDQS6#(7)
DDRB_SDQS6(7)
D_CK_SDATA(12,14)
D_CK_SCLK(12,14)
4 4
DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ17
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ28
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ30 DDRB_SDQ29
DDRB_SDQ31
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS#1
DDRB_ODT1
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ51
DDRB_SDQ50
DDRB_SDQ56
DDRB_SDM7
DDRB_SDQ59
DDRB_SDQ58
D_CK_SDATA
D_CK_SCLK
+3VS
DIMM1 STD H:5.2mm (BOT)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203
P-TWO_A5652C-A0G16
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
VDD
VDD
A11
VDD
VDD
BA1
RAS#
S0#
VDD
ODT0
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND2
+1.8V+1.8V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204
B
DDRB_SDQ5
DDRB_SDQ4
DDRB_SDM0
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDM1
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ21
DDRB_SDQ16DDRB_SDQ20
R120
DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ26
DDRB_SDQ24
DDRB_SDQS3#
DDRB_SDQS3
DDRB_SDQ27
DDRB_CKE1
DDRB_SMA11
DDRB_SMA7
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS#0
DDRB_ODT0
DDRB_SMA13
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDM4
DDRB_SDQ39
DDRB_SDQ38
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ57DDRB_SDQ61
DDRB_SDQS7#
DDRB_SDQS7
DDRB_SDQ62
DDRB_SDQ63
1 2
R24 10K_0402_5%
1 2
R22 10K_0402_5%
1 2
DDRB_CLK1 (6)
DDRB_CLK1# (6)
0_0402_5%
DDRB_SDQS3# (7)
DDRB_SDQS3 (7)
DDRB_CKE1 (6)
DDRB_SBS1# (7)
DDRB_SRAS# (7)
DDRB_SCS#0 (6)
DDRB_ODT0 (6)
DDRB_SDQS5# (7)
DDRB_SDQS5 (7)
DDRB_CLK0 (6)
DDRB_CLK0# (6)
DDRB_SDQS7# (7)
DDRB_SDQS7 (7)
+3VS
PM_EXTTS#0 (6,12)
DDRB_SMA[0..13](7)
DDRB_SDQ[0..63](7)
DDRB_SDM[0..7](7)
C
1
C263
2.2U_0805_10V6K
2
DDRB_SBS2#
DDRB_CKE0
DDRB_SMA9
DDRB_SMA12
DDRB_SMA5
DDRB_SMA8
DDRB_SMA1
DDRB_SMA3
DDRB_SBS0#
DDRB_SMA10
DDRB_SCAS#
DDRB_SWE#
DDRB_ODT1
DDRB_SCS#1
DDRB_CKE1
DDRB_SMA11
DDRB_SMA7
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS#0
DDRB_ODT0
DDRB_SMA13
1
C276
2
0.1U_0402_16V4Z
DDRB_SMA[0..13]
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
1 4
2 3
RP13 56_0404_4P2R_5%
1 4
2 3
RP11 56_0404_4P2R_5%
1 4
2 3
RP9 56_0404_4P2R_5%
1 4
2 3
RP7 56_0404_4P2R_5%
1 4
2 3
RP5 56_0404_4P2R_5%
1 4
2 3
RP3 56_0404_4P2R_5%
1 4
2 3
RP1 56_0404_4P2R_5%
1 4
2 3
RP40 56_0404_4P2R_5%
1 4
2 3
RP38 56_0404_4P2R_5%
1 4
2 3
RP36 56_0404_4P2R_5%
1 4
2 3
RP34 56_0404_4P2R_5%
1 4
2 3
RP32 56_0404_4P2R_5%
1 4
2 3
RP30 56_0404_4P2R_5%
D
+1.8V+DIMM_VREF
1
1
+
+
C290
C39
150U_D2_6.3VM@
2
150U_D2_6.3VM
+1.8V
1
C55
C50
2.2U_0805_10V6K
2
2.2U_0805_10V6K
+0.9VS
+1.8V
1
C64
2
0.1U_0402_16V4Z
+0.9VS
1
C669
2
0.1U_0402_16V4Z
+0.9VS
1
C662
0.1U_0402_16V4Z
2
+0.9VS
1
C65
0.1U_0402_16V4Z
2
C61
0.1U_0402_16V4Z
C677
0.1U_0402_16V4Z
C87
0.1U_0402_16V4Z
C73
0.1U_0402_16V4Z
C78
0.1U_0402_16V4Z
2
1
2
1
2
1
2
1
2
1
2
1
C89
2
0.1U_0402_16V4Z
1
C124
2.2U_0805_10V6K
2
1
C114
2
0.1U_0402_16V4Z
1
C647
2
0.1U_0402_16V4Z
1
C91
0.1U_0402_16V4Z
2
1
C77
0.1U_0402_16V4Z
2
C126
2.2U_0805_10V6K
C116
0.1U_0402_16V4Z
C652
0.1U_0402_16V4Z
C97
0.1U_0402_16V4Z
1
2
1
2
1
2
1
2
1
2
1
C79
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
C70
2.2U_0805_10V6K
2
1
C659
2
0.1U_0402_16V4Z
1
C110
0.1U_0402_16V4Z
2
C90
E
1
2
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
DDRII-SODIMM1
HBL51 LA-3081P
E
13 47Wednesday, November 09, 2005
0.2
of
A
FSLC FSLB FSLA CPU
CLKSEL2 CLKSEL1 CLKSEL0
0
0
01
1 1
**SEL_PCI5/REF1
**SEL_PCI6/PCICLK1
**SEL_24M/PCICLK2
**SEL_48M/PCICLK3
MHz
133 100 33.3
1
1
Table : ICS9LPR325
01
CLKREQ3# 33.3MHz PCICLK5
CLKREQ5# 33.3MHz PCICLK6
TESTMODE 24MHz Output
CLKREQ7# 48MHz_1 Output
ITP_EN/PCICLK_F0 SRC pair C P U_ IT P pai r
**SEL_24M/PCICLK2=0=TESTMODE
**SEL_PCI6/PCICLK1=0=CLKREQ5#
+3VS
**SEL_PCI5=1=PCICLK5
1 2
R712 10K_0402_5%
1 2
R619 10K_0402_5%
ITP_EN/PCICLK_F0=0=SRC pair
2 2
1 2
R713
10K_0402_5%
CLK_REF
CLK_PCI0
CLK_PCI4
08/29 add
+3VS
1 2
R620
10K_0402_5%
3 3
ICH_SMBDATA(20,26,28,29)
ICH_SMBCLK(20,26,28,29)
R621
4 4
8.2K_0402_5%
1 2
1 2
R616
1K_0402_5%@
A
+3VS
2
1 3
D
+3VS
2
1 3
D
R623
56_0402_5%@
R622
1K_0402_5%
1 2
1 2
1 2
R615
0_0402_5%
G
S
Q15
2N7002_SOT23
G
S
Q14
2N7002_SOT23
R387
4.7K_0402_5%
1 2
R386
4.7K_0402_5%
1 2
SRC
MHz
CLK_ICH_48M(20)
CLK_SD_48M(24)
CLK_14M_SIO(31)
CLK_PCI_SIO(31)
CLK_PCI_MINI(28)
CLK_PCI_LAN(26)
CLK_PCI_PCM(24)
CLK_PCI_LPC(32)
CLK_PCI_TPM(31)
CLK_ICH_14M(20)
CLK_DREF_96M(6)
CLK_DREF_96M#(6)
CLK_PCI_ICH(18)
CLK_ENABLE#(47)
CLK_ENABLE#
2005/10/17
D_CK_SDATA
D_CK_SCLK
MCH_CLKSEL0 (6)
B
PCI
MHz
33.3100166
+3VS
+3VS
CPU_BSEL0 (5)
B
C
+CLK_VDD48
1
C432
10U_0805_10V4Z
2
C466
33P_0402_50V8J
1 2
C468
33P_0402_50V8J
1 2
CLK_ICH_48M
CLK_SD_48M CLKSEL0
CLK_14M_SIO
CLK_PCI_SIO
CLK_PCI_MINI
CLK_PCI_LAN
CLK_PCI_PCM
CLK_PCI_TPM
CLK_ICH_14M CLK_REF
CLK_DREF_96M
CLK_DREF_96M#
CLK_PCI_ICH
CLK_ENABLE#
CLK_ENABLE#
1
C444
0.047U_0402_16V7K
2
+CLK_VDD2
12
Y3
14.31818MHz_20P_1BX14318BE1A
R288 12_0402_5%
1 2
R307 12_0402_5%
1 2
R349 33_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
G
S
Q38
2N7002_SOT23
2005/10/31
VGATE (6,20,47)
R326 33_0402_5%
R327 12_0402_5%
R333 33_0402_5%4401@
R338 33_0402_5%
R345 33_0402_5%
R344 12_0402_5%@
R353 33_0402_5%
R306 0_0402_5%
R305 0_0402_5%
R308 33_0402_5%
R657 0_0402_5%
D_CK_SCLK(12,13)
D_CK_SDATA(12,13)
1 3
D
1 2
R376 1_0603_5%
1 2
R316 2.2_0603_5%
12
D_CK_SCLK
D_CK_SDATA
1
2
+CLK_VDD1
+CLK_VDDREF
+CLK_VDD48
CLK_XTALIN
CLK_XTALOUT
2005/10/17
+1.05VS+1.05VS +1.05VS
R624
1K_0402_5%@
R625
1K_0402_5%
CLKSEL1CLKSEL0 CLKSEL2
1 2
R617
0_0402_5%@
1 2
C
1 2
1 2
R618
0_0402_5%
D
+CLK_VDDREF
C474
0.047U_0402_16V7K
+CLK_VDD1
15mil
15mil
CLKSEL1
CLKSEL2
CLK_PCI4
CLK_PCI3
CLK_PCI2
CLK_PCI1CLK_PCI_LPC
CLK_DOT
CLK_DOT#
CLK_PCI0
CLKIREF
15mil
+3VS
KC FBM-L11-201209-221LMAT_0805
U19
1
VDDSRC
49
VDDSRC
54
VDDSRC
65
VDDSRC
30
VDDPCI
36
VDDPCI
12
VDDCPU
18
VDDREF
40
VDD48
20
X1
19
X2
41
USB_48MHz/FSLA
45
FSLB/TEST_MODE/24Mhz
23
REF0/FSLC/TEST_SEL
34
PCICLK4/FCTSEL1
33
SEL_48M/PCICLK3
32
SEL_24M/PCICLK2
27
SEL_PCI6/PCICLK1
22
SEL_PCI5/REF1
43
DOTT_96MHz/27MHz_Nonspread
44
DOTC_96MHz/27MHz_spread
37
ITP_EN/PCICLK_F0
39
VTT_PWRGD#/PD
9
GND
16
SMBCLK
17
SMBDAT
4
GNDSRC
15
GNDCPU
21
GNDREF
31
GNDPCI
35
GNDPCI
42
GND48
68
GNDSRC
73
THRM_PAD
74
THRM_PAD
75
THRM_PAD
76
THRM_PAD
ICS9LPR325AKLFT_MLF72
ICS9LPR325AKLFT_MLF72: SA00000RE00
SLG8LP465VTR: SA00000TS00
MCH_CLKSEL1 (6)
CPU_BSEL1 (5)
D
E
L58
1 2
CPUCLKT2_ITP/SRCCLKT10LP
CPUCLKC2_ITP/SRCCLKC10LP
R646
0_0402_5%@
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C452
10U_0805_10V4Z
2
VDDA
GNDA
PCI_SRC_STOP#
CPU_STOP#
CPUCLKT1LP
CPUCLKC1LP
CPUCLKT0LP
CPUCLKC0LP
SRCCLKT9LP
SRCCLKC9LP
CLKREQ9#
SRCCLKT8LP
SRCCLKC8LP
CLKREQ8#
SRCCLKT7LP
SRCCLKC7LP
CLKREQ7#/48Mhz_1
SRCCLKT6LP
SRCCLKC6LP
CLKREQ6#
SRCCLKT5LP
SRCCLKC5LP
CLKREQ5#/PCICLK6
SRCCLKT4LP
SRCCLKC4LP
CLKREQ4#
SRCCLKT3LP
SRCCLKC3LP
CLKREQ3#/PCICLK5
SRCCLKT2LP
SRCCLKC2LP
CLKREQ2#
SRCCLKT1LP
SRCCLKC1LP
CLKREQ1#
LCD100/96/SRC0_TLP
LCD100/96/SRC0_CLP
R643
8.2K_0402_5%
1 2
1 2
1 2
+CLK_VCCA
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Deciphered Date
1
C443
0.047U_0402_16V7K
2
1
2
12
1
C477
0.047U_0402_16V7K
2
20mil
1
PM_STP_PCI#
PM_STP_CPU#
CLK_CPU1
CLK_CPU1#
CLK_CPU0
CLK_CPU0#
CLK_SRC9
CLK_SRC9#
CLK_SRC8
CLK_SRC8#
CLK_SRC6
CLK_SRC6#
CLK_SRC5
CLK_SRC5#
CLK_SRC4
CLK_SRC4#
CLK_SRC3
CLK_SRC3#
CLK_PCI5
CLK_SRC2
CLK_SRC2#
CLK_SRC1
CLK_SRC1#
CLK_SRC0
CLK_SRC0#
E
C483
10U_0805_10V4Z
2
R373 0_0402_5%
R372 0_0402_5%
R375 0_0402_5%
R374 0_0402_5%
R371 0_0402_5%EXPCARD@
R370 0_0402_5%EXPCARD@
R658 10K_0402_5%
R367 0_0402_5%MINI2@
R365 0_0402_5%MINI2@
R659 10K_0402_5%
R355 0_0402_5%
R361 0_0402_5%
R647 10K_0402_5%
R347 0_0402_5%
R351 0_0402_5%
R637 10K_0402_5%
R336 0_0402_5%8789@
R340 0_0402_5%8789@
R640 10K_0402_5%@
R636 10K_0402_5%@
R334 33_0402_5%
R300 0_0402_5%
R299 0_0402_5%
R639 10K_0402_5%
R302 0_0402_5%MINI1@
R301 0_0402_5%MINI1@
R626 10K_0402_5%
R304 0_0402_5%
R303 0_0402_5%
MCH_CLKSEL2 (6)
CPU_BSEL2 (5)
Compal Secret Data
7
8
25
24
11
10
14
13
6
5
3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46
47
48
R638
1K_0402_5%@
R645
1K_0402_5%
1 2
1 2
R642
0_0402_5%
2005/06/20 2006/06/20
F
40mil
1
2
L59
1 2
KC FBM-L11-201209-221LMAT_0805
C476
0.047U_0402_16V7K
PM_STP_PCI# (20)
PM_STP_CPU# (20)
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_PCIE_CARD
CLK_PCIE_CARD#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCI_1394
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
CLK_DREF_SSC
CLK_DREF_SSC#
F
C469
0.047U_0402_16V7K
+CLK_VDD1
0.047U_0402_16V7K
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+CLK_VDD1
1
C475
0.047U_0402_16V7K
2
+CLK_VDD2
40mil
1
C457
0.047U_0402_16V7K
2
CLK_MCH_BCLK (6)
CLK_MCH_BCLK# (6)
CLK_CPU_BCLK (4)
CLK_CPU_BCLK# (4)
CLK_PCIE_CARD (29)
CLK_PCIE_CARD# (29)
EXP_CLKREQ# (29)
CLK_PCIE_MINI2 (28)
CLK_PCIE_MINI2# (28)
MINI2_CLKREQ# (28)
CLK_PCIE_SATA (19)
CLK_PCIE_SATA# (19)
SATA_CLKREQ# (20)
CLK_PCIE_ICH (20)
CLK_PCIE_ICH# (20)
CLK_PCIE_LAN (26)
CLK_PCIE_LAN# (26)
CLK_PCI_1394 (30)
CLK_MCH_3GPLL (6)
CLK_MCH_3GPLL# (6)
MCH_CLKREQ# (6)
CLK_PCIE_MINI1 (28)
CLK_PCIE_MINI1# (28)
MINI1_CLKREQ# (28)
CLK_DREF_SSC (6)
CLK_DREF_SSC# (6)
Title
Size Document Number Rev
B
Date: Sheet
G
Clock Generator
1
C460
2
Compal Electronics, Inc.
HBL51 LA-3081P
G
C440
10U_0805_10V4Z
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_DREF_SSC
CLK_DREF_SSC#
CLK_DREF_96M
CLK_DREF_96M#
CLK_PCIE_CARD
CLK_PCIE_CARD#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_LAN
CLK_PCIE_LAN#
Clock Generator
R383 49.9_0402_1%@
R382 49.9_0402_1%@
R385 49.9_0402_1%@
R384 49.9_0402_1%@
R366 49.9_0402_1%@
R364 49.9_0402_1%@
R346 49.9_0402_1%@
R350 49.9_0402_1%@
R283 49.9_0402_1%@
R282 49.9_0402_1%@
R354 49.9_0402_1%@
R360 49.9_0402_1%@
R285 49.9_0402_1%@
R284 49.9_0402_1%@
R287 49.9_0402_1%@
R286 49.9_0402_1%@
R381 49.9_0402_1%@
R380 49.9_0402_1%@
R281 49.9_0402_1%@
R280 49.9_0402_1%@
R335 49.9_0402_1%@
R339 49.9_0402_1%@
H
L60
1 2
KC FBM-L11-201209-221LMAT_0805
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
14 47Thursday, No vember 10, 2005
of
H
+3VS
0.2
5
4
3
2
1
LCD POWER CIRCUIT
+3VS
12
R492
4.7K_0402_5%
2
+3VS
G
4.7U_0805_10V4Z
W=60mils
S
Q28
SI2301BDS_SOT23
D
1 3
1
C593
2
1
2
+LCDVDD
1
2
C12
4.7U_0805_10V4Z
AOS 3413
W=60mils
C597
0.1U_0402_16V4Z
+LCDVDD
12
D D
GMCH_ENVDD(8)
C C
300_0402_5%
2N7002_SOT23
R485
Q25
BKOFF#(32)
13
D
S
10K_0402_5%
+3VALW
12
R493
100K_0402_5%
2
G
2
G
12
R490
BKOFF# DISPOFF#
13
D
Q1
2N7002_SOT23
S
R496 1K_0402_5%
D27
RB751V_SOD323
21
12
C600
1
0.047U_0402_16V7K
2
LCD/PANEL BD. Conn.
+INVPWR_B+
+3VS +LCDVDD
I2CC_SCL
I2CC_SDA
TZOUT0-
TZOUT1+
TZOUT1-
TZOUT2+
TZOUT2-
TZCLK-
B B
TZCLK+
JP1
20
40
19
39
18
38
17
37
16
36
15
35
14
34
13
33
12
32
11
31
10
30
9
29
8
28
7
27
6
26
5
25
4
24
3
23
2
22
1
21
ACES_88107-4000G
DAC_BRIG
INVT_PWM
DISPOFF#
(60 MIL)
TXOUT0TXOUT0+TZOUT0+
TXOUT1TXOUT1+
TXOUT2+
TXOUT2-
TXCLKTXCLK+
DAC_BRIG (32)
INVT_PWM (32)
(SAME AS ACES_87216-4016)
+LCDVDD
1
C586
10U_0805_10V4Z
2
1
C591
0.1U_0402_16V4Z
2
C930
680P_0603_50V7K
L1
KC FBM-L11-201209-221LMAT_0805
L2
KC FBM-L11-201209-221LMAT_0805
1
2
1
C10
68P_0402_50V8K
2
+3VS+INVPWR_B+
12
12
B+
1
C11
0.1U_0402_16V4Z
2
I2CC_SCL
I2CC_SDA
TXOUT0TXOUT0+
TXOUT1TXOUT1+
TXOUT2+
TXOUT2-
TXCLKTXCLK+
TZOUT0TZOUT0+
TZOUT1+
TZOUT1-
TZOUT2+
TZOUT2-
TZCLKTZCLK+
08/30 modified
I2CC_SCL (8)
I2CC_SDA (8)
TXOUT0- (8)
TXOUT0+ (8)
TXOUT1- (8)
TXOUT1+ (8)
TXOUT2+ (8)
TXOUT2- (8)
TXCLK- (8)
TXCLK+ (8)
TZOUT0- (8)
TZOUT0+ (8)
TZOUT1+ (8)
TZOUT1- (8)
TZOUT2+ (8)
TZOUT2- (8)
TZCLK- (8)
TZCLK+ (8)
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet
Compal Electronics, Inc.
LCD Connector
HBL51 LA-3081P
1
15 47Wednesday, November 09, 2005
0.2
of
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