Texas Instruments XIO3130 EVM User Manual
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SLLU108–July2008

XIO3130 EVM

1.1Overview

The Texas Instruments XIO3130 EVM is a functional implementation of a four-portPCIe-to-PCIeswitch. The XIO3130 EVM was designed to allow validation of three separate functional modes. In normal mode, the EVM is configured as a generic PCI Express (PCIe) switch. Inhot-plugmode, downstream ports 1 and 2 are configured ashot-pluggableslots. In ExpressCard mode, all three downstream ports are configured to support the ExpressCard adapter board. The different functional modes are discussed later in this document.

Figure 1-1 shows the EVM board. There are various jumpers, dipswitches, push buttons, and LEDs to support the various functional modes. For the board to operate, power must be applied via the peripheral power connector located to the right side of the board. Endpoints can be plugged directly into any one or all of the downstream ports. The upstream edge connector can be plugged into any PCIe slot on a motherboard. Once the EVM with attached endpoints is plugged into a PCIe motherboard and power is provided to the EVM, nothing else needs to be done in order for the EVM to operate. The two LEDs in the upperright-handcorner light up when power is applied to the peripheral power connector.

Figure 1-1.EVM Board

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Normal-ModeOperation

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1.2Normal-ModeOperation

By default, the EVM should be configured to operate in normal mode. The six jumpers (J7, J11, J13, J14, J15, and J16) should be covering both pins of each header (see Figure 1-2).

Figure 1-2.Power Jumpers

The dipswitch should be configured with SCL slide switch in the up position and DN1_DPSTRP, DN2_DPSTRP, and DN3_DPSTRP slide switches in the down position (see Figure 1-3).This configuration enables the EEPROM and disableshot-plugoperation.

Figure 1-3.Dipswitch Configuration

The EEPROM (U3) should also be preconfigured for normal-modeoperation. SeeSection 1.5 for an explanation of how to configure the EEPROM. Upon deassertion of PERST, the XIO3130 automatically reads data from the EEPROM. This data is used to preset various PCI configuration register bits. Fornormal-modeoperation, the data in the EEPROM will configure bits in the following registers:

GPIO C control register (PCI register offset: C0h in upstream bridge)

PCIE_GPIO12_CTL = 010b – Port 1 ACT_LED0

PCIE_GPIO13_CTL = 011b – Port 2 ACT_LED1

PCIE_GPIO14_CTL = 100b – Port 3 ACT_LED2

Setting these bits configures LED1 as activity LED for port 1, LED2 as activity LED for port 2, and LED3 as activity LED for port 3. Any time a TLP is transferred to or from the slot, the activity LED flashes. LEDs 4 and 5 are nonfunctional in normal mode; pressing the push buttons will have no effect on the XIO3130.

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Hot-Plug-ModeOperation

Figure 1-4.GPIO Control Register

General control register (PCI register offset: D4h in each downstream bridge)

RCVR_PRSNT_EN = 0b – PRSNT pin is used to determine whether slot is present

REFCK_DIS = 0b – REFCK enabled

LINK_ACT_RPT_CAP = 1b – Slot is link active reporting capable

SLOT_PRSNT = 1b – Port connected to slot

General slot info register (PCI register offset EEh in each downstream bridge)

SLOT_NUM = 1b for slot 1, 2b for slot 2, and 3b for slot 3

1.3Hot-Plug-ModeOperation

In hot-plugmode, the EVM board utilizes the TPS2363 PCIe serverdual-slothot-plugcontroller to switch power on and off to slots 1 and 2. The TPS2363 is directly controlled by thehot-plugcontroller built into the XIO3130. Slot 3 operates in normal mode. To configure the EVM forhot-plugoperation, the six jumpers (J7, J11, J13, J14, J15, J16) must be removed (seeFigure 1-5).

Figure 1-5.Power Jumpers

The dipswitch should be configured with SCL, DN1_DPSTRP and DN2_DPSTRP slide switches in the up position, and DN3_DPSTRP slide switches in the down position (see Figure 1-6).This configuration enables the EEPROM and enableshot-plugoperation on slots 1 and 2.

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Hot-Plug-ModeOperation

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Figure 1-6.Dipswitch Configuration

The EEPROM (U3) should be reconfigured for hot-plug-modeoperation. SeeSection 1.5 for an explanation of how to configure the EEPROM. Upon deassertion of PERST, the XIO3130 automatically reads data from the EEPROM. This data is used to preset various PCI configuration register bits. Forhot-plug-modeoperation, the data in the EEPROM configures bits in the following registers:

GPIO B control register (PCI Register offset: BEh in upstream bridge)

PCIE_GPIO8_CTL = 010b – Port 1 ACT_BTN0

PCIE_GPIO9_CTL = 100b – Port 1 ATN_LED0

GPIO C control register (PCI register offset: C0h in upstream bridge)

PCIE_GPIO10_CTL = 011b –Port2 ACT_BTN1

PCIE_GPIO11_CTL = 101b – Port 2 PWRFLT1

PCIE_GPIO12_CTL = 101b – Port 1 PWR_LED0

PCIE_GPIO13_CTL = 110b – Port 2 PWR_LED1

GPIO D control register (PCI register offset: C2h in upstream bridge)

PCIE_GPIO15_CTL = 101b – Port 1 PWRFLT0

PCIE_GPIO16_CTL = 011b – Port 2 ATN_LED1

Setting these bits configures LED1 as PWR_LED0 for port 1 and LED2 as PWR_LED1 for port 2. LED3 is not used inhot-plug mode. LEDs 4 will be configured as ATN_LED0 for port 1 and LED5 will be configured as ATN_LED1 for port 2.Push-buttonswitch SW2 is the attention button for port 1 and SW3 is the attention button for port 2.

Figure 1-7.GPIO Control Register

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