Texas Instruments VLYNQ Port User Manual
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TMS320DM644x DMSoC

VLYNQ Port

User's Guide

Literature Number: SPRUE36A

September 2007

2

SPRUE36A –September2007

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Contents

Preface ...............................................................................................................................

 

 

7

1

Introduction................................................................................................................

 

9

 

1.1

Purpose of the Peripheral .......................................................................................

 

9

 

1.2

Features ...........................................................................................................

 

9

 

1.3

Functional Block Diagram .....................................................................................

 

10

 

1.4

Industry Standard(s) Compliance Statement ...............................................................

 

10

2

Peripheral Architecture ..............................................................................................

 

11

 

2.1

Clock Control ....................................................................................................

 

11

 

2.2

Signal Descriptions .............................................................................................

 

12

 

2.3

Pin Multiplexing .................................................................................................

 

12

 

2.4

Protocol Description ............................................................................................

 

12

 

2.5

VLYNQ Functional Description ...............................................................................

 

13

 

2.6

Initialization ......................................................................................................

 

16

 

2.7

Auto-Negotiation ................................................................................................

 

16

 

2.8

Serial Interface Width Configuration .........................................................................

 

16

 

2.9

Address Translation ............................................................................................

 

17

 

2.10

Flow Control .....................................................................................................

 

20

 

2.11

Reset Considerations ..........................................................................................

 

21

 

2.12

Interrupt Support................................................................................................

 

21

 

2.13

DMA Event Support ............................................................................................

 

23

 

2.14

Power Management ............................................................................................

 

24

 

2.15

Emulation Considerations .....................................................................................

 

24

3

VLYNQ Port Registers................................................................................................

 

25

 

3.1

Revision Register (REVID) ....................................................................................

 

26

 

3.2

Control Register (CTRL) .......................................................................................

 

27

 

3.3

Status Register (STAT) ........................................................................................

 

29

 

3.4

Interrupt Priority Vector Status/Clear Register (INTPRI) ..................................................

 

31

 

3.5

Interrupt Status/Clear Register (INTSTATCLR) ............................................................

 

31

 

3.6

Interrupt Pending/Set Register (INTPENDSET) ............................................................

 

32

 

3.7

Interrupt Pointer Register (INTPTR) .........................................................................

 

32

 

3.8

Transmit Address Map Register (XAM)......................................................................

 

33

 

3.9

Receive Address Map Size 1 Register (RAMS1) ..........................................................

 

34

 

3.10

Receive Address Map Offset 1 Register (RAMO1) ........................................................

 

34

 

3.11

Receive Address Map Size 2 Register (RAMS2) ..........................................................

 

35

 

3.12

Receive Address Map Offset 2 Register (RAMO2) ........................................................

 

35

 

3.13

Receive Address Map Size 3 Register (RAMS3) ..........................................................

 

36

 

3.14

Receive Address Map Offset 3 Register (RAMO3) ........................................................

 

36

 

3.15

Receive Address Map Size 4 Register (RAMS4) ..........................................................

 

37

 

3.16

Receive Address Map Offset 4 Register (RAMO4) ........................................................

 

37

 

3.17

Chip Version Register (CHIPVER) ...........................................................................

 

38

 

3.18

Auto Negotiation Register (AUTNGO) .......................................................................

 

38

4

Remote Configuration Registers .................................................................................

 

39

Appendix A

VLYNQ Protocol Specifications ........................................................................

 

40

 

A.1

Special 8b/10b Code Groups .................................................................................

 

40

SPRUE36A –September2007

Table of Contents

3

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A.2

Supported Ordered Sets.......................................................................................

40

A.3

VLYNQ 2.0 Packet Format ....................................................................................

41

A.4

VLYNQ 2.X Packets............................................................................................

43

Appendix B

Write/Read Performance ..................................................................................

45

B.1

Write Performance..............................................................................................

45

B.2

Read Performance .............................................................................................

47

Appendix C

Revision History .............................................................................................

48

4

Contents

SPRUE36A –September2007

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List of Figures

 

1

VLYNQ Port Functional Block Diagram .................................................................................

10

2

External Clock Block Diagram ............................................................................................

11

3

Internal Clock Block Diagram .............................................................................................

11

4

VLYNQ Module Structure .................................................................................................

13

5

Write Operations ...........................................................................................................

14

6

Read Operations ...........................................................................................................

15

7

Example Address Memory Map ..........................................................................................

18

8

Interrupt Generation Mechanism Block Diagram.......................................................................

22

9

Revision Register (REVID)................................................................................................

26

10

Control Register (CTRL)...................................................................................................

27

11

Status Register (STAT)....................................................................................................

29

12

Interrupt Priority Vector Status/Clear Register (INTPRI) ..............................................................

31

13

Interrupt Status/Clear Register (INTSTATCLR) ........................................................................

31

14

Interrupt Pending/Set Register (INTPENDSET)........................................................................

32

15

Interrupt Pointer Register (INTPTR) .....................................................................................

32

16

Transmit Address Map Register (XAM) .................................................................................

33

17

Receive Address Map Size 1 Register (RAMS1) ......................................................................

34

18

Receive Address Map Offset 1 Register (RAMO1) ....................................................................

34

19

Receive Address Map Size 2 Register (RAMS2) ......................................................................

35

20

Receive Address Map Offset 2 Register (RAMO2) ....................................................................

35

21

Receive Address Map Size 3 Register (RAMS3) ......................................................................

36

22

Receive Address Map Offset 3 Register (RAMO3) ....................................................................

36

23

Receive Address Map Size 4 Register (RAMS4) ......................................................................

37

24

Receive Address Map Offset 4 Register (RAMO4) ....................................................................

37

25

Chip Version Register (CHIPVER) .......................................................................................

38

26

Auto Negotiation Register (AUTNGO)...................................................................................

38

A-1

Packet Format (10-bit Symbol Representation) ........................................................................

41

SPRUE36A –September2007

List of Figures

5

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List of Tables

 

1

VLYNQ Port Pins ...........................................................................................................

12

2

Serial Interface Width ......................................................................................................

16

3

Address Translation Example (Single Mapped Region) ..............................................................

18

4

Address Translation Example (Single Mapped Region) ..............................................................

19

5

VLYNQ Register Address Space.........................................................................................

25

6

VLYNQ Port Controller Registers ........................................................................................

25

7

Revision Register (REVID) Field Descriptions .........................................................................

26

8

Control Register (CTRL) Field Descriptions ............................................................................

27

9

Status Register (STAT) Field Descriptions .............................................................................

29

10

Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions........................................

31

11

Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions..................................................

31

12

Interrupt Pending/Set Register (INTPENDSET) Field Descriptions .................................................

32

13

Interrupt Pointer Register (INTPTR) Field Descriptions ...............................................................

32

14

Address Map Register (XAM) Field Descriptions ......................................................................

33

15

Receive Address Map Size 1 Register (RAMS1) Field Descriptions ................................................

34

16

Receive Address Map Offset 1 Register (RAMO1) Field Descriptions..............................................

34

17

Receive Address Map Size 2 Register (RAMS2) Field Descriptions ................................................

35

18

Receive Address Map Offset 2 Register (RAMO2) Field Descriptions..............................................

35

19

Receive Address Map Size 3 Register (RAMS3) Field Descriptions ................................................

36

20

Receive Address Map Offset 3 Register (RAMO3) Field Descriptions..............................................

36

21

Receive Address Map Size 4 Register (RAMS4) Field Descriptions ................................................

37

22

Receive Address Map Offset 4 Register (RAMO4) Field Descriptions..............................................

37

23

Chip Version Register (CHIPVER) Field Descriptions.................................................................

38

24

Auto Negotiation Register (AUTNGO) Field Descriptions ............................................................

38

25

VLYNQ Port Remote Controller Registers ..............................................................................

39

A-1

Special 8b/10b Code Groups .............................................................................................

40

A-2

Supported Ordered Sets ..................................................................................................

40

A-3

Packet Format (10-bit Symbol Representation) Description..........................................................

42

B-1

Scaling Factors .............................................................................................................

46

B-2

Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ) ....................................

46

B-3

Relative Performance with Various Latencies ..........................................................................

47

C-1

Document Revision History ...............................................................................................

48

6

List of Tables

SPRUE36A –September2007

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