Texas Instruments VLYNQ Port User Manual

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TMS320DM644x DMSoC

VLYNQ Port

User's Guide

Literature Number: SPRUE36A

September 2007

2

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Contents

Preface ...............................................................................................................................

 

 

7

1

Introduction................................................................................................................

 

9

 

1.1

Purpose of the Peripheral .......................................................................................

 

9

 

1.2

Features ...........................................................................................................

 

9

 

1.3

Functional Block Diagram .....................................................................................

 

10

 

1.4

Industry Standard(s) Compliance Statement ...............................................................

 

10

2

Peripheral Architecture ..............................................................................................

 

11

 

2.1

Clock Control ....................................................................................................

 

11

 

2.2

Signal Descriptions .............................................................................................

 

12

 

2.3

Pin Multiplexing .................................................................................................

 

12

 

2.4

Protocol Description ............................................................................................

 

12

 

2.5

VLYNQ Functional Description ...............................................................................

 

13

 

2.6

Initialization ......................................................................................................

 

16

 

2.7

Auto-Negotiation ................................................................................................

 

16

 

2.8

Serial Interface Width Configuration .........................................................................

 

16

 

2.9

Address Translation ............................................................................................

 

17

 

2.10

Flow Control .....................................................................................................

 

20

 

2.11

Reset Considerations ..........................................................................................

 

21

 

2.12

Interrupt Support................................................................................................

 

21

 

2.13

DMA Event Support ............................................................................................

 

23

 

2.14

Power Management ............................................................................................

 

24

 

2.15

Emulation Considerations .....................................................................................

 

24

3

VLYNQ Port Registers................................................................................................

 

25

 

3.1

Revision Register (REVID) ....................................................................................

 

26

 

3.2

Control Register (CTRL) .......................................................................................

 

27

 

3.3

Status Register (STAT) ........................................................................................

 

29

 

3.4

Interrupt Priority Vector Status/Clear Register (INTPRI) ..................................................

 

31

 

3.5

Interrupt Status/Clear Register (INTSTATCLR) ............................................................

 

31

 

3.6

Interrupt Pending/Set Register (INTPENDSET) ............................................................

 

32

 

3.7

Interrupt Pointer Register (INTPTR) .........................................................................

 

32

 

3.8

Transmit Address Map Register (XAM)......................................................................

 

33

 

3.9

Receive Address Map Size 1 Register (RAMS1) ..........................................................

 

34

 

3.10

Receive Address Map Offset 1 Register (RAMO1) ........................................................

 

34

 

3.11

Receive Address Map Size 2 Register (RAMS2) ..........................................................

 

35

 

3.12

Receive Address Map Offset 2 Register (RAMO2) ........................................................

 

35

 

3.13

Receive Address Map Size 3 Register (RAMS3) ..........................................................

 

36

 

3.14

Receive Address Map Offset 3 Register (RAMO3) ........................................................

 

36

 

3.15

Receive Address Map Size 4 Register (RAMS4) ..........................................................

 

37

 

3.16

Receive Address Map Offset 4 Register (RAMO4) ........................................................

 

37

 

3.17

Chip Version Register (CHIPVER) ...........................................................................

 

38

 

3.18

Auto Negotiation Register (AUTNGO) .......................................................................

 

38

4

Remote Configuration Registers .................................................................................

 

39

Appendix A

VLYNQ Protocol Specifications ........................................................................

 

40

 

A.1

Special 8b/10b Code Groups .................................................................................

 

40

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A.2

Supported Ordered Sets.......................................................................................

40

A.3

VLYNQ 2.0 Packet Format ....................................................................................

41

A.4

VLYNQ 2.X Packets............................................................................................

43

Appendix B

Write/Read Performance ..................................................................................

45

B.1

Write Performance..............................................................................................

45

B.2

Read Performance .............................................................................................

47

Appendix C

Revision History .............................................................................................

48

4

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List of Figures

 

1

VLYNQ Port Functional Block Diagram .................................................................................

10

2

External Clock Block Diagram ............................................................................................

11

3

Internal Clock Block Diagram .............................................................................................

11

4

VLYNQ Module Structure .................................................................................................

13

5

Write Operations ...........................................................................................................

14

6

Read Operations ...........................................................................................................

15

7

Example Address Memory Map ..........................................................................................

18

8

Interrupt Generation Mechanism Block Diagram.......................................................................

22

9

Revision Register (REVID)................................................................................................

26

10

Control Register (CTRL)...................................................................................................

27

11

Status Register (STAT)....................................................................................................

29

12

Interrupt Priority Vector Status/Clear Register (INTPRI) ..............................................................

31

13

Interrupt Status/Clear Register (INTSTATCLR) ........................................................................

31

14

Interrupt Pending/Set Register (INTPENDSET)........................................................................

32

15

Interrupt Pointer Register (INTPTR) .....................................................................................

32

16

Transmit Address Map Register (XAM) .................................................................................

33

17

Receive Address Map Size 1 Register (RAMS1) ......................................................................

34

18

Receive Address Map Offset 1 Register (RAMO1) ....................................................................

34

19

Receive Address Map Size 2 Register (RAMS2) ......................................................................

35

20

Receive Address Map Offset 2 Register (RAMO2) ....................................................................

35

21

Receive Address Map Size 3 Register (RAMS3) ......................................................................

36

22

Receive Address Map Offset 3 Register (RAMO3) ....................................................................

36

23

Receive Address Map Size 4 Register (RAMS4) ......................................................................

37

24

Receive Address Map Offset 4 Register (RAMO4) ....................................................................

37

25

Chip Version Register (CHIPVER) .......................................................................................

38

26

Auto Negotiation Register (AUTNGO)...................................................................................

38

A-1

Packet Format (10-bit Symbol Representation) ........................................................................

41

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List of Figures

5

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List of Tables

 

1

VLYNQ Port Pins ...........................................................................................................

12

2

Serial Interface Width ......................................................................................................

16

3

Address Translation Example (Single Mapped Region) ..............................................................

18

4

Address Translation Example (Single Mapped Region) ..............................................................

19

5

VLYNQ Register Address Space.........................................................................................

25

6

VLYNQ Port Controller Registers ........................................................................................

25

7

Revision Register (REVID) Field Descriptions .........................................................................

26

8

Control Register (CTRL) Field Descriptions ............................................................................

27

9

Status Register (STAT) Field Descriptions .............................................................................

29

10

Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions........................................

31

11

Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions..................................................

31

12

Interrupt Pending/Set Register (INTPENDSET) Field Descriptions .................................................

32

13

Interrupt Pointer Register (INTPTR) Field Descriptions ...............................................................

32

14

Address Map Register (XAM) Field Descriptions ......................................................................

33

15

Receive Address Map Size 1 Register (RAMS1) Field Descriptions ................................................

34

16

Receive Address Map Offset 1 Register (RAMO1) Field Descriptions..............................................

34

17

Receive Address Map Size 2 Register (RAMS2) Field Descriptions ................................................

35

18

Receive Address Map Offset 2 Register (RAMO2) Field Descriptions..............................................

35

19

Receive Address Map Size 3 Register (RAMS3) Field Descriptions ................................................

36

20

Receive Address Map Offset 3 Register (RAMO3) Field Descriptions..............................................

36

21

Receive Address Map Size 4 Register (RAMS4) Field Descriptions ................................................

37

22

Receive Address Map Offset 4 Register (RAMO4) Field Descriptions..............................................

37

23

Chip Version Register (CHIPVER) Field Descriptions.................................................................

38

24

Auto Negotiation Register (AUTNGO) Field Descriptions ............................................................

38

25

VLYNQ Port Remote Controller Registers ..............................................................................

39

A-1

Special 8b/10b Code Groups .............................................................................................

40

A-2

Supported Ordered Sets ..................................................................................................

40

A-3

Packet Format (10-bit Symbol Representation) Description..........................................................

42

B-1

Scaling Factors .............................................................................................................

46

B-2

Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ) ....................................

46

B-3

Relative Performance with Various Latencies ..........................................................................

47

C-1

Document Revision History ...............................................................................................

48

6

List of Tables

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Preface

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About This Document

This document describes the VLYNQ™ communications interface port in the TMS320DM644x Digital Media System-on-Chip(DMSoC).

Notational Conventions

This document uses the following conventions.

Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.

Registers in this document are shown in figures and described in tables.

Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.

Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments

The following documents describe the TMS320DM644x Digital Media System-on-Chip(DMSoC). Copies of these documents are available on the Internet atwww.ti.com.Tip: Enter the literature number in the search box provided at www.ti.com.

The current documentation that describes the DM644x DMSoC, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.

SPRUE14 TMS320DM644x DMSoC ARM Subsystem Reference Guide.Describes the ARM subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP subsystem, the video processing subsystem, and a majority of the peripherals and external memories.

SPRUE15 TMS320DM644x DMSoC DSP Subsystem Reference Guide.Describes the digital signal processor (DSP) subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC).

SPRUE19 TMS320DM644x DMSoC Peripherals Overview Reference Guide.Provides an overview and briefly describes the peripherals available on the TMS320DM644x Digital Media System-on-Chip (DMSoC).

SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide.Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included.

SPRU732 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide.Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.

SPRU871 TMS320C64x+ DSP Megamodule Reference Guide.Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.

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Preface

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Related Documentation From Texas Instruments

SPRAAA6 EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC.Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memory access (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. This document summarizes the key differences between the EDMA3 and the EDMA2 and provides guidance for migrating from EDMA2 to EDMA3.

Trademarks

VLYNQ is a trademark of Texas Instruments.

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User's Guide

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VLYNQ Port

1 Introduction

1.1Purpose of the Peripheral

The VLYNQ™ communications interface port is a low pin count, high-speed,point-to-pointserial interface in the TMS320DM644x Digital MediaSystem-on-Chip(DMSoC) used for connecting to host processors and otherVLYNQ-compatibledevices. The VLYNQ port is afull-duplexserial bus where transmit and receive operations occur separately and simultaneously without interference.

VLYNQ enables the extension of an internal bus segment to one or more external physical devices. The external devices are mapped to local physical address space and appear as if they are on the internal bus of the DM644x DMSoC. The external devices must also have a VLYNQ interface.

VLYNQ uses a simple block code (8b/10b) packet format and supports in-bandflow control so that no extra terminals are needed to indicate that overflow conditions might occur.

The VLYNQ module on the DM644x DMSoC serializes a write transaction to the remote/external device and transfers the write via the VLYNQ port (TX pins). The remote VLYNQ module deserializes the transaction on the other side.

The read transactions to the remote/external device follow the same process, but the remote device's VLYNQ module serializes the read return data and transfers it to the VLYNQ port (RX pins). The read return data is finally deserialized and released to the device internal bus.

The external device can also initiate read and write transactions.

1.2Features

The general features of the VLYNQ port are:

Low pin count (10 pin interface, scalable to as low as 3 pins)

No tri-statesignals

All signals are dedicated and driven by only one device

Necessary to allow support for high-speedPHYs

Scalable Performance

Programmable frequency and 1 to 4 bits for TX and RX data

Performance increases linearly as the data port width increases

Simple packet-basedtransfer protocol formemory-mappedaccess

Write request/data packet

Read request packet

Read response data packet

Interrupt request packet

Auto width negotiation

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VLYNQ Port

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Introduction

Symmetric Operations

Transmit (TX) pins on the first device connect to the receive (RX) pins on the second device and vice-versa.

Data pin widths are automatically detected after reset

Re-requestpackets, response packets, and flow control information are all multiplexed and sent across the same physical pins.

Supports both host/peripheral and peer-to-peercommunication models

Simple block code packet formatting (8b/10b)

Supports in-bandand flow control

No extra pins are needed

Allows the receiver to momentarily throttle the transmitter back when overflow is about to occur

Uses the special built-inblock code capability to interleave flow control information seamlessly with user data

Automatic packet formatting optimizations

Internal loopback modes are provided

Connects to legacy VLYNQ devices

1.3Functional Block Diagram

Figure 1 shows a functional block diagram of the VLYNQ port.

Figure 1. VLYNQ Port Functional Block Diagram

VLYNQ module

Slave

ARM/EDMA

config bus

VLYNQ register Interface access

CPU/EDMA initiated transfers to remote device

 

Master

System

config

 

memory

bus

 

Off chip

Interface

(remote)

 

device access

 

 

VLQINT

 

INT31

 

ARM interrupt

 

controller

VLYNQ_SCRUN

VLYNQ_CLOCK

VLYNQ_TXD[3:0]

VLYNQ_RXD[3:0]

1.4Industry Standard(s) Compliance Statement

VLYNQ is an interface defined by Texas Instruments and does not conform to any other industry standard.

10

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