Texas Instruments TMS320TCI648x User Manual
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TMS320TCI648x Serial RapidIO (SRIO)

User's Guide

Literature Number: SPRUE13A

September 2006

2

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Contents

Preface..............................................................................................................................

 

14

1

Overview ..................................................................................................................

16

 

1.1

General RapidIO System ......................................................................................

16

 

1.2

RapidIO Feature Support in SRIO............................................................................

19

 

1.3

Standards........................................................................................................

20

 

1.4

External Devices Requirements ..............................................................................

20

 

1.5

TI Devices Supported By This Document ...................................................................

20

2

SRIO Functional Description.......................................................................................

21

 

2.1

Overview .........................................................................................................

21

 

2.2

SRIO Pins .......................................................................................................

25

 

2.3

Functional Operation ...........................................................................................

26

3

Logical/Transport Error Handling and Logging .............................................................

83

4

Interrupt Conditions...................................................................................................

85

 

4.1

CPU Interrupts ..................................................................................................

85

 

4.2

General Description ............................................................................................

85

 

4.3

Interrupt Condition Status and Clear Registers.............................................................

86

 

4.4

Interrupt Condition Routing Registers........................................................................

93

 

4.5

Interrupt Status Decode Registers ...........................................................................

97

 

4.6

Interrupt Generation ............................................................................................

99

 

4.7

Interrupt Pacing .................................................................................................

99

 

4.8

Interrupt Handling .............................................................................................

100

5

SRIO Registers ........................................................................................................

 

102

 

5.1

Introduction ....................................................................................................

 

102

 

5.2

Peripheral Identification Register (PID) ....................................................................

 

111

 

5.3

Peripheral Control Register (PCR)..........................................................................

 

112

 

5.4

Peripheral Settings Control Register (PER_SET_CNTL) ................................................

 

113

 

5.5

Peripheral Global Enable Register (GBL_EN) ............................................................

 

116

 

5.6

Peripheral Global Enable Status Register (GBL_EN_STAT)............................................

 

117

 

5.7

Block n Enable Register (BLKn_EN) .......................................................................

 

119

 

5.8

Block n Enable Status Register (BLKn_EN_STAT) ......................................................

 

120

 

5.9

RapidIO DEVICEID1 Register (DEVICEID_REG1).......................................................

 

121

 

5.10

RapidIO DEVICEID2 Register (DEVICEID_REG2).......................................................

 

122

 

5.11

Packet Forwarding Register n for16-BitDevice IDs (PF_16B_CNTLn)...............................

 

123

 

5.12

Packet Forwarding Register n for8-BitDevice IDs (PF_8B_CNTLn)..................................

 

124

 

5.13

SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL).................

125

 

5.14

SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL).................

128

 

5.15

SERDES Macro Configuration Register n (SERDES_CFGn_CNTL)..................................

 

130

 

5.16

DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR).............................

 

132

 

5.17

DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR)..............................

 

133

 

5.18

RX CPPI Interrupt Status Register (RX_CPPI_ICSR) ...................................................

 

134

 

5.19

RX CPPI Interrupt Clear Register (RX_CPPI_ICCR).....................................................

 

135

 

5.20

TX CPPI Interrupt Status Register (TX_CPPI_ICSR) ....................................................

 

136

 

5.21

TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) .....................................................

 

137

 

5.22

LSU Interrupt Condition Status Register (LSU_ICSR) ...................................................

 

138

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5.23

LSU Interrupt Condition Clear Register (LSU_ICCR) ....................................................

141

 

5.24

Error, Reset, and Special Event Interrupt Condition Status Register

 

 

 

(ERR_RST_EVNT_ICSR)....................................................................................

142

 

5.25

Error, Reset, and Special Event Interrupt Condition Clear Register

 

 

 

(ERR_RST_EVNT_ICCR) ...................................................................................

143

 

5.26

DOORBELLn Interrupt Condition Routing Registers (DOORBELLn_ICRR and

 

 

 

DOORBELLn_ICRR2) ........................................................................................

144

 

5.27

RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2) .........

145

 

5.28

TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2)..........

146

 

5.29

LSU Interrupt Condition Routing Registers (LSU_ICRR0–LSU_ICRR3) ..............................

147

 

5.30

Error, Reset, and Special Event Interrupt Condition Routing Registers

 

 

 

(ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3) .............

149

 

5.31

Interrupt Status Decode Register (INTDSTn_DECODE)................................................

150

 

5.32

INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL)...................................

154

 

5.33

LSUn Control Register 0 (LSUn_REG0) ...................................................................

155

 

5.34

LSUn Control Register 1 (LSUn_REG1) ...................................................................

156

 

5.35

LSUn Control Register 2 (LSUn_REG2) ...................................................................

157

 

5.36

LSUn Control Register 3 (LSUn_REG3) ...................................................................

158

 

5.37

LSUn Control Register 4 (LSUn_REG4) ...................................................................

159

 

5.38

LSUn Control Register 5 (LSUn_REG5) ...................................................................

160

 

5.39

LSUn Control Register 6 (LSUn_REG6) ...................................................................

161

 

5.40

LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS)..............................

162

 

5.41

Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP)..............

164

 

5.42

Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP)......................

165

 

5.43

Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP)..............

166

 

5.44

Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP)......................

167

 

5.45

Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN)....................................

168

 

5.46

Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0–7])..................

169

 

5.47

Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) ....................................

172

 

5.48

Receive CPPI Control Register (RX_CPPI_CNTL).......................................................

173

 

5.49

Transmit CPPI Weighted Round Robin Control Registers (TX_QUEUE_CNTL[0–3])...............

174

 

5.50

Mailbox to Queue Mapping Registers (RXU_MAP_Ln and RXU_MAP_Hn)..........................

177

 

5.51

Flow Control Table Entry Register n (FLOW_CNTLn) ...................................................

181

 

5.52

Device Identity CAR (DEV_ID) ..............................................................................

182

 

5.53

Device Information CAR (DEV_INFO) .....................................................................

183

 

5.54

Assembly Identity CAR (ASBLY_ID) .......................................................................

184

 

5.55

Assembly Information CAR (ASBLY_INFO) ...............................................................

185

 

5.56

Processing Element Features CAR (PE_FEAT) ..........................................................

186

 

5.57

Source Operations CAR (SRC_OP) ........................................................................

188

 

5.58

Destination Operations CAR (DEST_OP) .................................................................

189

 

5.59

Processing Element Logical Layer Control CSR (PE_LL_CTL) ........................................

190

 

5.60

Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR).................................

191

 

5.61

Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR)...................................

192

 

5.62

Base Device ID CSR (BASE_ID) ...........................................................................

193

 

5.63

Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK).............................................

194

 

5.64

Component Tag CSR (COMP_TAG) .......................................................................

195

 

5.65

1x/4x LP Serial Port Maintenance Block Header Register (SP_MB_HEAD)..........................

196

 

5.66

Port Link Time-Out Control CSR (SP_LT_CTL) ..........................................................

197

 

5.67

Port Response Time-Out Control CSR (SP_RT_CTL)...................................................

198

 

5.68

Port General Control CSR (SP_GEN_CTL) ...............................................................

199

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5.69

Port Link Maintenance Request CSR n (SPn_LM_REQ)................................................

200

5.70

Port Link Maintenance Response CSR n (SPn_LM_RESP)............................................

201

5.71

Port Local AckID Status CSR n (SPn_ACKID_STAT) ...................................................

202

5.72

Port Error and Status CSR n (SPn_ERR_STAT) .........................................................

203

5.73

Port Control CSR n (SPn_CTL) .............................................................................

206

5.74

Error Reporting Block Header Register (ERR_RPT_BH)................................................

209

5.75

Logical/Transport Layer Error Detect CSR (ERR_DET) .................................................

210

5.76

Logical/Transport Layer Error Enable CSR (ERR_EN) ..................................................

212

5.77

Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) ..............................

214

5.78

Logical/Transport Layer Address Capture CSR (ADDR_CAPT)........................................

215

5.79

Logical/Transport Layer Device ID Capture CSR (ID_CAPT)...........................................

216

5.80

Logical/Transport Layer Control Capture CSR (CTRL_CAPT) .........................................

217

5.81

Port-Write Target Device ID CSR (PW_TGT_ID).........................................................

218

5.82

Port Error Detect CSR n (SPn_ERR_DET)................................................................

219

5.83

Port Error Rate Enable CSR n (SPn_RATE_EN).........................................................

221

5.84

Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0)............................

223

5.85

Port n Error Capture CSR 1 (SPn_ERR_CAPT_DBG1) .................................................

224

5.86

Port n Error Capture CSR 2 (SPn_ERR_CAPT_DBG2) .................................................

225

5.87

Port n Error Capture CSR 3 (SPn_ERR_CAPT_DBG3) .................................................

226

5.88

Port n Error Capture CSR 4 (SPn_ERR_CAPT_DBG4) .................................................

227

5.89

Port Error Rate CSR n (SPn_ERR_RATE) ................................................................

228

5.90

Port Error Rate Threshold CSR n (SPn_ERR_THRESH) ...............................................

229

5.91

Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) ......................

230

5.92

Port IP Mode CSR (SP_IP_MODE) ........................................................................

231

5.93

Port IP Prescaler Register (IP_PRESCAL) ................................................................

233

5.94

Port-Write-InCapture CSRs(SP_IP_PW_IN_CAPT[0–3]) ..............................................

234

5.95

Port Reset Option CSR n (SPn_RST_OPT)...............................................................

235

5.96

Port Control Independent Register n (SPn_CTL_INDEP)...............................................

236

5.97

Port Silence Timer n Register (SPn_SILENCE_TIMER) ................................................

238

5.98

Port Multicast-EventControl Symbol Request Registern (SPn_MULT_EVNT_CS).................

239

5.99

Port Control Symbol Transmit n Register (SPn_CS_TX)................................................

240

Index ...............................................................................................................................

 

241

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List of Figures

 

1

RapidIO Architectural Hierarchy..........................................................................................

17

 

2

RapidIO Interconnect Architecture .......................................................................................

18

 

3

Serial RapidIO Device to Device Interface Diagrams .................................................................

19

 

4

SRIO Peripheral Block Diagram..........................................................................................

22

 

5

Operation Sequence .......................................................................................................

23

 

6

1x/4x RapidIO Packet Data Stream (Streaming-WriteClass)........................................................

24

 

7

Serial RapidIO Control Symbol Format..................................................................................

24

 

8

SRIO Component Block Diagram ........................................................................................

27

 

9

SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) ...............................................

28

 

10

SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL)...............................

31

 

11

SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL)..............................

33

 

12

Load/Store Registers for RapidIO (Address Offset: LSU1 400h–418h,LSU2420h–438h,LSU3

 

 

440h–458h, LSU4 460h-478h) ...........................................................................................

36

 

13

LSU Registers Timing .....................................................................................................

38

 

14

Example Burst NWRITE_R ...............................................................................................

39

 

15

Load/Store Module Data Flow Diagram .................................................................................

40

 

16

CPPI RX Scheme for RapidIO............................................................................................

44

 

17

Message Request Packet .................................................................................................

45

 

18

Mailbox to Queue Mapping Register Pair ...............................................................................

46

 

19

RX Buffer Descriptor Fields ...............................................................................................

47

 

20

RX CPPI Mode Explanation ..............................................................................................

49

 

21

CPPI Boundary Diagram ..................................................................................................

51

 

22

TX Buffer Descriptor Fields ...............................................................................................

52

 

23

Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh)...................................

56

 

24

RX Buffer Descriptors......................................................................................................

62

 

25

TX Buffer Descriptors ......................................................................................................

63

 

26

Doorbell Operation .........................................................................................................

64

 

27

Flow Control Table Entry Registers (Address Offset 0900h–093Ch) ...............................................

66

 

28

Transmit Source Flow Control Masks ...................................................................................

67

 

29

Fields Within Each Flow Mask............................................................................................

67

 

30

Configuration Bus Example ...............................................................................................

69

 

31

DMA Example ..............................................................................................................

69

 

32

GBL_EN (Address 0030h) ................................................................................................

71

 

33

GBL_EN_STAT (Address 0034h) ........................................................................................

71

 

34

BLK0_EN (Address 0038h) ...............................................................................................

72

 

35

BLK0_EN_STAT (Address 003Ch) ......................................................................................

73

 

36

BLK1_EN (Address 0040h) ...............................................................................................

73

 

37

BLK1_EN_STAT (Address 0044h).......................................................................................

73

 

38

BLK8_EN (Address 0078h) ...............................................................................................

73

 

39

BLK8_EN_STAT (Address 007Ch) ......................................................................................

73

 

40

Peripheral Control Register (PCR) - Address Offset 0004h ..........................................................

74

 

41

Bootload Operation ........................................................................................................

80

 

42

Packet Forwarding Register n for16-BitDevice IDs (PF_16B_CNTLn) Offsets 0x0090, 0x0098, 0x00A0,

 

 

0x00A8.......................................................................................................................

81

 

43

Packet Forwarding Register n for8-BitDevice IDs (PF_8B_CNTLn) Offsets 0x0094, 0x009C, 0x00A4,

 

 

0x00AC ......................................................................................................................

82

 

44

Logical/Transport Layer Error Detect CSR (ERR_DET) ..............................................................

83

 

45

RapidIO DOORBELL Packet for Interrupt Use .........................................................................

85

 

46

Doorbell 0 Interrupt Condition Status and Clear Registers ...........................................................

87

 

47

Doorbell 1 Interrupt Condition Status and Clear Registers ...........................................................

87

 

48

Doorbell 2 Interrupt Condition Status and Clear Registers ...........................................................

88

 

49

Doorbell 3 Interrupt Condition Status and Clear Registers ...........................................................

88

6

List of Figures

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50

RX CPPI Interrupt Condition Status and Clear Registers.............................................................

 

89

51

TX CPPI Interrupt Condition Status and Clear Registers .............................................................

 

89

52

LSU Interrupt Condition Status and Clear Registers ..................................................................

 

90

53

Error, Reset, and Special Event Interrupt Condition Status and Clear Registers .................................

 

91

54

Doorbell 0 Interrupt Condition Routing Registers ......................................................................

 

94

55

RX CPPI Interrupt Condition Routing Registers........................................................................

 

94

56

TX CPPI Interrupt Condition Routing Registers ........................................................................

 

95

57

LSU Interrupt Condition Routing Registers .............................................................................

 

96

58

Error, Reset, and Special Event Interrupt Condition Routing Registers ............................................

 

97

59

Interrupt Status Decode Register (INTDSTn_DECODE) .............................................................

 

98

60

Interrupt Sources Assigned to ISDR Bits ...............................................................................

 

98

61

Example Diagram of Interrupt Status Decode Register Mapping....................................................

 

99

62

INTDSTn_RATE_CNTL Interrupt Rate Control Register ............................................................

 

100

63

Peripheral ID Register (PID) - Address Offset 0000h................................................................

 

111

64

Peripheral Control Register (PCR) - Address Offset 0004h.........................................................

 

112

65

Peripheral Settings Control Register (PER_SET_CNTL) (Address Offset 0020h)...............................

 

113

66

Peripheral Global Enable Register (GBL_EN) (Address Offset 0030h) ...........................................

 

116

67

Peripheral Global Enable Status Register (GBL_EN_STAT) - Address 0034h ..................................

 

117

68

Block n Enable Register (BLKn_EN) ...................................................................................

 

119

69

Block n Enable Status Register (BLKn_EN) ..........................................................................

 

120

70

RapidIO DEVICEID1 Register (DEVICEID_REG1) (Offset 0080h) ................................................

 

121

71

RapidIO DEVICEID2 Register (DEVICEID_REG2) (Offset 0x0084) ...............................................

 

122

72

Packet Forwarding Register n for16-BitDevice IDs (PF_16B_CNTLn)..........................................

 

123

73

Packet Forwarding Register n for8-BitDevice IDs (PF_8B_CNTLn).............................................

 

124

74

SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL).............................

 

125

75

SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL).............................

 

128

76

SERDES Macro Configuration Register n (SERDES_CFGn_CNTL)..............................................

 

130

77

Doorbell n Interrupt Condition Status Register (DOORBELLn_ICSR).............................................

 

132

78

Doorbell n Interrupt Condition Clear Register (DOORBELLn_ICCR)..............................................

 

133

79

RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) - Address Offset 0240h ......................

 

134

80

RX CPPI Interrupt Condition Clear Register (RX_CPPI_ICCR) - Address Offset 0248h .......................

 

135

81

TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) - Address Offset 0250h .......................

 

136

82

TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) - Address Offset 0258h ........................

 

137

83

LSU Interrupt Condition Status Register (LSU_ICSR) - Address Offset 0260h ..................................

 

138

84

LSU Interrupt Condition Clear Register (LSU_ICCR) - Address Offset 0268h ...................................

 

141

85

Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) - Address

 

 

Offset 0270h...............................................................................................................

 

142

86

Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) - Address

 

 

Offset 0278h...............................................................................................................

 

143

87

Doorbell n Interrupt Condition Routing Registers.....................................................................

 

144

88

RX CPPI Interrupt Condition Routing Registers ......................................................................

 

145

89

TX CPPI Interrupt Condition Routing Registers ......................................................................

 

146

90

LSU Interrupt Condition Routing Registers............................................................................

 

147

91

Error, Reset, and Special Event Interrupt Condition Routing Registers ...........................................

 

149

92

Interrupt Status Decode Register (INTDSTn_DECODE) ............................................................

 

150

93

INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL)..............................................

 

154

94

LSUn Control Register 0 (LSUn_REG0)...............................................................................

 

155

95

LSUn Control Register 1 (LSUn_REG1)...............................................................................

 

156

96

LSUn Control Register 2 (LSUn_REG2)...............................................................................

 

157

97

LSUn Control Register 3 (LSUn_REG3)...............................................................................

 

158

98

LSUn Control Register 4 (LSUn_REG4)...............................................................................

 

159

99

LSUn Control Register 5 (LSUn_REG5)...............................................................................

 

160

100

LSUn Control Register 6 (LSUn_REG6)...............................................................................

 

161

101

LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS).........................................

 

162

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102

LSUn FLOW_MASK Fields..............................................................................................

 

162

 

103

Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP)

.........................

164

 

104

Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP).................................

 

165

 

105

Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP)..........................

 

166

 

106

Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP)..................................

 

167

 

107

Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) - Address Offset 0700h...................

168

 

108

Transmit CPPI Supported Flow Mask Registers .....................................................................

 

170

 

109

TX Queue n FLOW_MASK Fields ......................................................................................

 

170

 

110

Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) (Address Offset 0740h) ...................

172

 

111

Receive CPPI Control Register (RX_CPPI_CNTL) (Address Offset 0744h)......................................

 

173

 

112

Transmit CPPI Weighted Round Robin Control Registers ..........................................................

 

174

 

113

Mailbox to Queue Mapping Register Pair .............................................................................

 

179

 

114

Flow Control Table Entry Register n (FLOW_CNTLn)...............................................................

 

181

 

115

Device Identity CAR (DEV_ID) - Address Offset 1000h .............................................................

 

182

 

116

Device Information CAR (DEV_INFO) - Address Offset 1004h ....................................................

 

183

 

117

Assembly Identity CAR (ASBLY_ID) - Address Offset 1008h ......................................................

 

184

 

118

Assembly Information CAR (ASBLY_INFO) - Address Offset 100Ch .............................................

 

185

 

119

Processing Element Features CAR (PE_FEAT) - Address Offset 1010h .........................................

 

186

 

120

Source Operations CAR (SRC_OP) - Address Offset 1018h.......................................................

 

188

 

121

Destination Operations CAR (DEST_OP) - Address Offset 101Ch ................................................

 

189

 

122

Processing Element Logical Layer Control CSR (PE_LL_CTL) - Address Offset 104Ch .......................

190

 

123

Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) - Address Offset 1058h................

191

 

124

Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) - Address Offset 105Ch .................

192

 

125

Base Device ID CSR (BASE_ID) - Address Offset 1060h ..........................................................

 

193

 

126

Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) - Address Offset 1068h............................

 

194

 

127

Component Tag CSR (COMP_TAG) - Address Offset 106Ch .....................................................

 

195

 

128

1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) - Address Offset 1100h ........

196

 

129

Port Link Time-OutControl CSR (SP_LT_CTL) - Address Offset 1120h.........................................

 

197

 

130

Port Response Time-OutControl CSR (SP_RT_CTL) - Address Offset 1124h..................................

 

198

 

131

Port General Control CSR (SP_GEN_CTL) - Address Offset 113Ch..............................................

 

199

 

132

Port Link Maintenance Request CSR n (SPn_LM_REQ) ...........................................................

 

200

 

133

Port Link Maintenance Response CSR n (SPn_LM_RESP)........................................................

 

201

 

134

Port Local AckID Status CSR n (SPn_ACKID_STAT) ...............................................................

 

202

 

135

Port Error and Status CSR n (SPn_ERR_STAT).....................................................................

 

203

 

136

Port Control CSR n (SPn_CTL).........................................................................................

 

206

 

137

Error Reporting Block Header Register (ERR_RPT_BH) - Address Offset 2000h...............................

 

209

 

138

Logical/Transport Layer Error Detect CSR (ERR_DET) - Address Offset 2008h ................................

 

210

 

139

Logical/Transport Layer Error Enable CSR (ERR_EN) - Address Offset 200Ch.................................

 

212

 

140

Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) - Address Offset 2010h.............

214

 

141

Logical/Transport Layer Address Capture CSR (ADDR_CAPT) - Address Offset 2014h.......................

215

 

142

Logical/Transport Layer Device ID Capture CSR (ID_CAPT) - Address Offset 2018h..........................

 

216

 

143

Logical/Transport Layer Control Capture CSR (CTRL_CAPT) - Address Offset 201Ch ........................

217

 

144

Port-WriteTarget Device ID CSR (PW_TGT_ID) - Address Offset 2028h........................................

 

218

 

145

Port Error Detect CSR n (SPn_ERR_DET) ...........................................................................

 

219

 

146

Port Error Rate Enable CSR n (SPn_RATE_EN) ....................................................................

 

221

 

147

Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0)........................................

 

223

 

148

Port n Error Capture CSR 1 (SPn_ERR_CAPT_DBG1).............................................................

 

224

 

149

Port n Error Capture CSR 2 (SPn_ERR_CAPT_DBG2).............................................................

 

225

 

150

Port n Error Capture CSR 3 (SPn_ERR_CAPT_DBG3).............................................................

 

226

 

151

Port n Error Capture CSR 4 (SPn_ERR_CAPT_DBG4).............................................................

 

227

 

152

Port Error Rate CSR n (SPn_ERR_RATE)............................................................................

 

228

 

153

Port Error Rate Threshold CSR n (SPn_ERR_THRESH) ...........................................................

 

229

 

154

Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) - Address Offset 12000h ....

230

8

List of Figures

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155

Port IP Mode CSR (SP_IP_MODE) - Address Offset 12004h ......................................................

231

156

Port IP Prescaler Register (IP_PRESCAL) - Address Offset 12008h .............................................

233

157

Port-Write-In Capture CSRs.............................................................................................

234

158

Port Reset Option CSR n (SPn_RST_OPT) ..........................................................................

235

159

Port Control Independent Register n (SPn_CTL_INDEP)...........................................................

236

160

Port Silence Timer n Register (SPn_SILENCE_TIMER) ............................................................

238

161

Port Multicast-EventControl Symbol Request Registern (SPn_MULT_EVNT_CS)............................

239

162

Port Control Symbol Transmit n Register (SPn_CS_TX)............................................................

240

SPRUE13A –September2006

List of Figures

9

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List of Tables

 

1

TI Devices Supported By This Document...............................................................................

 

20

 

2

Registers Checked for Multicast DeviceID..............................................................................

 

21

 

3

Packet Types ...............................................................................................................

 

25

 

4

Pin Description..............................................................................................................

 

26

 

5

SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) Field Descriptions .........................

29

 

6

Line Rate versus PLL Output Clock Frequency........................................................................

 

30

 

7

Effect of the RATE Bits ....................................................................................................

 

30

 

8

Frequency Range versus MPY Value ...................................................................................

 

30

 

9

SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field Descriptions........

31

 

10

EQ Bits.......................................................................................................................

 

33

 

11

SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Field Descriptions........

33

 

12

DE Bits of SERDES_CFGTXn_CNTL ...................................................................................

 

34

 

13

SWING Bits of SERDES_CFGTXn_CNTL..............................................................................

 

35

 

14

LSU Control/Command Register Fields .................................................................................

 

36

 

15

LSU Status Register Fields ...............................................................................................

 

37

 

16

RX DMA State Head Descriptor Pointer (HDP) (Address Offset 600h–63Ch).....................................

 

46

 

17

RX DMA State Completion Pointer (CP) (Address Offset 680h–6BCh) ............................................

 

46

 

18

RX Buffer Descriptor Field Descriptions.................................................................................

 

47

 

19

TX DMA State Head Descriptor Pointer (HDP) (Address Offset 500h–53Ch) .....................................

 

51

 

20

TX DMA State Completion Pointer (CP) (Address Offset 58h–5BCh) ..............................................

 

52

 

21

TX Buffer Descriptor Field Definitions ...................................................................................

 

52

 

22

Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh)...................................

 

56

 

23

Examples of DOORBELL_INFO Designations (See Figure 26 ).....................................................

 

64

 

24

Flow Control Table Entry Register n (FLOW_CNTLn) Field Descriptions..........................................

 

67

 

25

Fields Within Each Flow Mask............................................................................................

 

68

 

26

Reset Hierarchy ............................................................................................................

 

70

 

27

Global Enable and Global Enable Status Field Descriptions .........................................................

 

72

 

28

Block Enable and Block Enable Status Field Descriptions ...........................................................

 

73

 

29

Peripheral Control Register (PCR) Field Descriptions.................................................................

 

74

 

30

Port Mode Register Settings ..............................................................................................

 

77

 

31

Multicast DeviceID Operation.............................................................................................

 

81

 

32

Packet Forwarding Register n for16-BitDeviceIDs (PF_16B_CNTLn) Field Descriptions......................

81

 

33

Packet Forwarding Register n for8-BitDeviceIDs (PF_8B_CNTLn) Field Descriptions.........................

82

 

34

Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions ........................................

 

83

 

35

Interrupt Condition Status and Clear Bits ...............................................................................

 

87

 

36

Interrupt Conditions Shown in LSU_ICSR and Cleared With LSU_ICCR ..........................................

 

90

 

37

Interrupt Conditions Shown in ERR_RST_EVNT_ICSR and Cleared With ERR_RST_EVNT_ICCR ..........

91

 

38

Interrupt Clearing Sequence for Special Event Interrupts ............................................................

 

92

 

39

Interrupt Condition Routing Options .....................................................................................

 

93

 

40

Serial RapidIO (SRIO) Registers .......................................................................................

 

102

 

41

Peripheral ID Register (PID) Field Descriptions ......................................................................

 

111

 

42

Peripheral Control Register (PCR) Field Descriptions ...............................................................

 

112

 

43

Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions .....................................

 

113

 

44

Peripheral Global Enable Register (GBL_EN) Field Descriptions..................................................

 

116

 

45

Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions .................................

 

117

 

46

Block n Enable Registers and the Associated Blocks ...............................................................

 

119

 

47

Block n Enable Register (BLKn_EN) Field Descriptions.............................................................

 

119

 

48

Block n Enable Status Registers and the Associated Blocks.......................................................

 

120

 

49

Block n Enable Status Register (BLKn_EN_STAT) Field Descriptions............................................

 

120

10

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50

RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions ............................................

 

121

51

RapidIO DEVICEID2 Register (DEVICEID_REG2) Field Descriptions ............................................

 

122

52

PF_16B_CNTL Registers................................................................................................

 

123

53

Packet Forwarding Register n for16-BitDeviceIDs (PF_16B_CNTLn) Field Descriptions.....................

 

123

54

PF_8B_CNTL Registers .................................................................................................

 

124

55

Packet Forwarding Register n for8-BitDeviceIDs (PF_8B_CNTLn) Field Descriptions........................

 

124

56

SERDES_CFGRXn_CNTL Registers and the Associated Ports...................................................

 

125

57

SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field Descriptions.......

125

58

EQ Bits .....................................................................................................................

 

126

59

SERDES_CFGTXn_CNTL Registers and the Associated Ports...................................................

 

128

60

SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Field Descriptions......

128

61

DE Bits of SERDES_CFGTXn_CNTL..................................................................................

 

129

62

SWING Bits of SERDES_CFGTXn_CNTL ............................................................................

 

129

63

SERDES_CFGn_CNTL Registers and the Associated Ports.......................................................

 

130

64

SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) Field Descriptions........................

 

130

65

DOORBELLn_ICSR Registers ..........................................................................................

 

132

66

DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR) Field Descriptions...................

 

132

67

DOORBELLn_ICCR Registers..........................................................................................

 

133

68

DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR) Field Descriptions....................

 

133

69

RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) Field Descriptions.............................

 

134

70

RX CPPI Interrupt Condition Clear Register (RX_CPPI_ICCR) Field Descriptions..............................

 

135

71

TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) Field Descriptions .............................

 

136

72

TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) Field Descriptions ..............................

 

137

73

LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions.........................................

 

138

74

LSU Interrupt Condition Clear Register (LSU_ICCR) Field Descriptions..........................................

 

141

75

Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) Field

 

 

Descriptions ...............................................................................................................

 

142

76

Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) Field

 

 

Descriptions ...............................................................................................................

 

143

77

DOORBELLn_ICRR Registers..........................................................................................

 

144

78

DOORBELLn Interrupt Condition Routing Register Field Descriptions............................................

 

144

79

RX CPPI Interrupt Condition Routing Register Field Descriptions .................................................

 

145

80

TX CPPI Interrupt Condition Routing Register Field Descriptions .................................................

 

146

81

LSU Interrupt Condition Routing Register Field Descriptions.......................................................

 

148

82

Error, Reset, and Special Event Interrupt Condition Routing Register Field Descriptions ......................

 

149

83

INTDSTn_DECODE Registers and the Associated Interrupt Destinations.......................................

 

150

84

Interrupt Status Decode Register (INTDSTn_DECODE) Field Descriptions......................................

 

150

85

INTDSTn_RATE_CNTL Registers and the Associated Interrupt Destinations...................................

 

154

86

INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL) Field Descriptions........................

 

154

87

LSUn_REG0 Registers and the Associated LSUs ...................................................................

 

155

88

LSUn Control Register 0 (LSUn_REG0) Field Descriptions ........................................................

 

155

89

LSUn_REG1 Registers and the Associated LSUs ...................................................................

 

156

90

LSUn Control Register 1 (LSUn_REG1) Field Descriptions ........................................................

 

156

91

LSUn_REG2 Registers and the Associated LSUs ...................................................................

 

157

92

LSUn Control Register 2 (LSUn_REG2) Field Descriptions ........................................................

 

157

93

LSUn_REG3 Registers and the Associated LSUs ...................................................................

 

158

94

LSUn Control Register 3 (LSUn_REG3) Field Descriptions ........................................................

 

158

95

LSUn_REG4 Registers and the Associated LSUs ...................................................................

 

159

96

LSUn Control Register 4 (LSUn_REG4) Field Descriptions ........................................................

 

159

97

LSUn_REG5 Registers and the Associated LSUs ...................................................................

 

160

98

LSUn Control Register 5 (LSUn_REG5) Field Descriptions ........................................................

 

160

SPRUE13A –September2006

List of Tables

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99

LSUn_REG6 Registers and the Associated LSUs ...................................................................

 

161

 

100

LSUn Control Register 6 (LSUn_REG6) Field Descriptions ........................................................

 

161

 

101

LSUn_FLOW_MASKS Registers and the Associated LSUs........................................................

 

162

 

102

LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS) Field Descriptions...................

162

 

103

LSUn FLOW_MASK Fields..............................................................................................

 

162

 

104

QUEUEn_TXDMA_HDP Registers .....................................................................................

 

164

 

105

Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) Field Descriptions...

164

 

106

QUEUEn_TXDMA_CP Registers.......................................................................................

 

165

 

107

Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) Field Descriptions............

165

 

108

QUEUEn_RXDMA_HDP Registers.....................................................................................

 

166

 

109

Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP) Field Descriptions...

166

 

110

QUEUEn_RXDMA_CP Registers ......................................................................................

 

167

 

111

Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP) Field Descriptions...........

167

 

112

Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Field Descriptions .........................

168

 

113

TX_CPPI_FLOW_MASKS Registers and the Associated TX Queues ............................................

 

169

 

114

TX Queue n FLOW_MASK Field Descriptions........................................................................

 

170

 

115

Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Field Descriptions

.........................

172

 

116

Receive CPPI Control Register (RX_CPPI_CNTL) Field Descriptions ............................................

 

173

 

117

Transmit CPPI Weighted Round Robin Control Register Field Descriptions .....................................

 

175

 

118

Mailbox to Queue Mapping Registers and the Associated RX Mappers ..........................................

 

177

 

119

Mailbox-to-QueueMapping Register Ln (RXU_MAP_Ln) Field Descriptions.....................................

 

179

 

120

Mailbox-to-QueueMapping Register Hn (RXU_MAP_Hn) Field Descriptions....................................

 

179

 

121

FLOW_CNTLn Registers ................................................................................................

 

181

 

122

Flow Control Table Entry Register n (FLOW_CNTLn) Field Descriptions........................................

 

181

 

123

Device Identity CAR (DEV_ID) Field Descriptions ...................................................................

 

182

 

124

Device Information CAR (DEV_INFO) Field Descriptions ...........................................................

 

183

 

125

Assembly Identity CAR (ASBLY_ID) Field Descriptions.............................................................

 

184

 

126

Assembly Information CAR (ASBLY_INFO) Field Descriptions ....................................................

 

185

 

127

Processing Element Features CAR (PE_FEAT) Field Descriptions ...............................................

 

186

 

128

Source Operations CAR (SRC_OP) Field Descriptions .............................................................

 

188

 

129

Destination Operations CAR (DEST_OP) Field Descriptions.......................................................

 

189

 

130

Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions..............................

 

190

 

131

Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Field Descriptions ......................

191

 

132

Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Field Descriptions ........................

192

 

133

Base Device ID CSR (BASE_ID) Field Descriptions.................................................................

 

193

 

134

Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) Field Descriptions ..................................

 

194

 

135

Component Tag CSR (COMP_TAG) Field Descriptions ............................................................

 

195

 

136

1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) Field Descriptions ..............

196

 

137

Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions .................................................

 

197

 

138

Port Response Time-OutControl CSR (SP_RT_CTL) Field Descriptions........................................

 

198

 

139

Port General Control CSR (SP_GEN_CTL) Field Descriptions ....................................................

 

199

 

140

SPn_LM_REQ Registers and the Associated Ports .................................................................

 

200

 

141

Port Link Maintenance Request CSR n (SPn_LM_REQ) Field Descriptions.....................................

 

200

 

142

SPn_LM_RESP Registers and the Associated Ports ................................................................

 

201

 

143

Port Link Maintenance Response CSR n (SPn_LM_RESP) Field Descriptions.................................

 

201

 

144

SPn_ACKID_STAT Registers and the Associated Ports ............................................................

 

202

 

145

Port Local AckID Status CSR n (SPn_ACKID_STAT) Field Descriptions.........................................

 

202

 

146

SPn_ERR_STAT Registers and the Associated Ports ..............................................................

 

203

 

147

Port Error and Status CSR n (SPn_ERR_STAT) Field Descriptions..............................................

 

203

 

148

SPn_CTL Registers and the Associated Ports .......................................................................

 

206

 

149

Port Control CSR n (SPn_CTL) Field Descriptions ..................................................................

 

206

12

List of Tables

SPRUE13A –September2006

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150

Error Reporting Block Header Register (ERR_RPT_BH) Field Descriptions .....................................

209

151

Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions ......................................

210

152

Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions .......................................

212

153

Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Field Descriptions ...................

214

154

Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Field Descriptions .............................

215

155

Logical/Transport Layer Device ID Capture CSR (ID_CAPT) Field Descriptions ................................

216

156

Logical/Transport Layer Control Capture CSR (CTRL_CAPT) Field Descriptions ...............................

217

157

Port-WriteTarget Device ID CSR (PW_TGT_ID) Field Descriptions..............................................

218

158

SPn_ERR_DET Registers and the Associated Ports ................................................................

219

159

Port Error Detect CSR n (SPn_ERR_DET) Field Descriptions.....................................................

219

160

SPn_RATE_EN Registers and the Associated Ports ................................................................

221

161

Port Error Rate Enable CSR n (SPn_RATE_EN) Field Descriptions..............................................

221

162

SPn_ERR_ATTR_CAPT_DBG0 Registers and the Associated Ports.............................................

223

163

Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0) Field Descriptions.................

223

164

SPn_ERR_CAPT_DBG1 Registers and the Associated Ports .....................................................

224

165

Port n Error Capture CSR 1 (SPn_ERR_CAPT_DBG1) Field Descriptions......................................

224

166

SPn_ERR_CAPT_DBG2 Registers and the Associated Ports .....................................................

225

167

Port n Error Capture CSR 2 (SPn_ERR_CAPT_DBG2) Field Descriptions......................................

225

168

SPn_ERR_CAPT_DBG3 Registers and the Associated Ports .....................................................

226

169

Port n Error Capture CSR 3 (SPn_ERR_CAPT_DBG3) Field Descriptions......................................

226

170

SPn_ERR_CAPT_DBG4 Registers and the Associated Ports .....................................................

227

171

Port n Error Capture CSR 4 (SPn_ERR_CAPT_DBG4) Field Descriptions......................................

227

172

SPn_ERR_RATE Registers and the Associated Ports ..............................................................

228

173

Port Error Rate CSR n (SPn_ERR_RATE) Field Descriptions.....................................................

228

174

SPn_ERR_THRESH Registers and the Associated Ports ..........................................................

229

175

Port Error Rate Threshold CSR n (SPn_ERR_THRESH) Field Descriptions.....................................

229

176

Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) Field Descriptions............

230

177

Port IP Mode CSR (SP_IP_MODE) Field Descriptions..............................................................

231

178

Port IP Prescaler Register (IP_PRESCAL) Field Descriptions .....................................................

233

179

Port-Write-In Capture CSR Field Descriptions........................................................................

234

180

SPn_RST_OPT Registers and the Associated Ports ................................................................

235

181

Port Reset Option CSR n (SPn_RST_OPT) Field Descriptions....................................................

235

182

SPn_CTL_INDEP Registers and the Associated Ports..............................................................

236

183

Port Control Independent Register n (SPn_CTL_INDEP) Field Descriptions....................................

236

184

SPn_SILENCE_TIMER Registers and the Associated Ports .......................................................

238

185

Port Silence Timer n Register (SPn_SILENCE_TIMER) Field Descriptions......................................

238

186

SPn_MULT_EVNT_CS Registers and the Associated Ports .......................................................

239

187

Port Multicast-EventControl Symbol Request Registern (SPn_MULT_EVNT_CS) Field Descriptions......

239

188

SPn_CS_TX Registers and the Associated Ports....................................................................

240

189

Port Control Symbol Transmit n Register (SPn_CS_TX) Field Descriptions.....................................

240

SPRUE13A –September2006

List of Tables

13

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