Texas Instruments TMS320DM646X DMSOC User Manual

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Table 34. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions (continued)

Bit

Field

Value

Description

 

 

 

 

17-16

CS2_WAIT

0-3h

EM_WAIT[5:2] pin map for chip select 2. By default, the EM_WAIT[2] pin is used for chip select 2.

 

 

0

EM_WAIT[2] pin is used.

 

 

1h

EM_WAIT[3] pin is used.

 

 

2h

EM_WAIT[4] pin is used.

 

 

3h

EM_WAIT[5] pin is used.

 

 

 

 

15-8

Reserved

0

Reserved

 

 

 

 

7-0

MEWC

0-FFh

Maximum extended wait cycles. The EMIF will wait for a maximum of (MEWC + 1) × 16 clock cycles

 

 

 

before it stops inserting asynchronous wait cycles and proceeds to the hold period of the access.

 

 

 

 

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4.3Asynchronous n Configuration Registers (A1CR-A4CR)

The asynchronous configuration register (ACFGn) is used to configure the shaping of the address and control signals during an access to asynchronous memory. It is also used to program the width of asynchronous interface and to select from various modes of operation. This register can be written prior to any transfer, and any asynchronous transfer following the write will use the new configuration. The ACFGn is shown inFigure 22 and described inTable 35. There are four ACFGns. Each chip select space has a dedicated ACFGn. This allows each chip select space to be programmed independently to interface to different asynchronous memory types.

Figure 22. Asynchronous n Configuration Register (ACFGn)

31

 

30

29

 

 

 

 

26

25

 

24

 

SS

 

EW(A)

 

 

W_SETUP

 

 

 

W_STROBE(B)

 

R/W-0

R/W-0

 

 

R/W-Fh

 

 

 

 

R/W-3Fh

 

23

 

 

 

 

 

20

 

19

 

17

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W_STROBE(B)

 

 

 

 

W_HOLD

 

 

R_SETUP

 

 

 

 

R/W-3Fh

 

 

 

 

R/W-7h

 

 

R/W-Fh

15

 

13

 

12

 

7

6

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R_SETUP

 

 

 

R_STROBE(B)

 

 

 

 

R_HOLD

TA

 

ASIZE

 

R/W-Fh

 

 

 

R/W-3Fh

 

 

 

 

R/W-7h

R/W-3h

 

R/W-0

 

LEGEND: R/W = Read/Write; -n = value after reset

A.The EW bit must be cleared to 0 when operating in NAND Flash mode.

B.The W_STROBE and R_STROBE bits must not be cleared to 0 when operating in Extended Wait mode.

Table 35. Asynchronous n Configuration Register (ACFGn) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

31

SS

 

Select Strobe bit. This bit defines whether the asynchronous interface operates in Normal mode or

 

 

 

Select Strobe mode. See Section 2.5 for details on the two modes of operation.

 

 

0

Normal mode is enabled.

 

 

1

Select Strobe mode is enabled.

 

 

 

 

30

EW

 

Extend Wait enable bit. This bit enables extended wait cycles. See Section 2.5.8 on extended wait

 

 

 

cycles for details. This bit must be cleared to 0, if the EMIF on your device does not have a

 

 

 

EM_WAIT pin.

 

 

0

Extended wait cycles are disabled.

 

 

1

Extended wait cycles are enabled.

 

 

 

 

29-26

W_SETUP

0-Fh

Write setup width in EMIF clock cycles, minus 1 cycle. See Section 2.5.3 for details.

 

 

 

 

25-20

W_STROBE

0-3Fh

Write strobe width in EMIF clock cycles, minus 1 cycle. See Section 2.5.3 for details.

 

 

 

 

19-17

W_HOLD

0-7h

Write hold width in EMIF clock cycles, minus 1 cycle. See Section 2.5.3 for details.

 

 

 

 

16-13

R_SETUP

0-Fh

Read setup width in EMIF clock cycles, minus 1 cycle. See Section 2.5.3 for details.

 

 

 

 

12-7

R_STROBE

0-3Fh

Read strobe width in EMIF clock cycles, minus 1 cycle. See Section 2.5.3 for details.

 

 

 

 

6-4

R_HOLD

0-7h

Read hold width in EMIF clock cycles, minus 1 cycle. See Section 2.5.3 for details.

 

 

 

 

3-2

TA

0-3h

Minimum Turn-Aroundtime. This field defines the minimum number of EMIF clock cycles between

 

 

 

the end of one asynchronous access and the start of another, minus 1 cycle. This delay is not

 

 

 

incurred by a read followed by a read or a write followed by a write to the same CS space. See

 

 

 

Section 2.5.3 for details.

 

 

 

 

1-0

ASIZE

0-3h

Asynchronous data bus width. This bit defines the width of the asynchronous device's data bus.

 

 

0

8-bitdata bus

 

 

1h

16-bitdata bus

 

 

2h-3h

Reserved

 

 

 

 

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4.4EMIF Interrupt Raw Register (EIRR)

The EMIF interrupt raw register (EIRR) is used to monitor and clear the EMIF’s hardware-generatedinterrupts. The bits in EIRR are set when an interrupt condition occurs, regardless of the status of the EMIF interrupt mask set register (EIMSR) and EMIF interrupt mask clear register (EIMCR). Writing a 1 to a bit clears the bit and the corresponding bit in the EMIF interrupt mask register (EIMR). The EIRR is shown inFigure 23 and described inTable 36.

 

 

Figure 23. EMIF Interrupt Raw Register (EIRR)

 

 

31

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

R-0

 

 

 

15

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

R-0

 

 

 

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

Reserved

WR3

WR2

 

WR1

WR0

Reserved

AT

 

 

 

 

 

 

 

 

 

 

R-0

R/W1C-0

R/W1C-0

 

R/W1C-0

R/W1C-0

R-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset

Table 36. EMIF Interrupt Raw Register (EIRR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

 

 

31-6

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

 

value of 0.

 

 

 

 

 

 

5

WR3

 

Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EM_WAIT[5] pin has

 

 

 

 

occurred.

 

 

 

0

Indicates that a rising edge has not occurred on the EM_WAIT[5] pin. Writing a 0 has no effect.

 

 

 

1

Indicates that a rising edge has occurred on the EM_WAIT[5] pin. Writing a 1 will clear this bit and the

 

 

 

 

WRM3 bit in the EMIF interrupt mask register (EIMR).

 

 

 

 

 

 

4

WR2

 

Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EM_WAIT[4] pin has

 

 

 

 

occurred.

 

 

 

0

Indicates that a rising edge has not occurred on the EM_WAIT[4] pin. Writing a 0 has no effect.

 

 

 

1

Indicates that a rising edge has occurred on the EM_WAIT[4] pin. Writing a 1 will clear this bit and the

 

 

 

 

WRM2 bit in the EMIF interrupt mask register (EIMR).

 

 

 

 

 

 

3

WR1

 

Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EM_WAIT[3] pin has

 

 

 

 

occurred.

 

 

 

0

Indicates that a rising edge has not occurred on the EM_WAIT[3] pin. Writing a 0 has no effect.

 

 

 

1

Indicates that a rising edge has occurred on the EM_WAIT[3] pin. Writing a 1 will clear this bit and the

 

 

 

 

WRM1 bit in the EMIF interrupt mask register (EIMR).

 

 

 

 

 

 

2

WR0

 

Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EM_WAIT[0] pin has

 

 

 

 

occurred.

 

 

 

0

Indicates that a rising edge has not occurred on the EM_WAIT[0] pin. Writing a 0 has no effect.

 

 

 

1

Indicates that a rising edge has occurred on the EM_WAIT[0] pin. Writing a 1 will clear this bit and the

 

 

 

 

WRM0 bit in the EMIF interrupt mask register (EIMR).

 

 

 

 

 

 

1

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

 

value of 0.

 

 

 

 

 

 

0

AT

 

Asynchronous Timeout. This bit is set to 1 by hardware to indicate that during an extended

 

 

 

 

asynchronous memory access cycle the EM_WAITn pin did not go inactive within the number of cycles

 

 

 

defined by the MEWC field in the asynchronous wait cycle configuration register (AWCCR).

 

 

 

0

Indicates that an asynchronous timeout has not occurred. Writing a 0 has no effect.

 

 

 

1

Indicates that an asynchronous timeout has occurred. Writing a 1 will clear this bit and the ATM bit in

 

 

 

 

the EMIF interrupt mask register (EIMR).

 

 

 

 

 

 

 

 

 

 

 

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4.5EMIF Interrupt Mask Register (EIMR)

Similar to the EMIF interrupt raw register (EIRR), the EMIF interrupt mask register (EIMR) is used to monitor and clear the status of the EMIF’s hardware-generatedinterrupts. The main difference between the two registers is that when the bits in EIMR are set, anactive-highpulse is sent to the CPU interrupt controller. Also, the bits in EIMR are only set to 1, if the associated interrupt has been enabled in the EMIF interrupt mask set register (EIMSR). The EIMR is shown inFigure 24 and described inTable 37.

 

 

Figure 24. EMIF Interrupt Mask Register (EIMR)

 

 

31

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

R-0

 

 

 

 

15

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

R-0

 

 

 

 

7

6

5

4

3

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

Reserved

WRM3

WRM2

 

WRM1

WRM0

 

Reserved

ATM

 

 

 

 

 

 

 

 

 

 

 

R-0

R/W1C-0

R/W1C-0

 

R/W1C-0

R/W1C-0

R-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset

Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

31-6

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

value of 0.

 

 

 

 

5

WRM3

 

Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the

 

 

 

EM_WAIT[5] pin, provided that the WRMSET3 bit is set to 1 in the EMIF interrupt mask set register

 

 

 

(EIMSR).

 

 

0

Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.

 

 

1

Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM3 bit in

 

 

 

the EMIF interrupt raw register (EIRR).

 

 

 

 

4

WRM2

 

Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the

 

 

 

EM_WAIT[4] pin, provided that the WRMSET2 bit is set to 1 in the EMIF interrupt mask set register

 

 

 

(EIMSR).

 

 

0

Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.

 

 

1

Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM2 bit in

 

 

 

the EMIF interrupt raw register (EIRR).

 

 

 

 

3

WRM1

 

Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the

 

 

 

EM_WAIT[3] pin, provided that the WRMSET1 bit is set to 1 in the EMIF interrupt mask set register

 

 

 

(EIMSR).

 

 

0

Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.

 

 

1

Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM1 bit in

 

 

 

the EMIF interrupt raw register (EIRR).

 

 

 

 

2

WRM0

 

Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the

 

 

 

EM_WAIT[2] pin, provided that the WRMSET0 bit is set to 1 in the EMIF interrupt mask set register

 

 

 

(EIMSR).

 

 

0

Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.

 

 

1

Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM0 bit in

 

 

 

the EMIF interrupt raw register (EIRR).

 

 

 

 

1

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

value of 0.

 

 

 

 

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Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions (continued)

Bit

Field

Value

Description

 

 

 

 

0

ATM

 

Asynchronous Timeout Masked. This bit is set to 1 by hardware to indicate that during an extended

 

 

 

asynchronous memory access cycle the EM_WAITn pin did not go inactive within the number of cycles

 

 

 

defined by the MEWC field in the asynchronous wait cycle configuration register (AWCCR), provided

 

 

 

that the ATMSET bit is set to 1 in the EMIF interrupt mask set register (EIMSR).

 

 

0

Indicates that an asynchronous timeout interrupt has not been generated. Writing a 0 has no effect.

 

 

1

Indicates that an asynchronous timeout interrupt has been generated. Writing a 1 will clear this bit and

 

 

 

the AT bit in the EMIF interrupt raw register (EIRR).

 

 

 

 

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4.6EMIF Interrupt Mask Set Register (EIMSR)

The EMIF interrupt mask set register (EIMSR) is used to enable the interrupts. If a bit is set to 1, the corresponding bit in the EMIF interrupt mask register (EIMR) is set and an interrupt is generated when the associated interrupt condition occurs. If a bit is cleared to 0, the the corresponding bit in EIMR will always read 0 and no interrupts are generated when the associated interrupt condition occurs. Writing a 1 to the WRMSETn and ATMSET bits enables each respective interrupt. The EIMSR is shown inFigure 25 and described inTable 38.

 

 

Figure 25. EMIF Interrupt Mask Set Register (EIMSR)

 

 

31

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R-0

 

 

 

 

15

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R-0

 

 

 

 

7

6

5

4

3

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

Reserved

WRMSET3

WRMSET2

 

WRMSET1

WRMSET0

 

Reserved

ATMSET

 

R-0

R/W1S-0

R/W1S-0

 

R/W1S-0

R/W1S-0

R-0

R/W1S-0

LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing 0 has no effect); -n = value after reset

Table 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

31-6

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

value of 0.

 

 

 

 

5

WRMSET3

 

Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the

 

 

 

WRMCLR3 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To

 

 

 

clear this bit, a 1 must be written to the WRMCLR3 bit in EIMCR.

 

 

0

Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR3 bit in

 

 

 

EIMCR.

 

 

 

 

4

WRMSET2

 

Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the

 

 

 

WRMCLR2 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To

 

 

 

clear this bit, a 1 must be written to the WRMCLR2 bit in EIMCR.

 

 

0

Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR2 bit in

 

 

 

EIMCR.

 

 

 

 

3

WRMSET1

 

Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the

 

 

 

WRMCLR1 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To

 

 

 

clear this bit, a 1 must be written to the WRMCLR1 bit in EIMCR.

 

 

0

Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR1 bit in

 

 

 

EIMCR.

 

 

 

 

2

WRMSET0

 

Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the

 

 

 

WRMCLR0 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To

 

 

 

clear this bit, a 1 must be written to the WRMCLR0 bit in EIMCR.

 

 

0

Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR0 bit in

 

 

 

EIMCR.

 

 

 

 

1

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

value of 0.

 

 

 

 

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Table 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions (continued)

Bit

Field

Value

Description

 

 

 

 

0

ATMSET

 

Asynchronous Timeout Mask Set. This bit enables the asynchronous timeout interrupt. Writing a 1 to

 

 

 

this bit sets this bit and the ATMCLR bit in the EMIF interrupt mask clear register (EIMCR), and enables

 

 

 

the asynchronous timeout interrupt. To clear this bit, a 1 must be written to the ATMCLR bit in EIMCR.

 

 

0

Indicates that the asynchronous timeout interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the asynchronous timeout interrupt is enabled. Writing a 1 sets this bit and the ATMCLR

 

 

 

bit in EIMCR.

 

 

 

 

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4.7EMIF Interrupt Mask Clear Register (EIMCR)

The EMIF interrupt mask clear register (EIMCR) is used to disable the interrupts. If a bit is read as 1, the corresponding bit in the EMIF interrupt mask register (EIMR) is set and an interrupt is generated when the associated interrupt condition occurs. If a bit is read as 0, the corresponding bit in EIMR will always read 0 and no interrupts are generated when the corresponding interrupt condition occurs. Writing a 1 to the WRMCLRn and ATMCLR bits disables each respective interrupt. The EIMCR is shown inFigure 26 and described inTable 39.

 

 

Figure 26. EMIF Interrupt Mask Clear Register (EIMCR)

 

31

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R-0

 

 

 

15

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R-0

 

 

 

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

Reserved

WRMCLR3

WRMCLR2

 

WRMCLR1

WRMCLR0

Reserved

ATMCLR

 

R-0

R/W1C-0

R/W1C-0

 

R/W1C-0

R/W1C-0

R-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset

Table 39. EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

31-6

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

value of 0.

 

 

 

 

5

WRMCLR3

 

Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. Writing a 1

 

 

 

to this bit clears this bit and the WRMSET3 bit in the EMIF interrupt mask set register (EIMSR), and

 

 

 

disables the wait rise interrupt. To set this bit, a 1 must be written to the WRMSET3 bit in EIMSR.

 

 

0

Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the wait rise interrupt is enabled. Writing a 1 clears this bit and the WRMSET3 bit in

 

 

 

EIMSR.

 

 

 

 

4

WRMCLR2

 

Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. Writing a 1

 

 

 

to this bit clears this bit and the WRMSET2 bit in the EMIF interrupt mask set register (EIMSR), and

 

 

 

disables the wait rise interrupt. To set this bit, a 1 must be written to the WRMSET2 bit in EIMSR.

 

 

0

Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the wait rise interrupt is enabled. Writing a 1 clears this bit and the WRMSET2 bit in

 

 

 

EIMSR.

 

 

 

 

3

WRMCLR1

 

Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. Writing a 1

 

 

 

to this bit clears this bit and the WRMSET1 bit in the EMIF interrupt mask set register (EIMSR), and

 

 

 

disables the wait rise interrupt. To set this bit, a 1 must be written to the WRMSET1 bit in EIMSR.

 

 

0

Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the wait rise interrupt is enabled. Writing a 1 clears this bit and the WRMSET1 bit in

 

 

 

EIMSR.

 

 

 

 

2

WRMCLR0

 

Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. Writing a 1

 

 

 

to this bit clears this bit and the WRMSET0 bit in the EMIF interrupt mask set register (EIMSR), and

 

 

 

disables the wait rise interrupt. To set this bit, a 1 must be written to the WRMSET0 bit in EIMSR.

 

 

0

Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the wait rise interrupt is enabled. Writing a 1 clears this bit and the WRMSET0 bit in

 

 

 

EIMSR.

 

 

 

 

1

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

value of 0.

 

 

 

 

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Table 39. EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions (continued)

Bit

Field

Value

Description

 

 

 

 

0

ATMCLR

 

Asynchronous Timeout Mask Clear. This bit determines whether or not the asynchronous timeout

 

 

 

interrupt is enabled. Writing a 1 to this bit clears this bit and the ATMSET bit in the EMIF interrupt mask

 

 

 

set register (EIMSR), and disables the asynchronous timeout interrupt. To set this bit, a 1 must be

 

 

 

written to the ATMSET bit in EIMSR.

 

 

0

Indicates that the asynchronous timeout interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the asynchronous timeout interrupt is enabled. Writing a 1 clears this bit and the ATMSET

 

 

 

bit in EIMSR.

 

 

 

 

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Registers

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4.8NAND Flash Control Register (NANDFCR)

The NAND Flash control register (NANDFCR) is shown in Figure 27 and described inTable 40.

Figure 27. NAND Flash Control Register (NANDFCR)

31

 

 

 

 

 

16

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

R-0

 

 

 

15

12

11

10

9

8

 

 

 

 

 

 

 

Reserved

 

 

CS5ECC

CS4ECC

CS3ECC

CS2ECC

 

 

 

 

 

 

 

R-0

 

 

R/W-0

R/W-0

R/W-0

R/W-0

7

4

3

2

1

0

 

 

 

 

 

 

 

Reserved

 

 

CS5NAND

CS4NAND

CS3NAND

CS2NAND

 

 

 

 

 

 

 

R-0

 

 

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 40. NAND Flash Control Register (NANDFCR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

31-12

Reserved

0

Reserved

 

 

 

 

11

CS5ECC

 

NAND Flash ECC start for chip select 5.

 

 

0

Do not start ECC calculation.

 

 

1

Start ECC calculation on data for NAND Flash on

 

 

 

 

EM_CS5.

10

CS4ECC

 

NAND Flash ECC start for chip select 4.

 

 

0

Do not start ECC calculation.

 

 

1

Start ECC calculation on data for NAND Flash on

 

 

 

 

EM_CS4.

9

CS3ECC

 

NAND Flash ECC start for chip select 3.

 

 

0

Do not start ECC calculation.

 

 

1

Start ECC calculation on data for NAND Flash on

 

 

 

 

EM_CS3.

8

CS2ECC

 

NAND Flash ECC start for chip select 2.

 

 

0

Do not start ECC calculation.

 

 

1

Start ECC calculation on data for NAND Flash on

 

 

 

 

EM_CS2.

7-4

Reserved

0

Reserved

 

 

 

 

 

 

3

CS5NAND

 

NAND Flash mode for chip select 5.

 

 

0

Not using NAND Flash.

 

 

1

Using NAND Flash on

 

 

 

 

 

 

EM_CS5.

2

CS4NAND

 

NAND Flash mode for chip select 4.

 

 

0

Not using NAND Flash.

 

 

1

Using NAND Flash on

 

 

 

 

 

 

EM_CS4.

1

CS3NAND

 

NAND Flash mode for chip select 3.

 

 

0

Not using NAND Flash.

 

 

1

Using NAND Flash on

 

 

 

 

 

 

EM_CS3.

0

CS2NAND

 

NAND Flash mode for chip select 2.

 

 

0

Not using NAND Flash.

 

 

1

Using NAND Flash on

 

 

 

 

 

 

EM_CS2.

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