Texas Instruments TMS320DM646X DMSOC User Manual

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Use Cases

From Figure 16, the following equations may be derived. tcyc is the period at which the EMIF operates. The R_SETUP, R_STROBE, and R_HOLD fields are programmed in terms of EMIF cycles where as the data sheet specifications are typically given is nano seconds. This is explains the presence of tcyc in the denominator of the following equations. A minus 1 is included in the equations because each field in ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, R_SETUP is equal to R_SETUP width in EMIF clock cycles minus 1 cycle.

R_SETUP w tCLR(m) * 1

tcyc

R_STROBE w max tREA(m) ) tSU ,tRP(m) * 1

tcyctcyc

R_SETUP ) R_STROBE w tCEA(m) ) tSU * 1

tcyc

R_HOLD w tH * tCHZ(m) * 1

tcyc

R_SETUP ) R_STROBE ) R_HOLD w tRC(m) * 3

tcyc

The EMIF offers an additional parameter, TA, that defines the turnaround time between read and write cycles. This parameter protects against the situation when the output turn-offtime of the memory is longer than the time it takes to start the next write cycle. If this is the case, the EMIF will drive data at the same time as the memory, causing contention on the bus. By examiningFigure 16, the equation for TA can be derived as:

TA w max

tCHZ(m)

,

tRHZ(m) * (R_HOLD ) 1)tcyc

* 1

tcyc

tcyc

Figure 16. Timing Waveform of a NAND Flash Read

 

 

Setup

Hold

 

 

 

Strobe

 

EM_CS

tRC(m)

ALE_EM_A[1]

CLE_EM_A[2]

 

 

 

tCLR(m)

tRP(m)

 

 

 

 

 

EM_OE

 

tCHZ(m)

 

 

 

 

tREA(m)

tSU

tH

 

tCEA(m)

tRHZ(m)

 

 

 

EM_D[7:0]

 

 

 

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To determine the required EMIF configuration to interface to the NAND Flash for a write operation, Table 27 lists the NAND AC timing parameters for a command latch, address latch, and data input latch that must be considered.

 

 

Table 27. NAND Flash Write Timing Requirements

 

 

Parameter

Description

 

 

tWP

Write Pulse width

tCLS

CLE Setup time

tALS

ALE Setup time

tCS

 

Setup time

CS

tDS

Data Setup time

tCLH

CLE Hold time

tALH

ALE Hold time

tCH

 

Hold time

CS

tDH

Data Hold time

tWC

Write Cycle time

Figure 17 toFigure 19 show the command latch, address latch, and data input latch of the NAND access.

From Figure 17 toFigure 19, the following equations may be derived. tcyc is the period at which the EMIF operates. The W_SETUP, W_STROBE, and W_HOLD fields are programmed in terms of EMIF cycles where as the data sheet specifications are typically given is nano seconds. This is explains the presence of tcyc in the denominator of the following equations. A minus 1 is included in the equations because each field in ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, W_SETUP is equal to W_SETUP width in EMIF clock cycles minus 1 cycle.

 

 

tCLS(m)

tALS(m) tCS(m)

 

 

W_SETUP w max

 

 

 

,

 

 

 

 

,

 

 

 

 

* 1

tcyc

 

tcyc

 

 

 

tcyc

W_STROBE w

tWP(m)

* 1

 

 

 

 

 

 

 

 

tcyc

 

 

 

 

 

 

 

W_SETUP ) W_STROBE w

tDS(m)

* 1

 

 

tcyc

 

 

 

W_HOLD w max

tCLH(m)

tALH(m)

tCH(m)

 

tDH(m)

 

* 1

 

,

 

 

,

 

 

,

 

 

 

tcyc

 

tcyc

 

tcyc

tcyc

 

W_SETUP ) W_STROBE ) W_HOLD w

tWC(m)

* 3

tcyc

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Figure 17. Timing Waveform of a NAND Flash Command Write

 

Setup

Hold

Strobe

 

tCH(m)

EM_CS

tWC(m)

tALH(m)

ALE_EM_A[1]

tCLH(m)

CLE_EM_A[2]

tWP(m)

tCS(m) tALS(m) tCLS(m)

EM_WE

tDS(m)

tDH(m)

EM_D[7:0]

Figure 18. Timing Waveform of a NAND Flash Address Write

Setup

Hold

Strobe

tCH(m)

EM_CS

tWC(m)

tALH(m)

ALE_EM_A[1]

tCLH(m)

CLE_EM_A[2]

tWP(m)

tCS(m) tALS(m) tCLS(m)

EM_WE

tDS(m)

tDH(m)

EM_D[7:0]

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Figure 19. Timing Waveform of a NAND Flash Data Write

Setup

Hold

Strobe

tCH(m)

EM_CS

tWC(m)

tALH(m)

ALE_EM_A[1]

tCLH(m)

CLE_EM_A[2]

tWP(m)

tCS(m) tALS(m) tCLS(m)

EM_WE

tDS(m)

tDH(m)

EM_D[7:0]

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3.2.3Example Using Hynix HY27UA081G1M

This section takes you through the configuration steps required to implement Hynix’s HY27UA081G1M NAND Flash with the EMIF. The following assumptions are made:

NAND Flash is connected to chip select space 2 (EM_CS[2])

EMIF clock speed is 100 MHZ (tcyc = 10 nS)

Table 28 lists the data sheet specifications for the EMIF andTable 29 lists the data sheet specifications for the NAND Flash.

Table 28. EMIF Timing Requirements for HY27UA081G1M Example

Parameter

Description

Min

Max

Units

tSU

Data Setup time, data valid before

 

 

high

5

 

nS

EM_OE

 

tH

Data Hold time, data valid after

 

 

high

0

 

nS

EM_OE

 

Table 29. NAND Flash Timing Requirements for HY27UA081G1M Example

Parameter

Description

Min

Max

Units

tRP

Read Pulse width

60

 

nS

tREA

Read Enable Access time

 

60

nS

tCEA

Chip Enable low to output valid

 

75

nS

tCHZ

Chip Enable high to output High-impedance

 

20

nS

tRC

Read Cycle time

80

 

nS

tRHZ

Read Enable high to output High-impedance

 

30

nS

tCLR

Command Latch low to Read enable low

10

 

nS

tWP

Write Pulse width

60

 

nS

tCLS

CLE Setup time

0

 

nS

tALS

ALE Setup time

0

 

nS

tCS

 

Setup time

0

 

nS

CS

 

tDS

Data Setup time

20

 

nS

tCLH

CLE Hold time

10

 

nS

tALH

ALE Hold time

10

 

nS

tCH

 

Hold time

10

 

nS

CS

 

tDH

Data Hold time

10

 

nS

tWC

Write Cycle time

80

 

nS

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Inserting these values into the equations defined above allows you to determine the values for SETUP, STROBE, HOLD, and TA. For a read:

 

 

 

 

tCLR(m)

 

 

 

 

 

10

 

 

 

 

 

 

 

R_SETUP w

 

 

 

 

 

* 1 w 10 *

1 w 0

 

 

 

 

 

 

tcyc

 

 

 

 

 

 

 

 

 

tREA(m) ) tSU

tRP

 

 

 

65

 

 

 

 

 

R_STROBE w max

 

 

 

 

 

 

 

,

 

 

 

 

 

 

* 1 w * 1 w

5.5

 

 

t

 

 

 

 

t

cyc

 

 

 

 

cyc

 

 

 

 

 

 

10

 

 

 

 

 

R_SETUP ) R_STROBE w

tCEA) tSU

* 1 w

(75 ) 5)

*

1 w 7

 

 

 

 

tcyc

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tH * tCHZ(m)

 

 

 

 

(0 * 20)

 

 

 

 

 

 

R_HOLD w

 

 

 

 

 

 

 

* 1 w

 

 

 

 

 

* 1 w * 3

 

 

 

 

tcyc

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRC(m)

 

 

80

 

 

 

R_SETUP ) R_STROBE ) R_HOLD w

 

 

* 3 w 10 * 3 w

5

 

tcyc

Therefore with a 10 nS margin added in, R_SETUP ≥ 1.0, R_STROBE ≥ 6.5, and R_HOLD ≥ 0. After solving for R_HOLD, TA may be calculated:

 

 

tCHZ(m)

tRHZ(m) * (R_HOLD ) 1)tcyc

 

20

 

TA w max

 

 

 

,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

* 1 w

* 1 w 1

t

 

 

 

 

 

 

 

 

 

t

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cyc

 

 

 

 

 

 

 

 

 

 

cyc

 

 

 

 

 

 

 

 

 

10

 

Adding a 10 ns margin, TA ≥ 2.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

For a write:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWP(m)

 

 

 

 

 

 

60

 

 

 

 

 

 

 

 

W_STROBE w

 

 

 

 

* 1 w

10 * 1 w 5

 

 

 

 

tcyc

 

W_SETUP w max

tCLS(m) tALS(m)

 

 

tCS(m)

*

 

0

 

 

 

 

 

 

,

 

 

,

 

 

 

 

 

1 w

 

* 1 w * 1

 

tcyc

 

tcyc

tcyc

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDS(m)

 

 

 

 

 

20

 

 

 

W_SETUP ) W_STROBE w

 

 

 

* 1 w 10 * 1 w

1

tcyc

 

 

 

 

 

tCLH(m)

tALH(m)

 

 

tCH(m)

 

 

 

tDH(m)

10

 

W_HOLD w max

 

,

 

 

,

 

 

 

 

 

,

 

 

 

 

 

 

* 1 w 10 * 1 w 0

tcyc

 

tcyc

 

 

 

tcyc

 

 

tcyc

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWC(m)

 

80

 

W_SETUP ) W_STROBE ) W_HOLD w

 

 

 

 

 

* 3 w 10 * 3 w 5

 

 

 

tcyc

 

Therefore with a 10 nS margin added in, W_SETUP ≥ 0, W_STROBE ≥ 6, and W_HOLD ≥ 1.

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Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields are equal to EMIF clock cycles minus 1 cycle, the A1CR should be configured as inTable 30. In this example, although the EM_WAIT signal is connected to the R/B signal of the NAND Flash the Extended Wait mode of the EMIF is not used, therefore the asynchronous wait cycle configuration register (AWCCR) does not need to be programmed.

 

Table 30. Configuring A1CR for HY27UA081G1M Example

 

 

Parameter

Setting

 

 

SS

Select Strobe mode.

 

• SS = 0. Places EMIF in Normal Mode.

 

 

EW

Extended Wait mode enable.

 

• EW = 0. Disabled Extended wait mode.

 

 

W_SETUP/R_SETUP

Read/Write setup widths.

 

W_SETUP = 0

 

R_SETUP = 2

 

 

W_STROBE/R_STROBE

Read/Write strobe widths.

 

W_STROBE = 6

 

R_STROBE = 7

 

 

W_HOLD/R_HOLD

Read/Write hold widths.

 

W_HOLD = 1

 

R_HOLD = 0

 

 

TA

Minimum turnaround time.

 

TA = 2

 

 

ASIZE

Asynchronous device bus width.

 

• ASIZE = 0, select an 8-bitdata bus width.

 

 

 

Since this is a NAND Flash example, the EMIF must be configured for NAND Flash mode. This is accomplished by configuring the NAND Flash control register (NANDFCR) as in Table 31. In NANDFCR, chip select space 2 must be configured with NAND Flash mode enabled.

 

Table 31. Configuring NANDFCR for HY27UA081G1M Example

 

 

Parameter

Setting

 

 

CS5ECC

NAND Flash ECC start for chip select 5.

 

• CS5ECC = 0. Not set during configuration. Only set just prior to reading or writing data.

 

 

CS4ECC

NAND Flash ECC start for chip select 4.

 

• CS4ECC = 0. Not set during configuration. Only set just prior to reading or writing data.

 

 

CS3ECC

NAND Flash ECC start for chip select 3.

 

• CS3ECC = 0. Not set during configuration. Only set just prior to reading or writing data.

 

 

CS2ECC

NAND Flash ECC start for chip select 2.

 

• CS2ECC = 0. Not set during configuration. Only set just prior to reading or writing data.

 

 

CS5NAND

NAND Flash mode for chip select 5.

 

• CS5NAND = 0. NAND Flash mode is disabled.

 

 

CS4NAND

NAND Flash mode for chip select 4.

 

• CS4NAND = 0. NAND Flash mode is disabled.

 

 

CS3NAND

NAND Flash mode for chip select 3.

 

• CS3NAND = 0. NAND Flash mode is disabled.

 

 

CS2NAND

NAND Flash mode for chip select 2.

 

• CS5NAND = 1. NAND Flash mode is enabled.

 

 

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4Registers

The external memory interface (EMIF) is controlled by programming its internal memory-mappedregisters (MMRs).Table 32 lists thememory-mappedregisters for the EMIF. See thedevice-specificdata manual for the memory address of these registers. All other register offset addresses not listed inTable 32 should be considered as reserved locations and the register contents should not be modified.

NOTE: The EMIF MMRs only support word (4 byte) accesses. Performing a byte (8 bit) or halfword (16 bit) write to a register results in unknown behavior.

Table 32. External Memory Interface (EMIF) Registers

Offset

Acronym

Register Description

Section

0

RCSR

Revision Code and Status Register

Section 4.1

4h

AWCCR

Asynchronous Wait Cycle Configuration Register

Section 4.2

10h

A1CR

Asynchronous 1 Configuration Register (CS2 space)

Section 4.3

14h

A2CR

Asynchronous 2 Configuration Register (CS3 space)

Section 4.3

18h

A3CR

Asynchronous 3 Configuration Register (CS4 space)

Section 4.3

1Ch

A4CR

Asynchronous 4 Configuration Register (CS5 space)

Section 4.3

40h

EIRR

EMIF Interrupt Raw Register

Section 4.4

44h

EIMR

EMIF Interrupt Mask Register

Section 4.5

48h

EIMSR

EMIF Interrupt Mask Set Register

Section 4.6

4Ch

EIMCR

EMIF Interrupt Mask Clear Register

Section 4.7

60h

NANDFCR

NAND Flash Control Register

Section 4.8

64h

NANDFSR

NAND Flash Status Register

Section 4.9

70h

NANDF1ECC

NAND Flash 1 ECC Register (CS2 Space)

Section 4.10

74h

NANDF2ECC

NAND Flash 2 ECC Register (CS3 Space)

Section 4.10

78h

NANDF3ECC

NAND Flash 3 ECC Register (CS4 Space)

Section 4.10

7Ch

NANDF4ECC

NAND Flash 4 ECC Register (CS5 Space)

Section 4.10

 

 

 

 

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Registers

4.1Revision Code and Status Register (RCSR)

The revision code and status register (RCSR) is shown in Figure 20 and described inTable 33.

Figure 20. Revision Code and Status Register (RCSR)

31

30

29

 

16

Reserved

 

 

MODID

 

 

 

 

 

 

R-x

 

 

R-Fh

15

 

8

7

0

 

 

 

 

 

 

 

REVMAJ

 

REVMIN

 

 

 

 

 

 

 

R-2h

 

R-2h

LEGEND: R = Read only; -n = value after reset;-x= value is indeterminate after reset

Table 33. Revision Code and Status Register (RCSR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

31-30

Reserved

0

Reserved

 

 

 

 

29-16

MODID

0-3FFFh

Module identification.

 

 

Fh

Asynchronous memory interface.

 

 

 

 

15-8

REVMAJ

0-FFh

Major Revision. EMIF code revisions are indicated by a revision code taking the format

 

 

 

REVMAJ.REVMIN.

 

 

2h

Current major revision.

 

 

 

 

7-0

REVMIN

0-FFh

Minor Revision. EMIF code revisions are indicated by a revision code taking the format

 

 

 

REVMAJ.REVMIN.

 

 

2h

Current minor revision.

 

 

 

 

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4.2Asynchronous Wait Cycle Configuration Register (AWCCR)

The asynchronous wait cycle configuration register (AWCCR) is used to configure the parameters for extended wait cycles. Both the polarity of the EM_WAIT[5:2] pins and the maximum allowable number of extended wait cycles can be configured. the AWCCR is shown in Figure 21 and described inTable 34.

NOTE: The EW bit in the asynchronous configuration register (ACFGn) must be set to allow for the insertion of extended wait cycles.

Figure 21. Asynchronous Wait Cycle Configuration Register (AWCCR)

31

30

29

28

 

27

24

23

22

21

20

19

18

17

16

WP3

WP2

WP1

WP0

 

 

Reserved

CS5_WAIT

CS4_WAIT

CS3_WAIT

CS2_WAIT

R/W-1

R/W-1

R/W-1

R/W-1

 

R-0

R/W-3h

R/W-2h

 

R/W-1

R/W-0

 

15

 

 

 

 

 

8

7

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

MEWC

 

 

 

 

 

 

R-0

 

 

 

 

 

R/W-80h

 

 

 

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

 

 

 

 

 

 

 

 

Table 34. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions

Bit

 

Field

Value

Description

 

 

 

 

 

 

 

31

 

WP3

 

WAIT polarity bit. This bit defines the polarity of the EM_WAIT[5] pin.

 

 

 

 

0

Insert wait cycles if EM_WAIT[5] pin is low.

 

 

 

 

1

Insert wait cycles if EM_WAIT[5] pin is high.

 

 

 

 

 

 

 

30

 

WP2

 

WAIT polarity bit. This bit defines the polarity of the EM_WAIT[4] pin.

 

 

 

 

0

Insert wait cycles if EM_WAIT[4] pin is low.

 

 

 

 

1

Insert wait cycles if EM_WAIT[4] pin is high.

 

 

 

 

 

 

 

29

 

WP1

 

WAIT polarity bit. This bit defines the polarity of the EM_WAIT[3] pin.

 

 

 

 

0

Insert wait cycles if EM_WAIT[3] pin is low.

 

 

 

 

1

Insert wait cycles if EM_WAIT[3] pin is high.

 

 

 

 

 

 

 

28

 

WP0

 

WAIT polarity bit. This bit defines the polarity of the EM_WAIT[2] pin.

 

 

 

 

0

Insert wait cycles if EM_WAIT[2] pin is low.

 

 

 

 

1

Insert wait cycles if EM_WAIT[2] pin is high.

 

 

 

 

 

 

 

27-24

 

Reserved

0

Reserved

 

 

 

 

 

 

23-22

 

CS5_WAIT

0-3h

EM_WAIT[5:2] pin map for chip select 5. By default, the EM_WAIT[5] pin is used for chip select 5.

 

 

 

0

EM_WAIT[2] pin is used.

 

 

 

 

1h

EM_WAIT[3] pin is used.

 

 

 

 

2h

EM_WAIT[4] pin is used.

 

 

 

 

3h

EM_WAIT[5] pin is used.

 

 

 

 

 

 

21-20

 

CS4_WAIT

0-3h

EM_WAIT[5:2] pin map for chip select 4. By default, the EM_WAIT[4] pin is used for chip select 4.

 

 

 

0

EM_WAIT[2] pin is used.

 

 

 

 

1h

EM_WAIT[3] pin is used.

 

 

 

 

2h

EM_WAIT[4] pin is used.

 

 

 

 

3h

EM_WAIT[5] pin is used.

 

 

 

 

 

 

19-18

 

CS3_WAIT

0-3h

EM_WAIT[5:2] pin map for chip select 3. By default, the EM_WAIT[3] pin is used for chip select 3.

 

 

 

0

EM_WAIT[2] pin is used.

 

 

 

 

1h

EM_WAIT[3] pin is used.

 

 

 

 

2h

EM_WAIT[4] pin is used.

 

 

 

 

3h

EM_WAIT[5] pin is used.

 

 

 

 

 

 

 

 

 

 

 

 

 

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