Texas Instruments TMS320DM646X DMSOC User Manual

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3.1.2Meeting AC Timing Requirements for ASRAM

When configuring the EMIF to interface to ASRAM, you must consider the AC timing requirements of the ASRAM as well as the AC timing requirements of the EMIF. These can be found in the data sheet for each respective device. The read and write asynchronous cycles are programmed separately in the asynchronous configuration register (ACFGn).

For a read access, Table 15 toTable 17 list the AC timing specifications that must be considered.

 

Table 15. EMIF Input Timing Requirements

 

 

Parameter

Description

 

 

 

 

tSU

Data Setup time, data valid before

 

 

high

EM_OE

tH

Data Hold time, data valid after

 

 

high

EM_OE

 

Table 16. ASRAM Output Timing Characteristics

 

 

Parameter

Description

 

 

tACC

Address Access time

tOH

Output data Hold time for address change

tCOD

Output Disable time from chip enable

 

Table 17. ASRAM Input Timing Requirement for a Read

 

 

Parameter

Description

 

 

tRC

Read Cycle time

Figure 12 shows an asynchronous read access and describes how the EMIF and ASRAM AC timing requirements work together to define the values for R_SETUP, R_STROBE, and R_HOLD.

From Figure 12, the following equations may be derived. tcyc is the period at which the EMIF operates. The R_SETUP, R_STROBE, and R_HOLD fields are programmed in terms of EMIF cycles where as the data sheet specifications are typically given in nano seconds. This explains the presence of tcyc in the denominator of the following equations. A minus 1 is included in the equations because each field in ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, R_SETUP is equal to R_SETUP width in EMIF clock cycles minus 1 cycle.

R_SETUP ) R_STROBE w tACC(m) ) tSU * 1

tcyc

R_SETUP ) R_STROBE ) R_HOLD w tRC(m) * 3

tcyc

R_HOLD w tH * tOH(m) * 1

tcyc

The EMIF offers an additional parameter, TA, that defines the turnaround time between read and write cycles. This parameter protects against the situation when the output turn-offtime of the memory is longer than the time it takes to start the next write cycle. If this is the case, the EMIF will drive data at the same time as the memory, causing contention on the bus. By examiningFigure 12, the equation for TA can be derived as:

TA w tCOD(m) * 1

tcyc

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Figure 12. Timing Waveform of an ASRAM Read

Setup

Hold

 

Strobe

EM_CS

 

 

tRC(m)

EM_A[21:0]

 

EM_BA[1:0]

 

EM_OE

tCOD(m)

tSU

tOH(m)

tACC(m)

tH

EM_D[15:0]

For a write access, Table 18 lists the AC timing specifications that must be satisfied.

 

Table 18. ASRAM Input Timing Requirements for a Write

 

 

Parameter

Description

 

 

tWP

Write Pulse width

tAW

Address valid to end of Write

tDS

Data Setup time

tWR

Write Recovery time

tDH

Data Hold time

tWC

Write Cycle time

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Figure 13 shows an asynchronous write access and describes how the EMIF and ASRAM AC timing requirements work together to define values for W_SETUP, W_STROBE, and W_HOLD.

From Figure 13, the following equations may be derived. tcyc is the period at which the EMIF operates. The W_SETUP, W_STROBE, and W_HOLD fields are programmed in terms of EMIF cycles where as the data sheet specifications are typically given is nano seconds. This is explains the presence of tcyc in the denominator of the following equations. A minus 1 is included in the equations because each field in ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, W_SETUP is equal to W_SETUP width in EMIF clock cycles minus 1 cycle.

 

tWP(m)

 

 

W_STROBE w tcyc

 

* 1

 

 

W_SETUP ) W_STROBE w max

tAW(m)

tDS(m)

* 1

 

tcyc

, tcyc

W_HOLD w max

tWR(m) tDH(m)

 

 

tcyc,

 

tcyc* 1

 

 

 

 

 

tWC(m)

W_SETUP ) W_STROBE ) W_HOLD w tcyc

* 3

Figure 13. Timing Waveform of an ASRAM Write

Setup

Strobe

 

 

Hold

 

 

 

 

EM_CS

 

 

 

 

 

 

tWC(m)

 

 

 

tWR(m)

EM_A[21:0]

EM_BA[1:0]

tWP(m) tAW(m)

EM_WE

tDS(m) tDH(m)

EM_D[15:0]

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3.1.3Taking Into Account PCB Delays

The equations described in Section 3.1.2 are for the ideal case, when board design does not contribute delays. Board characteristics, such as impedance, loading, length, number of nodes, etc., affect how the device driver behaves. Signals driven by the EMIF will be delayed when they reach the ASRAM and conversely.Table 19 lists the delays shown inFigure 14 andFigure 15 due to PCB affects. The PCB delays are board specific and must be estimated or determined though the use of IBIS modeling. The signals denoted(ASRAM) are the signals seen at the ASRAM. For example, EM_CS represents the signal at the EMIF and EM_CS (ASRAM) represents the delayed signal seen at the ASRAM.

Table 19. ASRAM Timing Requirements With PCB Delays

Parameter Description

Read Access

tEM_CS

tEM_A

tEM_OE

tEM_D

Delay on EM_CS from EMIF to ASRAM. EM_CS is driven by EMIF. Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF.

Delay on EM_OE from EMIF to ASRAM. EM_OE is driven by EMIF. Delay on EM_D from ASRAM to EMIF. EM_D is driven by ASRAM.

Write Access

tEM_CS

tEM_A

tEM_WE

tEM_D

Delay on EM_CS from EMIF to ASRAM. EM_CS is driven by EMIF.

Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF.

Delay on EM_WE from EMIF to ASRAM. EM_WE is driven by EMIF.

Delay on EM_D from EMIF to ASRAM. EM_D is driven by EMIF.

From Figure 14, the following equations may be derived. tcyc is the period at which the EMIF operates. The R_SETUP, R_STROBE, and R_HOLD fields are programmed in terms of EMIF cycles where as the data sheet specifications are typically given in nano seconds. This is explains the presence of tcyc in the denominator of the following equations. A minus 1 is included in the equations because each field in ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, R_SETUP is equal to R_SETUP width in EMIF clock cycles minus 1 cycle.

R_SETUP ) R_STROBE w tEM_A ) tACC(m) ) tSU ) tEM_D * 1

tcyc

R_SETUP ) R_STROBE ) R_HOLD w tRC(m) * 3

tcyc

R_HOLD w tH * tEM_D * tOH(m) * tEM_A * 1

tcyc

TA w tEM_CS) tCOD(m) ) tEM_D* 1

tcyc

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Figure 14. Timing Waveform of an ASRAM Read with PCB Delays

Setup

 

 

 

Hold

2

 

Strobe

 

4

1

 

3

 

 

EM_CS

 

 

 

 

tCS

 

 

 

tCS

EM_CS (ASRAM)

 

 

 

 

EM_A[21:0]/

 

 

 

 

EM_BA[1:0]

 

 

 

 

tEM_A

 

tRC(m)

tEM_A

 

 

 

EM_A[21:0]/

 

 

 

 

EM_BA[1:0] (ASRAM)

 

 

 

 

EM_OE

 

 

 

 

 

tEM_OE

tEM_OE

 

EM_OE (ASRAM)

 

 

 

 

 

 

 

tSU

tH

 

 

 

tEM_D

 

 

tEM_D

 

 

 

 

 

EM_D[15:0]

 

 

 

 

t

ACC

(m)

 

tCOD(m)

 

 

 

 

 

 

 

 

tOH(m)

EM_D[15:0]

 

 

 

 

(ASRAM)

 

 

 

 

From Figure 15, the following equations may be derived. tcyc is the period at which the EMIF operates. The W_SETUP, W_STROBE, and W_HOLD fields are programmed in terms of EMIF cycles where as the data sheet specifications are typically given is nano seconds. This is explains the presence of tcyc in the denominator of the following equations. A minus 1 is included in the equations because each field in ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, W_SETUP is equal to W_SETUP width in EMIF clock cycles minus 1 cycle.

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tWP(m)

 

 

 

W_STROBE w tcyc

* 1

 

 

 

W_SETUP ) W_STROBE w max

tEM_A) tAW(m) * tEM_WE

tEM_D) tDS(m) * tEM_WE

tcyc

 

,

 

tcyc

* 1

tEM_WE) tWR(m) * tEM_A

 

tEM_WE) tDH(m) * tEM_D

* 1

W_HOLD w max

tcyc

,

 

tcyc

 

 

 

 

 

tWC(m)

 

 

W_SETUP ) W_STROBE ) W_HOLD w tcyc

* 3

 

Figure 15. Timing Waveform of an ASRAM Write with PCB Delays

Setup

 

 

 

Hold

 

2

Strobe

 

4

 

1

 

 

3

 

 

 

EM_CS

 

 

 

 

 

 

tEM_CS

 

 

 

 

 

tEM_CS

EM_CS (ASRAM)

 

 

 

 

 

 

EM_A[21:0]/

EM_BA[1:0]

tEM_A

tWC(m)

tEM_A

tWR(m)

EM_A[21:0]/

EM_BA[1:0] (ASRAM)

EM_WE

tWP(m)

tEM_WE

tEM_WE

tAW(m)

EM_WE (ASRAM)

EM_D[15:0]

tEM_D

 

tDH(m)

 

tDS(m)

tEM_D

 

 

EM_D[15:0] (ASRAM)

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3.1.4Example Using TC5516100FT-12

This section takes you through the configuration steps required to implement Toshiba’s TC55V1664FT-12ASRAM with the EMIF. The following assumptions are made:

ASRAM is connected to chip select space 3 (EM_CS[3])

EMIF clock speed is 100 MHZ (tcyc = 10 nS)

Table 20 lists the data sheet specifications for the EMIF andTable 21 lists the data sheet specifications for the ASRAM.

Table 20. EMIF Timing Requirements for TC5516100FT-12Example

Parameter

Description

Min

Max

Units

tSU

Data Setup time, data valid before

 

 

high

5

 

nS

EM_OE

 

tH

Data Hold time, data valid after

 

 

high

0

 

nS

EM_OE

 

Table 21. ASRAM Timing Requirements for TC5516100FT-12Example

Parameter

Description

Min

Max

Units

tACC

Address Access time

 

12

nS

tOH

Output data Hold time for address change

3

 

nS

tRC

Read cycle time

12

 

nS

tWP

Write Pulse width

8

 

nS

tAW

Address valid to end of Write

9

 

nS

tDS

Data Setup time

7

 

nS

tWR

Write Recovery time

0

 

nS

tDH

Data Hold time

0

 

nS

tWC

Write Cycle time

12

 

nS

tCOD

Output Disable time from chip enable

 

7

 

Table 22 lists the values of the PCB board delays. The delays were estimated using the rule that there is 180 pS of delay for every 1 inch of trace.

Table 22. Measured PCB Delays for TC5516100FT-12Example

Parameter

Description

Delay (ns)

Read Access

tEM_CS

tEM_A

tEM_OE

tEM_D

 

 

 

 

 

 

 

Delay on EM_CS from EMIF to ASRAM. EM_CS is driven by EMIF.

0.36

Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF.

0.27

Delay on

 

from EMIF to ASRAM.

 

 

is driven by EMIF.

0.36

EM_OE

EM_OE

Delay on EM_D from ASRAM to EMIF. EM_D is driven by ASRAM.

0.45

Write Access

tEM_CS

tEM_A

tEM_WE

tEM_D

 

 

 

 

 

 

 

 

Delay on EM_CS from EMIF to ASRAM. EM_CS is driven by EMIF.

0.36

Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF.

0.27

Delay on

 

 

from EMIF to ASRAM.

 

 

is driven by EMIF.

0.36

EM_WE

EM_WE

Delay on EM_D from EMIF to ASRAM. EM_D is driven by EMIF.

0.45

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Inserting these values into the equations defined above allows you to determine the values for SETUP, STROBE, HOLD, and TA. For a read:

 

 

 

tEM_A) tACC(m) ) tSU) tEM_D

 

(0.27 ) 12 ) 5 ) 0.45)

 

R_SETUP ) R_STROBE w

 

 

 

 

 

 

 

 

 

* 1 w

 

 

 

 

 

 

* 1 w 0.78

tcyc

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRC(m)

 

12

 

 

 

 

R_SETUP ) R_STROBE ) R_HOLD w

 

 

 

* 3

w 10 *

3 w * 1.8

 

tcyc

R_HOLD w

tH * tEM_D * tOH(m) * tEM_A

* 1

(0 * 0.45 * 3 * 0.27)

1 w * 1.37

 

 

 

 

 

w

 

 

 

 

 

 

*

 

 

tcyc

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tEM_CS) TCOD(m) ) tEM_D

 

 

(0.36 ) 7 ) 0.45)

 

 

 

 

 

TA w

 

 

* 1

w

 

 

 

 

* 1 w *0.22

 

 

 

10

 

 

 

 

 

tcyc

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Therefore if R_SETUP = 0, then R_STROBE = 0, R_HOLD = 0, and TA = 0.

For a write:

 

 

 

 

tWP(m)

 

 

 

 

 

8

* 1 w * 0.2

 

 

 

 

W_STROBE w

 

 

* 1 w

 

 

 

 

 

 

 

 

 

tcyc

10

 

 

 

 

W_SETUP ) W_STROBE w max

tEM_A) tAW(m) * tEM_WE

tEM_D) tDS(m) * tEM_WE

* 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

,

 

 

 

 

 

 

 

tcyc

 

 

 

 

 

 

 

 

tcyc

 

 

w max

(0.36 ) 0 * 0.27)

,

 

(0.36 ) 0 * 0.45)

* 1 w * 0.92

 

 

 

 

10

 

 

 

 

 

 

 

 

10

 

 

 

tEM_WE) tWR(m) * tEM_A

 

 

tEM_WE) tDH(m) * tEM_D

 

W_HOLD w max

 

 

 

 

 

 

 

 

,

 

 

 

 

 

 

 

 

 

 

* 1

 

 

 

tcyc

 

 

 

 

 

 

 

 

 

 

 

 

tcyc

 

 

 

w max

(0.27 ) 9 * 0.36) (0.45 ) 7 * 0.36)

* 1 w * 0.1

 

 

 

 

,

 

 

 

 

 

 

 

 

10

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

tWC(m)

 

 

 

12

 

 

 

 

W_SETUP ) W_STROBE ) W_HOLD w

 

 

 

* 3

w 10 *

3 w * 1.8

 

 

tcyc

 

Therefore, W_SETUP = 0, W_STROBE = 0, and W_HOLD = 0.

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Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields are equal to EMIF clock cycles minus 1 cycle, the A2CR should be configured as in Table 23. In this example, the EM_WAIT signal is not implemented; therefore, the asynchronous wait cycle configuration register (AWCCR) does not need to be programmed.

Table 23. Configuring A2CR for TC5516100FT-12Example

 

 

Parameter

Setting

 

 

SS

Select Strobe mode.

 

• SS = 0. Places EMIF in Normal Mode.

 

 

EW

Extended Wait mode enable.

 

• EW = 0. Disabled Extended wait mode.

 

 

W_SETUP/R_SETUP

Read/Write setup widths.

 

W_SETUP = 0

 

R_SETUP = 0

 

 

W_STROBE/R_STROBE

Read/Write strobe widths.

 

W_STROBE = 0

 

R_STROBE = 0

 

 

W_HOLD/R_HOLD

Read/Write hold widths.

 

W_HOLD = 0

 

R_HOLD = 0

 

 

TA

Minimum turnaround time.

 

TA = 0

 

 

ASIZE

Asynchronous Device Bus Width.

 

• ASIZE = 1, select a 16-bitdata bus width

 

 

 

3.2Interfacing to NAND Flash

The following example explains how to interface the EMIF to the Hynix HY27UA081G1M NAND Flash device. Section 2.5.6.2 describes how to connect the EMIF to the HY27UA081G1M.

3.2.1Margin Requirements

The Flash interface is typically a low-performanceinterface compared to synchronous memory interfaces,high-speedasynchronous memory interfaces, andhigh-speedFIFO interfaces. For this reason, this example gives little attention to minimizing the amount of margin required when programming the asynchronous timing parameters. The approach used requires approximately 10 ns of margin on all parameters, which is not significant for a100-nsread or write cycle. For additional details on minimizing the amount of margin, see the ASRAM example given inSection 3.1.

 

Table 24. Recommended Margins

 

 

Timing Parameter

Recommended Margin

 

 

Output Setup

10 nS

Output Hold

10 nS

Input Setup

10 nS

Input Hold

10 nS

 

 

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3.2.2Meeting AC Timing Requirements for NAND Flash

When configuring the EMIF to interface to NAND Flash, you must consider the AC timing requirements of the NAND Flash as well as the AC timing requirements of the EMIF. These can be found in the data sheet for each respective device. The read and write asynchronous cycles are programmed separately in the asynchronous configuration register (ACFGn).

As described in Section 2.5.6, a NAND Flash access cycle is composed of a command, address, and data phases. The EMIF will not automatically generate these three phases to complete a NAND access with one transfer request. To complete a NAND access cycle, multiple single asynchronous access cycles must be completed by the EMIF. The command and address phases of a NAND Flash access cycle are asynchronous writes performed by the EMIF where as the data phase can be either an asynchronous write or a read depending on whether the NAND Flash is being programmed or read.

Therefore, to determine the required EMIF configuration to interface to the NAND Flash for a read operation, Table 25 andTable 26 list the AC timing parameters that must be considered.

 

Table 25. EMIF Read Timing Requirements

 

 

Parameter

Description

 

 

 

 

tSU

Data Setup time, data valid before

 

 

high

EM_OE

tH

Data Hold time, data valid after

 

 

high

EM_OE

 

Table 26. NAND Flash Read Timing Requirements

 

 

Parameter

Description

 

 

tRP

Read Pulse width

tREA

Read Enable Access time

tCEA

Chip Enable low to output valid

tCHZ

Chip Enable high to output High-impedance

tRC

Read Cycle time

tRHZ

Read enable high to output High-impedance

tCLR

Command Latch low to Read enable low

Figure 16 shows an asynchronous read access and describes how the EMIF and NAND Flash AC timing requirements work together to define the values for R_SETUP, R_STROBE, and R_HOLD.

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