Texas Instruments TMS320DM646X DMSOC User Manual

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Figure 7. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode

Setup

Strobe

Hold

3

2

2

 

Internal clock

 

 

EM_CS[5:2]

 

 

EM_A/EM_BA

Address

 

EM_D

Data

 

EM_OE

EM_WE

EM_RW

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2.5.6NAND Flash Mode

NAND Flash mode is the EMIF'sthird mode of operation. Each chip select space may be placed in NAND Flash mode individually by setting the appropriate CSnNAND bit in the NAND Flash control register (NANDFCR).Table 11 displays the bit fields present in NANDFCR and briefly describes their use.

When a chip select space is configured to operate in NAND Flash mode, the EMIF hardware can calculate the error correction code (ECC) for each 512 byte data transfer to that chip select space. The EMIF hardware will not generate the NAND access cycle, which includes the command, address, and data phases, necessary to complete a transfer to NAND Flash. All NAND Flash operations can be divided into single asynchronous cycles and with the help of software, the EMIF can execute a complete NAND access cycle.

Table 11. Description of the NAND Flash Control Register (NANDFCR)

Parameter Description

CS5ECC NAND Flash ECC state for chip select 5.

Set to 1 to start an ECC calculation.

Cleared to 0 when NAND Flash 4 ECC register (NANDF4ECC) is read.

CS4ECC NAND Flash ECC state for chip select 4.

Set to 1 to start an ECC calculation.

Cleared to 0 when NAND Flash 3 ECC register (NANDF3ECC) is read.

CS3ECC NAND Flash ECC state for chip select 3.

Set to 1 to start an ECC calculation.

Cleared to 0 when NAND Flash 2 ECC register (NANDF2ECC) is read.

CS2ECC NAND Flash ECC state for chip select 2.

Set to 1 to start an ECC calculation.

Cleared to 0 when NAND Flash 1 ECC register (NANDF1ECC) is read.

CS5NAND NAND Flash mode for chip select 5.

• Set to 1 to enable NAND Flash mode.

CS4NAND NAND Flash mode for chip select 4.

• Set to 1 to enable NAND Flash mode.

CS3NAND NAND Flash mode for chip select 3.

• Set to 1 to enable NAND Flash mode.

CS2NAND NAND Flash mode for chip select 2.

Set to 1 to enable NAND Flash mode.

2.5.6.1Configuring for NAND Flash Mode

Similar to the asynchronous accesses previously described, the EMIF'smemory-mappedregisters must be programmed appropriately to interface to a NAND Flash device.Table 12 lists the bit fields that must be programmed when operating in NAND Flash mode and the values to set each bit. NAND Flash mode cannot be used with Extended Wait mode.

Table 12. Configuration For NAND Flash

Register

Bit Field

Configuration Value

Asynchronous configuration

SS

0

register (ACFGn)

EW

0

 

 

W_SETUP/R_SETUP

See Section 3.2 for information on how to program.

 

W_STROBE/R_STROBE

See Section 3.2 for information on how to program.

 

W_HOLD/R_HOLD

See Section 3.2 for information on how to program.

 

ASIZE

Programmed to equal the width of the NAND Flash device

 

 

 

NAND Flash control register

CS2NAND

1

(NANDFCR)

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2.5.6.2Connecting to NAND Flash

Figure 8 shows the EMIF external pins used to interface with a NAND Flash device. EMIF address lines are used to drive the NAND Flash device'scommand latch enable (CLE) and address latch enable (ALE) signals.

NOTE: The EMIF will not control the NAND Flash device'swrite protect pin. The write protect pin must be controlled outside of the EMIF.

Figure 8. EMIF to NAND Flash Interface

EMIF

 

 

 

NAND flash

CLE_EM_A[16]

 

 

 

CLE

 

 

ALE_EM_A[17]

 

 

 

ALE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EM_CS[n]

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EM_WE

 

 

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EM_OE

 

 

 

OE

 

 

 

 

 

EM_D[7:0]

 

 

 

IO[7:0]

 

 

 

EM_WAIT[n]

 

 

 

R/B

 

 

 

 

 

 

a) Connection to 8-bitNAND device

 

 

 

 

 

EMIF

 

 

 

NAND flash

CLE_EM_A[16]

 

 

 

CLE

 

 

 

ALE_EM_A[17]

 

 

 

ALE

 

 

 

 

 

 

 

 

 

 

 

EM_CS[n]

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EM_WE

 

 

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EM_OE

 

 

 

OE

 

 

 

 

 

 

EM_D[15:0]

 

 

 

IO[15:0]

 

 

 

EM_WAIT[n]

 

 

 

R/B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b) Connection to 16-bitNAND device

2.5.6.3Driving CLE and ALE

As stated in Section 2.5.1, the EMIF always drives the least significant bit of a32-bitword address on EM_A[0]. This functionality must be considered when attempting to drive the address lines connected to CLE and ALE to the appropriate state.

For example, if using EM_A[2] and EM_A[1] to connect to CLE and ALE, respectively, the following offsets should be chosen:

00h to drive CLE and ALE low

10h to drive CLE high and ALE low

0Bh to drive CLE low and ALE high

These offsets should be added to the base address for the chip select space the NAND Flash device is connected to. For example, if the base address of the CS space the NAND Flash device is connected to is 4200 0000h, then the above list translates to the following memory-mappedaddresses: 4200 0000h, 4200 0010h, and 4200 000Bh, respectively. Therefore, when attempting to drive CLE high and ALE low, thememory-mappedaddress of 4200 0010h would be written to.

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2.5.6.4NAND Read and Program Operations

A NAND Flash access cycle is composed of a command, address, and data phase. The EMIF will not automatically generate these three phases to complete a NAND access with one transfer request. To complete a NAND access cycle, multiple single asynchronous access cycles (as described above) must be completed by the EMIF. Software must be used to request the appropriate asynchronous accesses to complete a NAND Flash access cycle. This software must be developed to the specification of the chosen NAND Flash device.

Since NAND operations are divided into single asynchronous access cycles, the chip select signal will not remain activated for the duration of the NAND operation. Instead, the chip select signal will deactivate between each asynchronous access cycle. For this reason, the EMIF does not support NAND Flash devices that require the chip select signal to remain low during the tR time for a read. SeeSection 2.5.6.8 for workaround.

Care must be taken when performing a NAND read or write operation via the EDMA. See Section 2.5.6.5 for more details.

NOTE: The EMIF does not support NAND Flash devices that require the chip select signal to remain low during the tR time for a read. SeeSection 2.5.6.8 for workaround.

2.5.6.5NAND Data Read and Write via DMA

When performing NAND accesses, the EDMA is most efficiently used for the data phase of the access. The command and address phases of the NAND access require only a few words of data to be transferred and therefore do not take advantage of the EDMA'sability to transfer larger quantities of data with a single request. In this section we will focus on using the EDMA for the data phase of a NAND access.

There are two conditions that require care to be taken when performing NAND reads and writes via the EDMA. These are:

CLE_EM_A[2] and ALE_EM_A[1] are lower address lines and must be driven low

The EMIF does not support a constant address mode, but only supports linear incrementing address modes.

Since the EMIF does not support a constant addressing mode, when programming the EDMA, a linear incrementing address mode must be used. When using a linear incrementing address mode, since the CLE and ALE are driven by lower address lines, care must be taken not to increase the address into a range the drives CLE and/or ALE high. To prevent the address from incrementing into a range that drives CLE and/or ALE high, the EDMA ACNT, BCNT, SIDX, DIDX, and synchronization type must be programmed appropriately. The proper EDMA configurations are described below.

EDMA setup for a NAND Flash data read:

ACNT ≤ 8 bytes (this can also be set to less than or equal to the external data bus width)

BCNT = transfer size in bytes/ACNT

SIDX (source index) = 0

DIDX (destination index) = ACNT

AB synchronized

EDMA setup for a NAND Flash data write:

ACNT ≤ 8 bytes (this can also be set to less than or equal to the external data bus width)

BCNT = transfer size in bytes/ACNT

SIDX (source index) = ACNT

DIDX (destination index) = 0

AB synchronized

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2.5.6.6ECC Generation

If the CSnNAND bit in the NAND Flash control register (NANDFCR) is set to 1, the EMIF supports ECC calculation for up to 512 bytes for the corresponding chip select care. To perform the ECC calculation, the CS2ECC bit in NANDFCR must be set to 1. The ECC calculation for each chip select space is independent of each other. It is the responsibility of the software to start the ECC calculation by writing to the CS2ECC bit prior to issuing a write or read to NAND Flash. It is also the responsibility of the software to read the calculated ECC from the NAND Flash 1 ECC register (NANDF1ECC) once the transfer to NAND Flash has completed. If the software writes or reads more than 512 bytes, the ECC will be incorrect. There is a NANDECCn for each chip select space and when read, the corresponding CSnECC bit in NANDFCR is cleared. The NANDF1ECC is cleared upon writing a 1 to the CS2ECC bit.Figure 9 shows the algorithm used to calculate the ECC value for an8-bitNAND Flash.

For an 8-bitNAND Flash p1e through p4e are column parities and p8e through p2048 are row parities. Similarly, the algorithm can be extended to a16-bitNAND Flash. For a16-bitNAND Flash p1e through p8e are column parities and p16e through p2048 are row parities. The software must ignore the unwanted parity bits if ECC is desired for less than 512 bytes of data. For example. p2048e and p2048o are not required for ECC on 256 bytes of data. Similarly, p1024e, p1024o, p2048e, and p2048o are not required for ECC on 128 bytes of data.

 

 

 

 

Figure 9. ECC Value for 8-BitNAND Flash

 

Byte 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

p8e

 

Byte 2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

p16e

 

p8o

p32e

Byte 3

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

p8e

p2048e

 

 

 

 

 

 

 

 

 

p16o

Byte 4

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

 

p8o

 

Byte 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

p8e

 

Byte 2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

p16e

p2048o

p8o

p32o

Byte 3

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

p8e

 

Byte 4

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

p16o

 

p8o

 

 

p1o

p1e

p1o

p1e

p1o

p1e

p1o

p1e

 

 

 

p2o

p2e

p2o

p2e

 

 

 

 

p4o

 

 

p4e

 

 

 

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2.5.6.7NAND Flash Status Register (NANDFSR)

The NAND Flash status register (NANDFSR) indicates the raw status of the EM_WAITn pin. The EM_WAITn pin should be connected to the NAND Flash device'sR/B signal, so that it indicates whether or not the NAND Flash device is busy. During a read, theR/B signal will transition and remain low while the NAND Flash retrieves the data requested. Once the R/B signal transitions high, the requested data is ready and should be read by the EMIF. During a write/program operation, the R/B signal transitions and remains lowwhile the NAND Flash is programming the Flash with the data it has received from the EMIF. Once the R/B signal transitions high, the data has been written to the Flash and the next phase of the transaction may be performed. From this explanation, you can see that the NAND Flash status register is useful to the software for indicating the status of the NAND Flash device and determining when to proceed to the next phase of a NAND Flash operation.

When a rising edge occurs on the EM_WAITn pin, the EMIF sets the WR (wait rise) bit in the EMIF interrupt raw register (EIRR). Therefore, the EMIF wait rise interrupt may be used to indicate the status of the NAND Flash device. The WPn bit in the asynchronous wait cycle configuration register (AWCCR) does not affect the NAND Flash status register (NANDFSR) or the WRn bit in EIRR. SeeSection 2.5.11.1 for more a detailed description of the wait rise interrupt.

2.5.6.8Interfacing to a Non-CEDon't Care NAND Flash

As explained in Section 2.5.6.4, the EMIF does not support NAND Flash devices that require the chip select signal to remain low during the tR time for a read. One way to work around this limitation is to use a GPIO pin to drive the CE signal of the NAND Flash device. If this work around is implemented, software will configure the selected GPIO to be low, then begin the NAND Flash operation, starting with the command phase. Once the NAND Flash operation has completed the software will configure the selected GPIO to be high. SeeSection 3 for more details on the GPIO workaround.

2.5.7Interfacing to a TI DSP HPI

The EMIF supports connecting as a host to a TI DSP HPI interface. When connecting to a TI DSP HPI interface, the EMIF must be configured for normal mode operation. Figure 10 shows the connection diagram.

Figure 10. EMIF to 16-BitMultiplexed HPI16 Interface

AEMIF

 

 

 

 

 

 

 

HPI16

EM_D[15:0]

 

 

 

HD[15:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

EM_RW

 

 

 

HR/W

 

 

EM_A[1:0]

 

 

 

HCNTL[1:0]

 

 

EM_WAIT

 

 

 

 

 

 

 

 

 

 

 

HRDY

 

 

 

 

 

 

 

 

 

 

EM_OE

 

 

 

HDS1

 

 

 

 

 

 

 

 

 

EM_WE

 

 

 

HDS2

 

 

EM_CS

 

 

 

HCS

 

 

EM_BA1

 

 

 

HHWIL

 

 

GPIOX

 

 

 

 

 

 

 

 

 

 

HINT

 

 

 

 

 

VCC

 

 

HAS

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

 

HPIENA

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

VSS

 

 

HBED

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

VSS

 

 

HBE1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A HBE signals may not be present on all HPI interfaces.

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2.5.8Extended Wait Mode and the EM_WAIT Pin

The Extended Wait mode is a mode in which the external asynchronous device may assert control over the length of the strobe period. The Extended Wait mode can be entered by setting the EW bit in the asynchronous configuration register (ACFGn). When the EW bit is set, the EMIF monitors the EM_WAIT[5:2] pins to determine if the attached device wishes to extend the strobe period of the current access cycle beyond the programmed number of clock cycles.

When the EMIF detects that the EM_WAIT pin has been asserted, it will begin inserting extra strobe cycles into the operation until the EM_WAIT pin is deactivated by the external device. The EMIF will then return to the last cycle of the programmed strobe period and the operation will proceed as usual from this point. Refer to the device-specificdata manual for details on the timing requirements of the EM_WAIT signal.

The EM_WAIT pin cannot be used to extend the strobe period indefinitely. The programmable MEWC bit in the asynchronous wait cycle configuration register (AWCCR) determines the maximum number of EMIF clock cycles the strobe period may be extended beyond the programmed length. When the number of cycles programmed in the MEWC bit expires, the EMIF proceeds to the hold period of the operation regardless of the state of the EM_WAIT pin. The EMIF can also generate an interrupt upon expiration of this counter. See Section 2.5.11.1 for details on enabling this interrupt.

For the EMIF to function properly in the Extended Wait mode, the WPn bit in AWCCR must be programmed to match the polarity of the attached device. When the WPn bit is in its reset state of 1, the EMIF will insert wait cycles when the EM_WAITn pin is sampled high; when the WPn bit is cleared to 0, the EMIF will insert wait cycles only when the EM_WAITn pin is sampled low. This programmability allows for a glueless connection to larger variety of asynchronous devices.

Finally, a restriction is placed on the setup and strobe period timing parameters when operating in Extended Wait mode. Specifically, the sum of the W_SETUP and W_STROBE fields must be greater than 4, and the sum of the R_SETUP and R_STROBE fields must be greater than 4 for the EMIF to recognize the EM_WAIT pin has been asserted. The W_SETUP, W_STROBE, R_SETUP, and R_STROBE fields are in ACFGn.

2.5.9Data Bus Parking

The EMIF always drives the data bus to the previous write data value when it is idle. This feature is called data bus parking. Only when the EMIF issues a read command to the external memory does it stop driving the data bus. After the EMIF latches the last read data, it immediately parks the data bus again.

2.5.10Reset and Initialization Considerations

The EMIF and its registers will be reset when any of the following events occur:

1.The RESET pin on the device is asserted

2.The EMIF is placed in reset by the Power and Sleep Controller.

When a reset occurs, the EMIF will immediately abandon any access request that is in progress and reset all registers and internal logic to their default state.

Following device power up and deassertion of the RESET pin, the internal clock to the EMIF is turned on and the EMIF memory-mappedregisters are programmed to their default values.

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2.5.11Interrupt Support

The EMIF has a single interrupt source (Table 13) mapped to the ARM interrupt controller. For more information on the ARM interrupt controller (AINTC), see theTMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9).

Table 13. EMIF Interrupt

ARM Event

Acronym

Source

60

EMIFAINT

EMIF

 

 

 

The EMIF supports a single interrupt to the CPU. Section 2.5.11.1 details the generation and internal masking of EMIF interrupts andSection 2.5.11.2 describes how the EMIF interrupts are sent to the CPU.

2.5.11.1Interrupt Events

There are two conditions that may cause the EMIF to generate an interrupt to the CPU. These two conditions are:

A rising edge on the EM_WAIT signal (wait rise interrupt)

An asynchronous time out

The wait rise interrupt is not affected by the WPn bit in the asynchronous wait cycle configuration register (AWCCR). The asynchronous time out interrupt condition occurs when the attached asynchronous device fails to deassert the EM_WAIT pin within the number of cycles defined by the MEWC bit in AWCCR.

Only when the interrupt is enabled by setting the appropriate bit (WRMSETn or ATMSET) in the EMIF interrupt mask set register (EIMSR) to 1, will the interrupt be sent to the CPU. Once enabled, the interrupt may be disabled by writing a 1 to the corresponding bit in the EMIF interrupt mask clear register (EIMCR). The bit fields in both the EIMSR and EIMCR may be used to indicate whether the interrupt is enabled. When the interrupt is enabled, the corresponding bit field in both the EIMSR and EIMCR will have a value of 1; when the interrupt is disabled, the corresponding bit field will have a value of 0.

The EMIF interrupt raw register (EIRR) and the EMIF interrupt mask register (EIMR) indicate the status of each interrupt. The appropriate bit (WRn or AT) in EIRR is set when the interrupt condition occurs, whether or not the interrupt has been enabled. Whereas, the appropriate bit (WRMn or ATM) in EIMR is set only when the interrupt condition occurs and the interrupt is enabled. Writing a 1 to the bit in EIRR clears the EIRR bit as well as the corresponding bit in EIMR.

Table 14 contains a brief summary of the interrupt status and control bit fields. SeeSection 4 for complete details on the register fields.

Table 14. Interrupt Monitor and Control Bit Fields

Register Name

Bit Name

Description

EMIF interrupt raw register

WRn

This bit is always set when an rising edge on the EM_WAIT signal occurs.

(EIRR)

 

Writing a 1 clears the WRn bit as well as the WRMn bit in EIMR.

 

AT

This bit is always set when an asynchronous timeout occurs. Writing a 1

 

 

clears the AT bit as well as the ATM bit in EIMR.

 

 

 

EMIF interrupt mask register

WRMn

This bit is only set when a rising edge on the EM_WAIT signal occurs and

(EIMR)

 

the interrupt has been enabled by writing a 1 to the WRMSETn bit in

 

 

EIMSR.

 

ATM

This bit is only set when an asynchronous timeout occurs and the interrupt

 

 

has been enabled by writing a 1 to the ATMSET bit in EIMSR.

 

 

 

EMIF interrupt mask set register

WRMSETn

Writing a 1 to this bit enables the wait rise interrupt.

(EIMSR)

ATMSET

Writing a 1 to this bit enables the asynchronous timeout interrupt.

 

 

 

 

EMIF interrupt mask clear register

WRMCLRn

Writing a 1 to this bit disables the wait rise interrupt.

(EIMCR)

ATMCLR

Writing a 1 to this bit disables the asynchronous timeout interrupt.

 

 

 

 

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2.5.11.2Interrupt Multiplexing

The EMIF interrupt is supported by both the ARM and DSP. The interrupt is not multiplexed with another interrupt and is therefore always available.

2.5.12Program Execution

Since the EMIF does not have byte enable or data mask pins, byte accesses to memory are not supported when the data bus width is equal to 16 bits. When performing data accesses on a 16-bitbus, this may be worked around by performing a write modify read back operation. When executing code from the EMIF, the bus width must be configured to be an8-bitdata bus.

2.5.13Power Management

Power dissipation to the EMIF may be managed by gating the input clock to the EMIF off. The input clock is turned off outside of the EMIF through the use of the Power and Sleep Controller (PSC). When the PSC sends a clock stop request to the EMIF, the EMIF will complete pending transfers before issuing a clock stop acknowledge, allowing the PSC to stop the clock. See the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9) for more information.

2.5.14Emulation Considerations

The operation of the EMIF is not affected when a breakpoint is reached or an emulation halt occurs.

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3Use Cases

The EMIF allows a high degree of programmability for shaping asynchronous accesses. As previously stated, the shape and duration of the asynchronous access is determined by controlling the widths of the SETUP, STROBE, HOLD, and turnaround periods. The widths of these periods are configured by programming the asynchronous configuration register (ACFGn) for the corresponding chip select space. SeeSection 2.5.3 andSection 4.3 for more information.

The programmability inherent to the EMIF, provides the EMIF with the flexibility to interface with a variety of asynchronous memory types. By programming the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, TA, and ASIZE fields in ACFGn, the EMIF can be configured to meet the data sheet specification for most asynchronous memory devices.

This section presents examples describing how to interface the EMIF to asynchronous SRAM and NAND Flash devices.

3.1Interfacing to Asynchronous SRAM (ASRAM)

The following example describes how to interface the EMIF to the Toshiba TC55V16100FT-12device.

3.1.1Connecting to ASRAM

Figure 11 shows how to connect the EMIF to the TC55V16100FT-12device. Since the EMIF does not include data mask or byte enable signals, the LB and UB signals of the ASRAM must be tied high.

Figure 11. Connecting the EMIF to the TC55V16100FT-12

EMIF

 

 

TC5516100FT−12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EM_CS

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EM_WE

 

 

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EM_OE

 

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VS S

 

 

LB

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

 

UB

 

 

 

 

 

 

 

 

A[18:0]

 

 

A[19:1]

 

 

 

EM_BA[1]

 

 

A[0]

 

EM_D[15:0]

 

 

DQ[15:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

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