Texas Instruments TMS320DM646X DMSOC User Manual

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Architecture

2.5.1Interfacing to Asynchronous Memory

Figure 2 shows the EMIF'sexternal pins used in interfacing with an asynchronous device. Of special note is the connection between the EMIF and the external device'saddress bus. The EMIF address pin EM_A[0] always provides the least significant bit of a32-bitword address. Therefore, when interfacing to a16-bitor8-bitasynchronous device, the EM_BA[1] and EM_BA[0] pins provide theleast-significantbits of the halfword or byte address, respectively.Figure 2 andFigure 3 show the mapping between the EMIF and the connected device'sdata and address pins for various programmed data bus widths. The data bus width may be configured in the asynchronous configuration register (ACFGn).

Figure 2. EMIF Asynchronous Interface

EMIF

EM_CS[5:2]

EM_WE

EM_OE

EM_RW

EM_WAIT[5:2]

EM_D[15:0]

EM_A[22:0]

EM_BA[1:0]

Figure 3. EMIF to 8-bitand16-bitMemory Interfaces

EMIF

 

8−bit

 

 

asynchronous

 

 

memory

EM_D[7:0]

 

DQ[7:0]

 

EM_A[21:0]

 

A[23:2]

 

EM_BA[1:0]

 

A[1:0]

 

 

 

 

a) EMIF to 8-bitmemory interface

 

 

 

EMIF

 

16−bit

 

 

asynchronous

 

 

memory

EM_D[15:0]

 

DQ[15:0]

 

EM_A[21:0]

 

A[22:1]

 

EM_BA[1]

 

A[0]

 

 

 

 

b) EMIF to 16-bitmemory interface

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2.5.2Programmable Asynchronous Parameters

The EMIF allows a high degree of programmability for shaping asynchronous accesses. The programmable parameters are:

Setup: The time between the beginning of a memory cycle (address valid) and the activation of the output enable or write enable strobe

Strobe: The time between the activation and deactivation of output enable or write enable strobe.

Hold: The time between the deactivation of output enable or write enable strobe and the end of the cycle, which may be indicated by an address change or the deactivation of the EM_CS signal.

Separate parameters are provided for read and write cycles. Each parameter is programmed in terms of EMIF clock cycles.

2.5.3Configuring the EMIF for Asynchronous Accesses

The operation of the EMIF'sasynchronous interface can be configured by programming the appropriate memory-mappedregisters. The reset value and bit position for each register field can be found inSection 4. The following tables list the programmable register fields and describe the purpose of each field. These registers should not be programmed while an asynchronous access is in progress. The transfer following a write to these registers will use the new configuration.

Table 3 describes the asynchronous configuration register (ACFGn). There are four ACFGns. Each chip select space has a dedicated ACFGn. This allows each chip select space to be programmed independently to interface to different asynchronous memory types.

 

Table 3. Description of the Asynchronous Configuration Register (ACFGn)

 

 

 

 

 

 

 

 

 

Parameter

Description

 

 

 

 

 

 

 

 

 

SS

Select Strobe mode. This bit selects the EMIF's mode of operation in the following way:

 

 

• SS = 0 selects Normal mode.

 

is active for duration of access.

 

 

EM_CS

 

 

• SS = 1 selects Select Strobe mode.

 

 

acts as a strobe.

 

 

 

 

 

 

 

EM_CS

 

 

 

 

 

 

EW

Extended Wait mode enable.

 

 

 

 

 

 

 

• EW = 0 disables Extended Wait mode

 

 

 

 

 

 

 

• EW = 1 enables Extended Wait mode

 

 

 

 

 

 

 

When set to 1, the EMIF enables its Extended Wait mode in which the strobe width of an access

 

 

cycle can be extended in response to the assertion of the EM_WAIT[5:2] pins. The WPn bit in the

 

 

asynchronous wait cycle configuration register (AWCCR) controls the polarity of the EM_WAITn pin.

 

 

See Section 2.5.8 for more details on this mode of operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W_SETUP/R_SETUP

Read/Write setup widths.

 

 

 

 

 

 

 

These fields define the number of EMIF clock cycles of setup time for the address pins (EM_A and

 

 

EM_BA) and asynchronous chip enable

(EM_CS)

 

before the read strobe pin

(READ_OE)

or write

 

 

strobe pin

(WRITE_WE)

falls, minus 1 cycle. For writes, the W_SETUP field also defines the setup

 

 

time for the data pins (EM_D). Refer to the datasheet of the external asynchronous device to

 

 

determine the appropriate setting for this field.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W_STROBE/R_STROBE

Read/Write strobe widths.

 

 

 

 

 

 

 

These fields define the number of EMIF clock cycles between the falling and rising of the read strobe

 

 

pin

 

or write strobe pin

 

 

 

 

 

 

 

 

 

(READ_OE)

(WRITE_WE), minus 1 cycle. If Extended Wait mode is enabled

 

 

by setting the EW bit in the asynchronous configuration register (ACFGn), these fields must be set to

 

 

a value greater than zero. Refer to the datasheet of the external asynchronous device to determine

 

 

the appropriate setting for this field.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W_HOLD/R_HOLD

Read/Write hold widths.

 

 

 

 

 

 

 

These fields define the number of EMIF clock cycles of hold time for the address pins (EM_A and

 

 

EM_BA) and asynchronous chip enable

(EM_CS)

 

after the read strobe pin

(READ_OE)

or write

 

 

strobe pin

(WRITE_WE)

rises, minus 1 cycle. For writes, the W_HOLD field also defines the hold

 

 

time for the data pins (EM_D). Refer to the datasheet of the external asynchronous device to

 

 

determine the appropriate setting for this field.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TA

Minimum turnaround time.

 

 

 

 

 

 

 

This field defines the minimum number of EMIF clock cycles between the end of one asynchronous

 

 

access and the start of another, minus 1 cycle. This delay is not incurred when a read is followed by

 

 

a read, or a write is followed by a write to the same chip select space. The purpose of this feature is

 

 

to avoid contention on the bus. Refer to the datasheet of the external asynchronous device to

 

 

determine the appropriate setting for this field.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Table 3. Description of the Asynchronous Configuration Register (ACFGn) (continued)

Parameter

Description

ASIZE

Asynchronous Device Bus Width.

 

This field determines the data bus width of the asynchronous interface in the following way:

 

• ASIZE = 0 selects an 8-bitbus

 

• ASIZE = 1 selects a 16-bitbus

 

The configuration of ASIZE determines the function of the EM_A and EM_BA pins as described in

 

Section 2.5.1. This field also determines the number of external accesses required to fulfill a request

 

generated by one of the sources mentioned in Section 2.2. For example, a request for a32-bitword

 

would require four external access when ASIZE = 0h. Refer to the datasheet of the external

 

asynchronous device to determine the appropriate setting for this field.

 

 

Table 4. Description of the Asynchronous Wait Cycle Configuration Register (AWCCR)

Parameter

Description

WPn

WAIT Polarity.

 

• WPn = 0 selectsactive-lowpolarity

 

• WPn = 1 selectsactive-highpolarity

 

When set to 1, the EMIF will wait if the EM_WAITn pin is high. When cleared to 0, the EMIF will wait if the

 

EM_WAITn pin is low. The EMIF must have the Extended Wait mode enabled (EW bit in the asynchronous

 

configuration register (ACFGn) is set to 1) for the EM_WAITn pin to affect the width of the strobe period.

 

 

MEWC

Maximum Extended Wait Cycles.

 

This field configures the number of EMIF clock cycles the EMIF will wait for the EM_WAITn pin to be deactivated

 

during the strobe period of an access cycle. The maximum number of EMIF clock cycles the EMIF will wait is

 

determined by the following formula:

 

Maximum Extended Wait Cycles = (MEWC + 1) × 16

 

If the EM_WAITn pin is not deactivated within the time specified by this field, the EMIF resumes the access cycle,

 

registering whatever data is on the bus and preceding to the hold period of the access cycle. This situation is

 

referred to as an asynchronous timeout. An asynchronous timeout generates an interrupt if it has been enabled in

 

the EMIF interrupt mask set register (EIMSR). Refer to Section 2.5.11 for more information about the EMIF

 

interrupts.

 

 

Table 5. Description of the EMIF Interrupt Mask Set Register (EIMSR)

Parameter Description

WRMSETn Wait Rise Mask Set.

Writing a 1 enables an interrupt to be generated when a rising edge on EM_WAITn occurs.

ATMSET Asynchronous Timeout Mask Set.

Writing a 1 to this bit enables an interrupt to be generated when an asynchronous timeout occurs.

Table 6. Description of the EMIF Interrupt Mast Clear Register (EIMCR)

Parameter Description

WRMCLRn Wait Rise Mask Clear.

Writing a 1 to this bit disables the interrupt, clearing the WRMSETn bit in the EMIF interrupt mask set register (EIMSR).

ATMCLR Asynchronous Timeout Mask Clear.

Writing a 1 to this bit disables the interrupt, clearing the ATMSET bit in the EMIF interrupt mask set register (EIMSR).

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2.5.4Read and Write Operations in Normal Mode

Normal mode is the asynchronous interface'sdefault mode of operation. The Normal mode is selected when the SS bit in the asynchronous configuration register (ACFGn) is cleared to 0. In this mode, the EM_CS signal operates as a chip enable signal, active throughout the duration of the memory access.

2.5.4.1Asynchronous Read Operations (Normal Mode)

An asynchronous read is performed when any of the requesters mentioned in Section 2.2 request a read from the attached asynchronous memory. In the event that the read request cannot be serviced by a single access cycle to the external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled. The details of an asynchronous read operation in Normal mode are described inTable 7 and an example timing diagram of a basic read operation is shown inFigure 4.

NOTE: During the entirety of an asynchronous read operation, the WRITE_WE and EM_RW pins are driven high.

 

Table 7. Asynchronous Read Operation in Normal Mode

 

 

Time Interval

Pin Activity in WE Strobe Mode

 

 

Turnaround

Once the EMIF receives a read request, the EMIF waits for the programmed number of turn-aroundcycles

period

before proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA

 

field of the asynchronous configuration register (ACFGn). There are two exceptions to this rule:

If the current read operation was directly proceeded by another read operation to the same CS space, no turnaround cycles are inserted.

If the current read operation was not directly proceeded by a read operation to the same CS space and the TA field has been cleared to 0, one turn-aroundcycle will be inserted.

After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.

Start of setup

At the beginning of the setup period:

period

• The setup, strobe, and hold values are set according to the R_SETUP, R_STROBE, and R_HOLD values

 

 

 

in ACFGn.

 

• The address pins EM_A and EM_BA become valid

 

 

falls to enable the external device (if not already low from a previous operation)

 

EM_CS

Start of strobe

At the beginning of the strobe period

period

 

 

 

 

• READ_OE falls

 

Start of hold

At the beginning of the hold period:

period

 

 

 

 

• READ_OE rises

 

 

• The EMIF samples the data on the EM_D bus.

 

 

 

End of hold

At the end of the hold period:

period

• The address pins EM_A and EM_BA become invalid

 

 

 

rises (if no more operations are required to complete the current request)

 

EM_CS

 

The EMIF will be required to issue additional read operations to a device with a small data bus width in order to

 

complete an entire word access. In this case, the EMIF immediately re-entersthe setup period to begin another

 

operation without incurring the turn-roundcycle delay. The setup, strobe, and hold values are not updated in this

 

case. If the entire word access has been completed, the EMIF returns to its previous state unless another

 

asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF

 

instead enters directly into the turnaround period for the pending read or write operation.

 

 

 

 

 

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Figure 4. Timing Waveform of an Asynchronous Read Cycle in Normal Mode

Setup

Strobe

Hold

3

2

2

 

Internal clock

 

 

EM_CS[5:2]

 

 

EM_A/EM_BA

Address

 

EM_D

 

Data

EM_OE

EM_WE

EM_RW

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2.5.4.2Asynchronous Write Operations (Normal Mode)

An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write to asynchronous memory. In the event that the write request cannot be serviced by a single access cycle to the external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled. The details of an asynchronous write operation in Normal mode are described inTable 8 and an example timing diagram of a basic write operation is shown inFigure 5.

NOTE: During the entirety of an asynchronous write operation, the EM_OE pin is driven high.

 

Table 8. Asynchronous Write Operation in Normal Mode

 

 

Time Interval

Pin Activity in WE Strobe Mode

 

 

Turnaround

Once the EMIF receives a write request, the EMIF waits for the programmed number of turn-aroundcycles

period

before proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA

 

field of the asynchronous configuration register (ACFGn). There are two exceptions to this rule:

If the current write operation was directly proceeded by another write operation to the same CS space, no turnaround cycles are inserted.

If the current write operation was not directly proceeded by a write operation to the same CS space and the TA field has been cleared to 0, one turnaround cycle will be inserted.

After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.

Start of setup

At the beginning of the setup period:

period

• The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values

 

 

 

in ACFGn.

 

• The address pins EM_A and EM_BA and the data pins EM_D become valid.

 

 

 

pin falls to indicate a write (if not already low from a previous operation).

 

• The EM_RW

 

 

falls to enable the external device (if not already low from a previous operation).

 

EM_CS

Start of strobe

At the beginning of the strobe period of a write operation:

period

 

 

 

 

 

 

 

• EM_WE falls

 

Start of hold

At the beginning of the hold period

period

 

 

 

 

 

 

 

• EM_WE rises

 

End of hold

At the end of the hold period:

period

• The address pins EM_A and EM_BA become invalid

 

 

• The data pins become invalid

 

 

 

 

 

pin rises (if no more operations are required to complete the current request)

 

• The EM_RW

 

 

 

rises (if no more operations are required to complete the current request)

 

EM_CS

 

The EMIF may be required to issue additional write operations to a device with a small data bus width in order to

 

complete an entire word access. In this case, the EMIF immediately re-entersthe setup period to begin another

 

operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this

 

case. If the entire word access has been completed, the EMIF returns to its previous state unless another

 

asynchronous request has been submitted. If this is the case, the EMIF instead enters directly into the

 

turnaround period for the pending read or write operation.

 

 

 

 

 

 

 

 

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Figure 5. Timing Waveform of an Asynchronous Write Cycle in Normal Mode

Setup

Strobe

Hold

3

2

2

 

Internal clock

 

 

EM_CS[5:2]

 

 

EM_A/EM_BA

Address

 

EM_D

Data

 

EM_OE

EM_WE

EM_RW

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2.5.5Read and Write Operations in Select Strobe Mode

Select Strobe mode is the EMIF'ssecond mode of operation. The SS mode is selected when the SS bit in the asynchronous configuration register (ACFGn) is set to 1. In this mode, the EM_CS pin functions as a strobe signal and is therefore only active during the strobe period of an access cycle.

2.5.5.1Asynchronous Read Operations (Select Strobe Mode)

An asynchronous read is performed when any of the requesters mentioned in Section 2.2 request a read from the attached asynchronous memory. In the event that the read request cannot be serviced by a single access cycle to the external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled. The details of an asynchronous read operation in Select Strobe mode are described inTable 9 and an example timing diagram of a basic read operation is shown inFigure 6.

NOTE: During the entirety of an asynchronous read operation, the EM_WE and EM_RW pins are driven high.

 

Table 9. Asynchronous Read Operation in Select Strobe Mode

 

 

Time Interval

Pin Activity in Select Strobe Mode

 

 

Turnaround

Once the EMIF receives a read request, the EMIF waits for the programmed number of turnaround cycles before

period

proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA field of

 

the asynchronous configuration register (ACFGn). There are two exceptions to this rule:

If the current read operation was directly proceeded by another read operation to the same CS space, no turnaround cycles are inserted.

If the current read operation was not directly proceeded by a read operation to the same CS space and the TA field has been cleared to 0, one turnaround cycle will be inserted.

After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.

Start of setup

At the beginning of the setup period:

period

• The setup, strobe, and hold values are set according to the R_SETUP, R_STROBE, and R_HOLD values

 

 

 

in ACFGn.

 

• The address pins EM_A and EM_BA become valid.

 

 

Start of strobe

At the beginning of the strobe period:

period

 

 

 

 

 

• EM_CS and EM_OE fall at the start of the strobe period

 

Start of hold

At the beginning of the hold period:

period

 

 

 

 

 

• EM_CS and EM_OE rise

 

 

• The EMIF samples the data on the EM_D bus

 

 

 

 

 

 

End of hold

At the end of the hold period:

period

• The address pins EM_A and EM_BA become invalid

 

The EMIF may be required to issue additional read operations to a device with a small data bus width in order to

 

complete an entire word access. In this case, the EMIF immediately re-entersthe setup period to begin another

 

operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this

 

case. If the entire word access has been completed, the EMIF returns to its previous state unless another

 

asynchronous request has been submitted. If this is the case, the EMIF instead enters directly into the

 

turnaround period for the pending read or write operation.

 

 

 

 

 

 

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Figure 6. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode

Setup

Strobe

Hold

3

2

2

 

Internal clock

 

 

EM_CS[5:2]

 

 

EM_A/EM_BA

Address

 

EM_D Data

EM_OE

EM_WE

EM_RW

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2.5.5.2Asynchronous Write Operations (Select Strobe Mode)

An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write to memory in the asynchronous bank of the EMIF. In the event that the write request cannot be serviced by a single access cycle to the external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled. The details of an asynchronous write operation in Select Strobe mode are described inTable 10 and an example timing diagram of a basic write operation is shown inFigure 7.

NOTE: During the entirety of an asynchronous write operation, the EM_OE pin is driven high.

 

Table 10. Asynchronous Write Operation in Select Strobe Mode

 

 

Time Interval

Pin Activity in Select Strobe Mode

 

 

Turnaround

Once the EMIF receives a write request, the EMIF waits for the programmed number of turnaround cycles

period

before proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA

 

field of the asynchronous configuration register (ACFGn). There are two exceptions to this rule:

If the current write operation was directly proceeded by another write operation to the same CS space, no turnaround cycles are inserted.

If the current write operation was directly proceeded by a write operation to the same CS space and the TA field has been cleared to 0, one turnaround cycle will be inserted.

After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.

Start of setup

At the beginning of the setup period:

period

• The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values

 

 

 

in ACFGn.

 

• The address pins EM_A and EM_BA and the data pins EM_D become valid.

 

 

 

pin falls to indicate a write (if not already low from a previous operation).

 

• The EM_RW

Start of strobe

At the beginning of the strobe period:

period

 

 

 

 

 

 

 

 

• EM_CS and EM_WE fall

 

Start of hold

At the beginning of the hold period:

period

 

 

 

 

 

 

 

 

• EM_CS and EM_WE rise

 

End of hold

At the end of the hold period:

period

• The address pins EM_A and EM_BA become invalid

 

 

• The data pins become invalid

 

 

 

 

 

 

 

pin rises (if no more operations are required to complete the current request)

 

• The EM_RW

 

The EMIF may be required to issue additional write operations to a device with a small data bus width in order to

 

complete an entire word access. In this case, the EMIF immediately re-entersthe setup period to begin another

 

operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this

 

case. If the entire word access has been completed, the EMIF returns to its previous state unless another

 

asynchronous request has been submitted. If this is the case, the EMIF instead enters directly into the

 

turn-aroundperiod for the pending read or write operation.

 

 

 

 

 

 

 

 

 

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