Texas Instruments TMS320DM646X DMSOC User Manual
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TMS320DM646x DMSoC

Asynchronous External Memory Interface (EMIF)

User's Guide

Literature Number: SPRUEQ7C

February 2010

2

SPRUEQ7C –February2010

 

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Preface .......................................................................................................................................

 

6

1

Introduction ........................................................................................................................

8

 

1.1

Purpose of the Peripheral ..............................................................................................

8

 

1.2

Features ..................................................................................................................

8

 

1.3

Functional Block Diagram ..............................................................................................

9

2

Architecture ........................................................................................................................

9

 

2.1

Clock Control .............................................................................................................

9

 

2.2

EMIF Requests ..........................................................................................................

9

 

2.3

Signal Descriptions ....................................................................................................

10

 

2.4

Pin Multiplexing ........................................................................................................

10

 

2.5

Asynchronous Controller and Interface .............................................................................

10

3

Use Cases ........................................................................................................................

30

 

3.1

Interfacing to Asynchronous SRAM (ASRAM) .....................................................................

30

 

3.2

Interfacing to NAND Flash ............................................................................................

39

4

Registers ..........................................................................................................................

48

 

4.1

Revision Code and Status Register (RCSR) .......................................................................

49

 

4.2

Asynchronous Wait Cycle Configuration Register (AWCCR) ....................................................

50

 

4.3

Asynchronous n Configuration Registers (A1CR-A4CR) .........................................................

52

 

4.4

EMIF Interrupt Raw Register (EIRR) ................................................................................

53

 

4.5

EMIF Interrupt Mask Register (EIMR) ...............................................................................

54

 

4.6

EMIF Interrupt Mask Set Register (EIMSR) ........................................................................

56

 

4.7

EMIF Interrupt Mask Clear Register (EIMCR) .....................................................................

58

 

4.8

NAND Flash Control Register (NANDFCR) ........................................................................

60

 

4.9

NAND Flash Status Register (NANDFSR) .........................................................................

61

 

4.10

NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) ...................................................

61

Appendix A

Revision History ......................................................................................................

63

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Table of Contents

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List of Figures

 

1

EMIF Functional Block Diagram ..........................................................................................

9

2

EMIF Asynchronous Interface ...........................................................................................

11

3

EMIF to 8-bit and 16-bit Memory Interfaces ...........................................................................

11

4

Timing Waveform of an Asynchronous Read Cycle in Normal Mode ..............................................

15

5

Timing Waveform of an Asynchronous Write Cycle in Normal Mode ..............................................

17

6

Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode.......................................

19

7

Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode .......................................

21

8

EMIF to NAND Flash Interface ..........................................................................................

23

9

ECC Value for 8-Bit NAND Flash .......................................................................................

25

10

EMIF to 16-Bit Multiplexed HPI16 Interface............................................................................

26

11

Connecting the EMIF to the TC55V16100FT-12 ......................................................................

30

12

Timing Waveform of an ASRAM Read ................................................................................

32

13

Timing Waveform of an ASRAM Write .................................................................................

33

14

Timing Waveform of an ASRAM Read with PCB Delays ............................................................

35

15

Timing Waveform of an ASRAM Write with PCB Delays ............................................................

36

16

Timing Waveform of a NAND Flash Read ............................................................................

41

17

Timing Waveform of a NAND Flash Command Write ...............................................................

43

18

Timing Waveform of a NAND Flash Address Write ..................................................................

43

19

Timing Waveform of a NAND Flash Data Write ......................................................................

44

20

Revision Code and Status Register (RCSR) ..........................................................................

49

21

Asynchronous Wait Cycle Configuration Register (AWCCR)........................................................

50

22

Asynchronous n Configuration Register (ACFGn) ....................................................................

52

23

EMIF Interrupt Raw Register (EIRR)....................................................................................

53

24

EMIF Interrupt Mask Register (EIMR) ..................................................................................

54

25

EMIF Interrupt Mask Set Register (EIMSR)............................................................................

56

26

EMIF Interrupt Mask Clear Register (EIMCR) .........................................................................

58

27

NAND Flash Control Register (NANDFCR)............................................................................

60

28

NAND Flash Status Register (NANDFSR) .............................................................................

61

29

NAND Flash n ECC Register (NANDECCn)...........................................................................

62

4

List of Figures

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List of Tables

 

1

EMIF Pins ..................................................................................................................

10

2

Behavior of EM_CS Signal Between Normal Mode and Select Strobe Mode.....................................

10

3

Description of the Asynchronous Configuration Register (ACFGn).................................................

12

4

Description of the Asynchronous Wait Cycle Configuration Register (AWCCR)..................................

13

5

Description of the EMIF Interrupt Mask Set Register (EIMSR)......................................................

13

6

Description of the EMIF Interrupt Mast Clear Register (EIMCR)....................................................

13

7

Asynchronous Read Operation in Normal Mode ......................................................................

14

8

Asynchronous Write Operation in Normal Mode ......................................................................

16

9

Asynchronous Read Operation in Select Strobe Mode ..............................................................

18

10

Asynchronous Write Operation in Select Strobe Mode...............................................................

20

11

Description of the NAND Flash Control Register (NANDFCR) ......................................................

22

12

Configuration For NAND Flash .........................................................................................

22

13

EMIF Interrupt..............................................................................................................

28

14

Interrupt Monitor and Control Bit Fields ................................................................................

28

15

EMIF Input Timing Requirements .......................................................................................

31

16

ASRAM Output Timing Characteristics .................................................................................

31

17

ASRAM Input Timing Requirement for a Read ........................................................................

31

18

ASRAM Input Timing Requirements for a Write ......................................................................

32

19

ASRAM Timing Requirements With PCB Delays .....................................................................

34

20

EMIF Timing Requirements for TC5516100FT-12 Example ........................................................

37

21

ASRAM Timing Requirements for TC5516100FT-12Example.....................................................

37

22

Measured PCB Delays for TC5516100FT-12 Example ..............................................................

37

23

Configuring A2CR for TC5516100FT-12 Example....................................................................

39

24

Recommended Margins ..................................................................................................

39

25

EMIF Read Timing Requirements.......................................................................................

40

26

NAND Flash Read Timing Requirements ..............................................................................

40

27

NAND Flash Write Timing Requirements .............................................................................

42

28

EMIF Timing Requirements for HY27UA081G1M Example .........................................................

45

29

NAND Flash Timing Requirements for HY27UA081G1M Example ................................................

45

30

Configuring A1CR for HY27UA081G1M Example ....................................................................

47

31

Configuring NANDFCR for HY27UA081G1M Example ..............................................................

47

32

External Memory Interface (EMIF) Registers ..........................................................................

48

33

Revision Code and Status Register (RCSR) Field Descriptions ....................................................

49

34

Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions .................................

50

35

Asynchronous n Configuration Register (ACFGn) Field Descriptions..............................................

52

36

EMIF Interrupt Raw Register (EIRR) Field Descriptions .............................................................

53

37

EMIF Interrupt Mask Register (EIMR) Field Descriptions ............................................................

54

38

EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions .....................................................

56

39

EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions...................................................

58

40

NAND Flash Control Register (NANDFCR) Field Descriptions .....................................................

60

41

NAND Flash Status Register (NANDFSR) Field Descriptions.......................................................

61

42

NAND Flash n ECC Register (NANDECCn) Field Descriptions....................................................

62

43

Document Revision History ..............................................................................................

63

SPRUEQ7C –February2010

List of Tables

5

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Preface

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Read This First

About This Manual

This document describes the asynchronous external memory interface (EMIF) in the TMS320DM646x Digital Media System-on-Chip(DMSoC). The EMIF supports a glueless interface to a variety of external devices.

Notational Conventions

This document uses the following conventions.

Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.

Registers in this document are shown in figures and described in tables.

Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.

Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments

The following documents describe the TMS320DM646x Digital Media System-on-Chip(DMSoC). Copies of these documents are available on the Internet atwww.ti.com.Tip: Enter the literature number in the search box provided at www.ti.com.

The current documentation that describes the DM646x DMSoC, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.

SPRUEP8 TMS320DM646x DMSoC DSP Subsystem Reference Guide.Describes the digital signal processor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC).

SPRUEP9 TMS320DM646x DMSoC ARM Subsystem Reference Guide.Describes the ARM subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP subsystem and a majority of the peripherals and external memories.

SPRUEQ0 TMS320DM646x DMSoC Peripherals Overview Reference Guide.Provides an overview and briefly describes the peripherals available on the TMS320DM646x Digital Media System-on-Chip (DMSoC).

SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide.Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included.

SPRU732 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide.Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.

6

Preface

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Related Documentation From Texas Instruments

SPRU871 TMS320C64x+ DSP Megamodule Reference Guide.Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.

SPRUEQ7C –February2010

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