Texas Instruments TMS320DM646X DMSOC User Manual
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TMS320DM646x DMSoC

Asynchronous External Memory Interface (EMIF)

User's Guide

Literature Number: SPRUEQ7C

February 2010

2

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Preface .......................................................................................................................................

 

6

1

Introduction ........................................................................................................................

8

 

1.1

Purpose of the Peripheral ..............................................................................................

8

 

1.2

Features ..................................................................................................................

8

 

1.3

Functional Block Diagram ..............................................................................................

9

2

Architecture ........................................................................................................................

9

 

2.1

Clock Control .............................................................................................................

9

 

2.2

EMIF Requests ..........................................................................................................

9

 

2.3

Signal Descriptions ....................................................................................................

10

 

2.4

Pin Multiplexing ........................................................................................................

10

 

2.5

Asynchronous Controller and Interface .............................................................................

10

3

Use Cases ........................................................................................................................

30

 

3.1

Interfacing to Asynchronous SRAM (ASRAM) .....................................................................

30

 

3.2

Interfacing to NAND Flash ............................................................................................

39

4

Registers ..........................................................................................................................

48

 

4.1

Revision Code and Status Register (RCSR) .......................................................................

49

 

4.2

Asynchronous Wait Cycle Configuration Register (AWCCR) ....................................................

50

 

4.3

Asynchronous n Configuration Registers (A1CR-A4CR) .........................................................

52

 

4.4

EMIF Interrupt Raw Register (EIRR) ................................................................................

53

 

4.5

EMIF Interrupt Mask Register (EIMR) ...............................................................................

54

 

4.6

EMIF Interrupt Mask Set Register (EIMSR) ........................................................................

56

 

4.7

EMIF Interrupt Mask Clear Register (EIMCR) .....................................................................

58

 

4.8

NAND Flash Control Register (NANDFCR) ........................................................................

60

 

4.9

NAND Flash Status Register (NANDFSR) .........................................................................

61

 

4.10

NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) ...................................................

61

Appendix A

Revision History ......................................................................................................

63

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Table of Contents

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List of Figures

 

1

EMIF Functional Block Diagram ..........................................................................................

9

2

EMIF Asynchronous Interface ...........................................................................................

11

3

EMIF to 8-bit and 16-bit Memory Interfaces ...........................................................................

11

4

Timing Waveform of an Asynchronous Read Cycle in Normal Mode ..............................................

15

5

Timing Waveform of an Asynchronous Write Cycle in Normal Mode ..............................................

17

6

Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode.......................................

19

7

Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode .......................................

21

8

EMIF to NAND Flash Interface ..........................................................................................

23

9

ECC Value for 8-Bit NAND Flash .......................................................................................

25

10

EMIF to 16-Bit Multiplexed HPI16 Interface............................................................................

26

11

Connecting the EMIF to the TC55V16100FT-12 ......................................................................

30

12

Timing Waveform of an ASRAM Read ................................................................................

32

13

Timing Waveform of an ASRAM Write .................................................................................

33

14

Timing Waveform of an ASRAM Read with PCB Delays ............................................................

35

15

Timing Waveform of an ASRAM Write with PCB Delays ............................................................

36

16

Timing Waveform of a NAND Flash Read ............................................................................

41

17

Timing Waveform of a NAND Flash Command Write ...............................................................

43

18

Timing Waveform of a NAND Flash Address Write ..................................................................

43

19

Timing Waveform of a NAND Flash Data Write ......................................................................

44

20

Revision Code and Status Register (RCSR) ..........................................................................

49

21

Asynchronous Wait Cycle Configuration Register (AWCCR)........................................................

50

22

Asynchronous n Configuration Register (ACFGn) ....................................................................

52

23

EMIF Interrupt Raw Register (EIRR)....................................................................................

53

24

EMIF Interrupt Mask Register (EIMR) ..................................................................................

54

25

EMIF Interrupt Mask Set Register (EIMSR)............................................................................

56

26

EMIF Interrupt Mask Clear Register (EIMCR) .........................................................................

58

27

NAND Flash Control Register (NANDFCR)............................................................................

60

28

NAND Flash Status Register (NANDFSR) .............................................................................

61

29

NAND Flash n ECC Register (NANDECCn)...........................................................................

62

4

List of Figures

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List of Tables

 

1

EMIF Pins ..................................................................................................................

10

2

Behavior of EM_CS Signal Between Normal Mode and Select Strobe Mode.....................................

10

3

Description of the Asynchronous Configuration Register (ACFGn).................................................

12

4

Description of the Asynchronous Wait Cycle Configuration Register (AWCCR)..................................

13

5

Description of the EMIF Interrupt Mask Set Register (EIMSR)......................................................

13

6

Description of the EMIF Interrupt Mast Clear Register (EIMCR)....................................................

13

7

Asynchronous Read Operation in Normal Mode ......................................................................

14

8

Asynchronous Write Operation in Normal Mode ......................................................................

16

9

Asynchronous Read Operation in Select Strobe Mode ..............................................................

18

10

Asynchronous Write Operation in Select Strobe Mode...............................................................

20

11

Description of the NAND Flash Control Register (NANDFCR) ......................................................

22

12

Configuration For NAND Flash .........................................................................................

22

13

EMIF Interrupt..............................................................................................................

28

14

Interrupt Monitor and Control Bit Fields ................................................................................

28

15

EMIF Input Timing Requirements .......................................................................................

31

16

ASRAM Output Timing Characteristics .................................................................................

31

17

ASRAM Input Timing Requirement for a Read ........................................................................

31

18

ASRAM Input Timing Requirements for a Write ......................................................................

32

19

ASRAM Timing Requirements With PCB Delays .....................................................................

34

20

EMIF Timing Requirements for TC5516100FT-12 Example ........................................................

37

21

ASRAM Timing Requirements for TC5516100FT-12Example.....................................................

37

22

Measured PCB Delays for TC5516100FT-12 Example ..............................................................

37

23

Configuring A2CR for TC5516100FT-12 Example....................................................................

39

24

Recommended Margins ..................................................................................................

39

25

EMIF Read Timing Requirements.......................................................................................

40

26

NAND Flash Read Timing Requirements ..............................................................................

40

27

NAND Flash Write Timing Requirements .............................................................................

42

28

EMIF Timing Requirements for HY27UA081G1M Example .........................................................

45

29

NAND Flash Timing Requirements for HY27UA081G1M Example ................................................

45

30

Configuring A1CR for HY27UA081G1M Example ....................................................................

47

31

Configuring NANDFCR for HY27UA081G1M Example ..............................................................

47

32

External Memory Interface (EMIF) Registers ..........................................................................

48

33

Revision Code and Status Register (RCSR) Field Descriptions ....................................................

49

34

Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions .................................

50

35

Asynchronous n Configuration Register (ACFGn) Field Descriptions..............................................

52

36

EMIF Interrupt Raw Register (EIRR) Field Descriptions .............................................................

53

37

EMIF Interrupt Mask Register (EIMR) Field Descriptions ............................................................

54

38

EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions .....................................................

56

39

EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions...................................................

58

40

NAND Flash Control Register (NANDFCR) Field Descriptions .....................................................

60

41

NAND Flash Status Register (NANDFSR) Field Descriptions.......................................................

61

42

NAND Flash n ECC Register (NANDECCn) Field Descriptions....................................................

62

43

Document Revision History ..............................................................................................

63

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List of Tables

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Preface

SPRUEQ7C – February 2010

Read This First

About This Manual

This document describes the asynchronous external memory interface (EMIF) in the TMS320DM646x Digital Media System-on-Chip(DMSoC). The EMIF supports a glueless interface to a variety of external devices.

Notational Conventions

This document uses the following conventions.

Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.

Registers in this document are shown in figures and described in tables.

Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.

Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments

The following documents describe the TMS320DM646x Digital Media System-on-Chip(DMSoC). Copies of these documents are available on the Internet atwww.ti.com.Tip: Enter the literature number in the search box provided at www.ti.com.

The current documentation that describes the DM646x DMSoC, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.

SPRUEP8 TMS320DM646x DMSoC DSP Subsystem Reference Guide.Describes the digital signal processor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC).

SPRUEP9 TMS320DM646x DMSoC ARM Subsystem Reference Guide.Describes the ARM subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP subsystem and a majority of the peripherals and external memories.

SPRUEQ0 TMS320DM646x DMSoC Peripherals Overview Reference Guide.Provides an overview and briefly describes the peripherals available on the TMS320DM646x Digital Media System-on-Chip (DMSoC).

SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide.Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included.

SPRU732 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide.Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.

6

Preface

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Related Documentation From Texas Instruments

SPRU871 TMS320C64x+ DSP Megamodule Reference Guide.Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.

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User's Guide

SPRUEQ7C – February 2010

Asynchronous External Memory Interface (EMIF)

1Introduction

This document describes the operation of the asynchronous external memory interface (EMIF) in the TMS320DM646x Digital Media System-on-Chip(DMSoC).

1.1Purpose of the Peripheral

The purpose of this EMIF is to provide a means to connect to a variety of external devices including:

NAND Flash

Asynchronous devices including Flash and SRAM

Host processor interfaces such as the host port interface (HPI) on a Texas Instruments Digital Signal Processor (DSP)

The most common use for the EMIF is to interface with both flash devices and SRAM devices. The Example Configuration section contains examples of operating the EMIF in this configuration.

1.2Features

The EMIF includes many features to enhance the ease and flexibility of connecting to external asynchronous devices. The EMIF features includes support for:

4 addressable chip select spaces of up to 32MB each

8-bitand16-bitdata bus widths

Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time

Select strobe mode

Extended Wait mode

NAND Flash ECC generation

Connecting as a host to a TI DSP HPI interface

Data bus parking

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Architecture

1.3Functional Block Diagram

Figure 1 illustrates the connections between the EMIF and its internal requesters, along with the external EMIF pins.Section 2.2 contains a description of the entities internal to the device that can send requests to the EMIF, along with their prioritization.Section 2.3 describes the EMIF'sexternal pins and summarizes their purpose when interfacing with SDRAM and asynchronous devices.

 

Figure 1. EMIF Functional Block Diagram

VICP

EMIF

 

 

EM_CS[5:2]

 

EM_OE

DSP

EM_RW

 

EM_WAIT[5:2]

 

SCR

 

EM_WE

ARM

EM_BA[1:0]

 

 

EM_D[15:0]

EDMA3

EM_A[22:0]

 

Master peripherals

 

2Architecture

This section provides details about the architecture and operation of the EMIF.

2.1Clock Control

The EMIF'sinternal clock is sourced from the SYSCLK3 clock domain of PLL controller 0 and cannot be sourced directly from an external input clock. The frequency of the SYSCLK3 clock domain is the PLL0 frequency divided by 4. Changes to the frequency of the input clock to PLL controller 0 and to the PLL controller 0 multiplier values alters the operating frequency of the EMIF. See the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9) for more information on how to program the PLL controller.

2.2EMIF Requests

Four different sources within the device can make requests to the EMIF. These requests consist of accesses to asynchronous memory and EMIF memory-mappedregisters. Because the EMIF can process only one request at a time, a high performance switched central resource (SCR) exists to provide prioritized requests from the different sources to the EMIF. Each requester has a programmable priority value that may be configured in the System Module MSTPRI0 register or in the EDMACC QUEPRI register. See thedevice-specificdata manual for more information.

If a request is submitted from two or more sources simultaneously, the SCR will forward the highest priority request to the EMIF first. Upon completion of a request, the SCR again evaluates the pending requests and forwards the highest priority pending request to the EMIF.

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2.3Signal Descriptions

Table 1 describes the function of each of the EMIF pins.

 

 

 

 

 

 

 

 

Table 1. EMIF Pins

 

 

 

 

 

Pins(s)

I/O

Description

 

 

 

 

 

EM_ A[22:0]

O

EMIF address bus. These pins are used in conjunction with the EM_BA pins to form the address that is

 

 

 

 

 

 

 

 

sent to the device.

 

EM_BA[1:0]

O

EMIF bank address. These pins are used in conjunction with the EM_A pins to form the address that is

 

 

 

 

 

 

 

 

sent to the device.

 

 

 

O

Active-lowchip enable pin for asynchronous devices. These pins are meant to be connected to the

 

EM_CS[5:2]

 

 

 

 

 

 

 

 

chip-selectpin of the attached asynchronous device.

 

EM_D[15:0]

I/O

EMIF data bus.

 

 

 

 

 

O

Read/Write select pin. This pin is high for the duration of an asynchronous read access cycle and low

 

EM_RW

 

 

 

 

 

 

 

 

for the duration of an asynchronous write cycle.

 

 

 

 

 

 

O

Active-lowpin enable for asynchronous devices. This pin provides a signal which isactive-lowduring

 

EM_OE

 

 

 

 

 

 

 

 

the strobe period of an asynchronous read access cycle.

 

 

 

 

 

 

 

O

Active-lowwrite enable. This pin provides a signal which isactive-lowduring the strobe period of an

 

EM_WE

 

 

 

 

 

 

 

 

asynchronous write access cycle.

 

EM_WAIT[5:2]

I

Wait input with programmable polarity. A connected asynchronous device can extend the strobe period

 

 

 

 

 

 

 

 

of an access cycle by asserting the WAIT input to the EMIF as described in Section 2.5.8. To enable

 

 

 

 

 

 

 

 

this functionality, the EW bit in the asynchronous configuration register (ACFGn) must be set to 1. In

 

 

 

 

 

 

 

 

addition, the WPn bit in the asynchronous wait cycle configuration register (AWCCR) must be

 

 

 

 

 

 

 

 

configured to define the polarity of the EM_WAITn pin.

 

 

 

 

 

 

 

 

 

2.4Pin Multiplexing

The EMIF pins are multiplexed with other peripherals such as PCI, HPI, GPIO, and ATA. See the device-specificdata manual for instructions on how to select the EMIF pins for proper operation.

2.5Asynchronous Controller and Interface

The EMIF easily interfaces to a variety of asynchronous devices including Flash and ASRAM. It can be operated in three major modes:

Normal mode

Select Strobe (SS) mode

NAND Flash mode

The behavior of the EM_CS signal is the single difference between Normal mode and Select Strobe mode (seeTable 2). In Normal mode, the EM_CS signal becomes active at the beginning of the setup period and remains active for the duration of the transfer. In Select Strobe mode, the EM_CS signal functions as a strobe signal, active only during the strobe period of an access.

In NAND Flash mode, the EMIF hardware is able to calculate the error correction code (ECC) for each 512 byte data transfer. In addition to the three modes of operation, the EMIF also provides configurable cycle timing parameters and an Extended Wait mode that allows the connected device to extend the strobe period of an access cycle. The following sections describe the features related to interfacing with external asynchronous devices.

Table 2. Behavior of EM_CS Signal Between Normal Mode and

Select Strobe Mode

 

 

 

 

Mode

Operation of EM_CS[5:2]

Normal

Active during the entire asynchronous access cycle

Select Strobe

Active only during the strobe period of an access cycle

 

 

 

 

10

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