Texas Instruments TMS320DM643x User Manual
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TMS320DM643x DMP

DSP Subsystem

Reference Guide

Literature Number: SPRU978E

March 2008

2

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Contents

Preface ...............................................................................................................................

 

9

1

Introduction .............................................................................................................

11

 

1.1

Introduction.........................................................................................................

12

 

1.2

Block Diagram .....................................................................................................

12

 

1.3

DSP Subsystem in TMS320DM643x DMP ....................................................................

13

 

 

1.3.1 Components of the DSP Subsystem ..................................................................

13

2

TMS320C64x+ Megamodule .......................................................................................

15

 

2.1

Introduction.........................................................................................................

16

 

2.2

TMS320C64x+ CPU ..............................................................................................

16

 

2.3

Memory Controllers ...............................................................................................

18

 

 

2.3.1

L1P Controller ............................................................................................

18

 

 

2.3.2

L1D Controller ............................................................................................

20

 

 

2.3.3

L2 Controller ..............................................................................................

20

 

 

2.3.4 External Memory Controller (EMC) ....................................................................

21

 

 

2.3.5

Internal DMA (IDMA).....................................................................................

21

 

2.4

Internal Peripherals ...............................................................................................

22

 

 

2.4.1

Interrupt Controller (INTC) ..............................................................................

22

 

 

2.4.2

Power-Down Controller (PDC)..........................................................................

22

 

 

2.4.3

Bandwidth Manager......................................................................................

23

3

System Memory .......................................................................................................

25

 

3.1

Memory Map .......................................................................................................

26

 

 

3.1.1 DSP Internal Memory (L1P, L1D, L2) .................................................................

26

 

 

3.1.2

External Memory .........................................................................................

26

 

 

3.1.3

Internal Peripherals ......................................................................................

26

 

 

3.1.4

Device Peripherals .......................................................................................

26

 

3.2

Memory Interfaces Overview ....................................................................................

27

 

 

3.2.1 DDR2 External Memory Interface ......................................................................

27

 

 

3.2.2

External Memory Interface ..............................................................................

27

4

Device Clocking .......................................................................................................

29

 

4.1

Overview............................................................................................................

30

 

4.2

Clock Domains.....................................................................................................

30

 

 

4.2.1

Core Domains ............................................................................................

30

 

 

4.2.2

Core Frequency Flexibility ..............................................................................

32

 

 

4.2.3

DDR2/EMIF Clock........................................................................................

33

 

 

4.2.4

I/O Domains...............................................................................................

34

 

 

4.2.5 Video Processing Back End ............................................................................

35

5

PLL Controller ..........................................................................................................

 

37

 

5.1

PLL Module ........................................................................................................

 

38

 

5.2

PLL1 Control .......................................................................................................

 

38

 

 

5.2.1

Device Clock Generation................................................................................

 

39

 

 

5.2.2 Steps for Changing PLL1/Core Domain Frequency .................................................

 

39

 

5.3

PLL2 Control .......................................................................................................

 

43

 

 

5.3.1

Device Clock Generation................................................................................

 

43

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5.3.2 Steps for Changing PLL2 Frequency ..................................................................

44

 

 

5.4

PLL Controller Registers .........................................................................................

48

 

 

 

5.4.1 Peripheral ID Register (PID) ............................................................................

49

 

 

 

5.4.2 Reset Type Status Register (RSTYPE) ...............................................................

49

 

 

 

5.4.3 PLL Control Register (PLLCTL) ........................................................................

50

 

 

 

5.4.4 PLL Multiplier Control Register (PLLM) ...............................................................

51

 

 

 

5.4.5 PLL Controller Divider 1 Register (PLLDIV1).........................................................

51

 

 

 

5.4.6 PLL Controller Divider 2 Register (PLLDIV2).........................................................

52

 

 

 

5.4.7 PLL Controller Divider 3 Register (PLLDIV3).........................................................

52

 

 

 

5.4.8 Oscillator Divider 1 Register (OSCDIV1)..............................................................

53

 

 

 

5.4.9 Bypass Divider Register (BPDIV) ......................................................................

54

 

 

 

5.4.10 PLL Controller Command Register (PLLCMD)......................................................

55

 

 

 

5.4.11 PLL Controller Status Register (PLLSTAT)..........................................................

55

 

 

 

5.4.12 PLL Controller Clock Align Control Register (ALNCTL)............................................

56

 

 

 

5.4.13 PLLDIV Ratio Change Status Register (DCHANGE)...............................................

57

 

 

 

5.4.14 Clock Enable Control Register (CKEN) ..............................................................

58

 

 

 

5.4.15 Clock Status Register (CKSTAT) .....................................................................

59

 

 

 

5.4.16 SYSCLK Status Register (SYSTAT)..................................................................

60

 

6

Power and Sleep Controller .......................................................................................

61

 

 

6.1

Introduction.........................................................................................................

62

 

 

6.2

Power Domain and Module Topology ..........................................................................

63

 

 

6.3

Power Domain and Module States..............................................................................

64

 

 

 

6.3.1

Power Domain States....................................................................................

64

 

 

 

6.3.2

Module States ............................................................................................

64

 

 

 

6.3.3

Local Reset ...............................................................................................

65

 

 

6.4

Executing State Transitions......................................................................................

65

 

 

 

6.4.1 Power Domain State Transitions .......................................................................

65

 

 

 

6.4.2

Module State Transitions................................................................................

65

 

 

6.5

IcePick Emulation Support in the PSC .........................................................................

66

 

 

6.6

PSC Interrupts .....................................................................................................

66

 

 

 

6.6.1

Interrupt Events...........................................................................................

66

 

 

 

6.6.2

Interrupt Registers........................................................................................

67

 

 

 

6.6.3

Interrupt Handling ........................................................................................

68

 

 

6.7

PSC Registers .....................................................................................................

68

 

 

 

6.7.1 Peripheral Revision and Class Information Register (PID) .........................................

69

 

 

 

6.7.2 Interrupt Evaluation Register (INTEVAL)..............................................................

69

 

 

 

6.7.3 Module Error Pending Register 1 (MERRPR1) ......................................................

70

 

 

 

6.7.4 Module Error Clear Register 1 (MERRCR1)..........................................................

70

 

 

 

6.7.5 Power Domain Transition Command Register (PTCMD) ...........................................

71

 

 

 

6.7.6 Power Domain Transition Status Register (PTSTAT) ...............................................

71

 

 

 

6.7.7 Power Domain Status 0 Register (PDSTAT0)........................................................

72

 

 

 

6.7.8 Power Domain Control 0 Register (PDCTL0) ........................................................

73

 

 

 

6.7.9 Module Status n Register (MDSTATn) ................................................................

74

 

 

 

6.7.10 Module Control n Register (MDCTLn)................................................................

75

 

7

Power Management ..................................................................................................

77

 

 

7.1

Overview............................................................................................................

78

 

 

7.2

PSC and PLLC Overview ........................................................................................

78

 

 

7.3

Clock Management ...............................................................................................

79

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7.3.1

Module Clock ON/OFF ..................................................................................

79

 

 

7.3.2 Module Clock Frequency Scaling ......................................................................

79

 

 

7.3.3 PLL Bypass and Power Down..........................................................................

79

 

7.4

DSP Sleep Mode Management .................................................................................

80

 

 

7.4.1

DSP Sleep Modes........................................................................................

80

 

 

7.4.2 DSP Module Clock ON/OFF ............................................................................

80

 

7.5

3.3 V I/O Power Down............................................................................................

81

 

7.6

Video DAC Power Down .........................................................................................

81

8

Interrupt Controller ...................................................................................................

83

9

System Module ........................................................................................................

85

 

9.1

Overview............................................................................................................

86

 

9.2

Device Identification...............................................................................................

86

 

9.3

Device Configuration..............................................................................................

86

 

 

9.3.1

Pin Multiplexing Control .................................................................................

86

 

 

9.3.2 Device Boot Configuration Status ......................................................................

86

 

9.4

3.3 V I/O Power-Down Control ..................................................................................

87

 

9.5

Peripheral Status and Control ...................................................................................

87

 

 

9.5.1

Timer Control .............................................................................................

87

 

 

9.5.2 VPSS Clock and DAC Control..........................................................................

87

 

 

9.5.3

DDR2 VTP Control .......................................................................................

87

 

 

9.5.4

HPI Control................................................................................................

87

 

9.6

Bandwidth Management..........................................................................................

88

 

 

9.6.1 Bus Master DMA Priority Control.......................................................................

88

 

 

9.6.2 EDMA Transfer Controller Configuration..............................................................

89

 

9.7

Boot Control........................................................................................................

89

10

Reset

......................................................................................................................

 

91

 

10.1

Overview............................................................................................................

92

 

10.2

Reset Pins..........................................................................................................

92

 

10.3 Device Configurations at Reset .................................................................................

92

 

10.4

DSP Reset .........................................................................................................

93

 

 

10.4.1

DSP Local Reset ........................................................................................

93

 

 

10.4.2

DSP Module Reset......................................................................................

93

11

Boot Modes

.............................................................................................................

95

A

Revision History .......................................................................................................

97

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List of Figures

1-1

TMS320DM643x DMP Block Diagram ..................................................................................

12

2-1

TMS320C64x+ Megamodule Block Diagram ...........................................................................

17

2-2

C64x+ Cache Memory Architecture......................................................................................

19

4-1

Overall Clocking Diagram .................................................................................................

31

4-2

VPBE/DAC Clocking .......................................................................................................

35

5-1

PLL1 Structure in the TMS320DM643x DMP ..........................................................................

39

5-2

PLL2 Structure in the TMS320DM643x DMP ..........................................................................

43

5-3

Peripheral ID Register (PID) ..............................................................................................

49

5-4

Reset Type Status Register (RSTYPE) .................................................................................

49

5-5

PLL Control Register (PLLCTL) ..........................................................................................

50

5-6

PLL Multiplier Control Register (PLLM) .................................................................................

51

5-7

PLL Controller Divider 1 Register (PLLDIV1)...........................................................................

51

5-8

PLL Controller Divider 2 Register (PLLDIV2) ..........................................................................

52

5-9

PLL Controller Divider 3 Register (PLLDIV3) ..........................................................................

52

5-10

Oscillator Divider 1 Register (OSCDIV1)................................................................................

53

5-11

Bypass Divider Register (BPDIV) ........................................................................................

54

5-12

PLL Controller Command Register (PLLCMD).........................................................................

55

5-13

PLL Controller Status Register (PLLSTAT).............................................................................

55

5-14

PLL Controller Clock Align Control Register (ALNCTL)...............................................................

56

5-15

PLLDIV Ratio Change Status Register (DCHANGE)..................................................................

57

5-16

Clock Enable Control Register (CKEN) .................................................................................

58

5-17

Clock Status Register (CKSTAT) ........................................................................................

59

5-18

SYSCLK Status Register (SYSTAT).....................................................................................

60

6-1

Power and Sleep Controller (PSC) Integration .........................................................................

62

6-2

Peripheral Revision and Class Information Register (PID) ...........................................................

69

6-3

Interrupt Evaluation Register (INTEVAL)................................................................................

69

6-4

Module Error Pending Register 1 (MERRPR1) ........................................................................

70

6-5

Module Error Clear Register 1 (MERRCR1)............................................................................

70

6-6

Power Domain Transition Command Register (PTCMD) .............................................................

71

6-7

Power Domain Transition Status Register (PTSTAT) .................................................................

71

6-8

Power Domain Status 0 Register (PDSTAT0)..........................................................................

72

6-9

Power Domain Control 0 Register (PDCTL0) ..........................................................................

73

6-10

Module Status n Register (MDSTATn) ..................................................................................

74

6-11

Module Control n Register (MDCTLn)...................................................................................

75

6

List of Figures

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List of Tables

4-1

System Clock Modes and Fixed Ratios for Core Clock Domains....................................................

30

4-2

Example PLL1 Frequencies and Dividers (27 MHZ Clock Input) ....................................................

32

4-3

Example PLL2 Frequencies (Core Voltage = 1.2V) ...................................................................

33

4-4

Example PLL2 Frequencies (Core Voltage = 1.05V)..................................................................

33

4-5

Peripheral I/O Domain Clock .............................................................................................

34

4-6

Possible Clocking Modes..................................................................................................

36

5-1

System PLLC1 Output Clocks ............................................................................................

39

5-2

DDR PLLC2 Output Clocks ...............................................................................................

43

5-3

PLL and Reset Controller List ............................................................................................

48

5-4

PLL and Reset Controller Registers .....................................................................................

48

5-5

Peripheral ID Register (PID) Field Descriptions........................................................................

49

5-6

Reset Type Status Register (RSTYPE) Field Descriptions ...........................................................

49

5-7

PLL Control Register (PLLCTL) Field Descriptions....................................................................

50

5-8

PLL Multiplier Control Register (PLLM) Field Descriptions ...........................................................

51

5-9

PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions ....................................................

51

5-10

PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions ....................................................

52

5-11

PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions ....................................................

52

5-12

Oscillator Divider 1 Register (OSCDIV1) Field Descriptions .........................................................

53

5-13

Bypass Divider Register (BPDIV) Field Descriptions..................................................................

54

5-14

PLL Controller Command Register (PLLCMD) Field Descriptions...................................................

55

5-15

PLL Controller Status Register (PLLSTAT) Field Descriptions.......................................................

55

5-16

PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions ........................................

56

5-17

PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ...........................................

57

5-18

Clock Enable Control Register (CKEN) Field Descriptions ...........................................................

58

5-19

Clock Status Register (CKSTAT) Field Descriptions ..................................................................

59

5-20

SYSCLK Status Register (SYSTAT) Field Descriptions ..............................................................

60

6-1

DM643x DMP Default Module Configuration ...........................................................................

63

6-2

Module States ..............................................................................................................

64

6-3

IcePick Emulation Commands............................................................................................

66

6-4

PSC Interrupt Events ......................................................................................................

66

6-5

Power and Sleep Controller (PSC) Registers ..........................................................................

68

6-6

Peripheral Revision and Class Information Register (PID) Field Descriptions .....................................

69

6-7

Interrupt Evaluation Register (INTEVAL) Field Descriptions .........................................................

69

6-8

Module Error Pending Register 1 (MERRPR1) Field Descriptions ..................................................

70

6-9

Module Error Clear Register 1 (MERRCR1) Field Descriptions .....................................................

70

6-10

Power Domain Transition Command Register (PTCMD) Field Descriptions.......................................

71

6-11

Power Domain Transition Status Register (PTSTAT) Field Descriptions...........................................

71

6-12

Power Domain Status 0 Register (PDSTAT0) Field Descriptions ...................................................

72

6-13

Power Domain Control 0 Register (PDCTL0) Field Descriptions ....................................................

73

6-14

Module Status n Register (MDSTATn) Field Descriptions............................................................

74

6-15

Module Control n Register (MDCTLn) Field Descriptions.............................................................

75

7-1

Power Management Features ............................................................................................

78

9-1

TMS320DM643x DMP Master IDs.......................................................................................

88

9-2

TMS320DM643x DMP Default Master Priorities .......................................................................

89

10-1

Reset Types.................................................................................................................

92

A-1

Document Revision History ...............................................................................................

97

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List of Tables

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List of Tables

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Preface

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About This Manual

This document describes the DSP subsystem in the TMS320DM643x Digital Media Processor (DMP).

Notational Conventions

This document uses the following conventions.

Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.

Registers in this document are shown in figures and described in tables.

Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.

Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments

The following documents describe the TMS320DM643x Digital Media Processor (DMP). Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.

The current documentation that describes the DM643x DMP, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.

SPRU983 TMS320DM643x DMP Peripherals Overview Reference Guide.Provides an overview and briefly describes the peripherals available on the TMS320DM643x Digital Media Processor (DMP).

SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide.Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included.

SPRU732 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide.Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.

SPRU871 TMS320C64x+ DSP Megamodule Reference Guide.Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.

SPRU862 TMS320C64x+ DSP Cache User's Guide. Explains the fundamentals of memory caches and describes how thetwo-levelcache-basedinternal memory architecture in the TMS320C64x+ digital signal processor (DSP) of the TMS320C6000 DSP family can be efficiently used in DSP applications. Shows how to maintain coherence with external memory, how to use DMA to reduce memory latencies, and how to optimize your code to improve cache efficiency. The internal memory architecture in the C64x+ DSP is organized in atwo-levelhierarchy consisting of a dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external memory.

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TMS320C6000, C6000 are trademarks of Texas Instruments.

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