Texas Instruments TMS320C6747 DSP User Manual
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TMS320C6747 DSP

Universal Serial Bus (USB)

OHCI Host Controller

User's Guide

Literature Number: SPRUFM8

September 2008

2

SPRUFM8–September2008

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Contents

Preface ........................................................................................................................................

 

6

1

Introduction.........................................................................................................................

7

 

1.1

Purpose of the Peripheral................................................................................................

7

2

Architecture ........................................................................................................................

8

 

2.1

USB1 Module Clock and Reset ........................................................................................

8

 

2.2

USB1 Module Open Host Controller Interface Functionality ........................................................

9

 

2.3

USB1 Module Differences From OHCI Specification for USB ......................................................

9

 

2.4

Implementation of OHCI Specification for USB......................................................................

10

 

2.5

OHCI Interrupts ..........................................................................................................

11

 

2.6

USB Host Controller Access to System Memory....................................................................

11

 

2.7

Physical Addressing.....................................................................................................

11

3

Registers...........................................................................................................................

12

 

3.1

OHCI Revision Number Register (HCREVISION)...................................................................

13

 

3.2

HC Operating Mode Register (HCCONTROL) ......................................................................

13

 

3.3

HC Command and Status Register (HCCOMMANDSTATUS) ....................................................

15

 

3.4

HC Interrupt and Status Register (HCINTERRUPTSTATUS) .....................................................

16

 

3.5

HC Interrupt Enable Register (HCINTERRUPTENABLE)..........................................................

17

 

3.6

HC Interrupt Disable Register (HCINTERRUPTDISABLE) ........................................................

18

 

3.7

HC HCAA Address Register (HCHCCA) .............................................................................

19

 

3.8

HC Current Periodic Register (HCPERIODCURRENTED) ........................................................

19

 

3.9

HC Head Control Register (HCCONTROLHEADED)...............................................................

20

 

3.10

HC Current Control Register (HCCONTROLCURRENTED) ......................................................

21

 

3.11

HC Head Bulk Register (HCBULKHEADED) ........................................................................

22

 

3.12

HC Current Bulk Register (HCBULKCURRENTED) ................................................................

22

 

3.13

HC Head Done Register (HCDONEHEAD) ..........................................................................

23

 

3.14

HC Frame Interval Register (HCFMINTERVAL) ....................................................................

23

 

3.15

HC Frame Remaining Register (HCFMREMAINING) ..............................................................

24

 

3.16

HC Frame Number Register (HCFMNUMBER) .....................................................................

24

 

3.17

HC Periodic Start Register (HCPERIODICSTART) .................................................................

25

 

3.18

HC Low-Speed Threshold Register (HCLSTHRESHOLD).........................................................

26

 

3.19

HC Root Hub A Register (HCRHDESCRIPTORA)..................................................................

27

 

3.20

HC Root Hub B Register (HCRHDESCRIPTORB)..................................................................

28

 

3.21

HC Root Hub Status Register (HCRHSTATUS).....................................................................

29

 

3.22

HC Port 1 Status and Control Register (HCRHPORTSTATUS1) .................................................

30

 

3.23

HC Port 2 Status and Control Register (HCRHPORTSTATUS2) .................................................

32

SPRUFM8–September2008

Table of Contents

3

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List of Figures

 

1

Relationships Between Virtual Address Physical Address............................................................

11

2

OHCI Revision Number Register (HCREVISION) .....................................................................

13

3

HC Operating Mode Register (HCCONTROL) .........................................................................

13

4

HC Command and Status Register (HCCOMMANDSTATUS).......................................................

15

5

HC Interrupt and Status Register (HCINTERRUPTSTATUS)........................................................

16

6

HC Interrupt Enable Register (HCINTERRUPTENABLE) ............................................................

17

7

HC Interrupt Disable Register (HCINTERRUPTDISABLE) ...........................................................

18

8

HC HCAA Address Register (HCHCCA) ................................................................................

19

9

HC Current Periodic Register (HCPERIODCURRENTED) ...........................................................

19

10

HC Head Control Register (HCCONTROLHEADED) .................................................................

20

11

HC Current Control Register (HCCONTROLCURRENTED) .........................................................

21

12

HC Head Bulk Register (HCBULKHEADED) ...........................................................................

22

13

HC Current Bulk Register (HCBULKCURRENTED)...................................................................

22

14

HC Head Done Register (HCDONEHEAD).............................................................................

23

15

HC Frame Interval Register (HCFMINTERVAL) .......................................................................

23

16

HC Frame Remaining Register (HCFMREMAINING) .................................................................

24

17

HC Frame Number Register (HCFMNUMBER) ........................................................................

24

18

HC Periodic Start Register (HCPERIODICSTART)....................................................................

25

19

HC Low-Speed Threshold Register (HCLSTHRESHOLD) ...........................................................

26

20

HC Root Hub A Register (HCRHDESCRIPTORA) ....................................................................

27

21

HC Root Hub B Register (HCRHDESCRIPTORB) ....................................................................

28

22

HC Root Hub Status Register (HCRHSTATUS) .......................................................................

29

23

HC Port 1 Status and Control Register (HCRHPORTSTATUS1)....................................................

30

24

HC Port 2 Status and Control Register (HCRHPORTSTATUS2)....................................................

32

4

List of Figures

SPRUFM8–September2008

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List of Tables

 

1

USB Host Controller Registers ...........................................................................................

12

2

OHCI Revision Number Register (HCREVISION) Field Descriptions ...............................................

13

3

HC Operating Mode Register (HCCONTROL) Field Descriptions...................................................

14

4

HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions ................................

15

5

HC Interrupt and Status Register (HCINTERRUPTSTATUS) Field Descriptions..................................

16

6

HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions ......................................

17

7

HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions.....................................

18

8

HC HCAA Address Register (HCHCCA) Field Descriptions..........................................................

19

9

HC Current Periodic Register (HCPERIODCURRENTED) Field Descriptions.....................................

19

10

HC Head Control Register (HCCONTROLHEADED) Field Descriptions ...........................................

20

11

HC Current Control Register (HCCONTROLCURRENTED) Field Descriptions...................................

21

12

HC Head Bulk Register (HCBULKHEADED) Field Descriptions.....................................................

22

13

HC Current Bulk Register (HCBULKCURRENTED) Field Descriptions ............................................

22

14

HC Head Done Register (HCDONEHEAD) Field Descriptions ......................................................

23

15

HC Frame Interval Register (HCFMINTERVAL) Field Descriptions .................................................

23

16

HC Frame Remaining Register (HCFMREMAINING) Field Descriptions...........................................

24

17

HC Frame Number Register (HCFMNUMBER) Field Descriptions..................................................

24

18

HC Periodic Start Register (HCPERIODICSTART) Field Descriptions .............................................

25

19

HC Low-SpeedThreshold Register (HCLSTHRESHOLD) Field Descriptions.....................................

26

20

HC Root Hub A Register (HCRHDESCRIPTORA) Field Descriptions ..............................................

27

21

HC Root Hub B Register (HCRHDESCRIPTORB) Field Descriptions ..............................................

28

22

HC Root Hub Status Register (HCRHSTATUS) Field Descriptions .................................................

29

23

HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions .............................

30

24

HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Field Descriptions .............................

32

SPRUFM8–September2008

List of Tables

5

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Preface

SPRUFM8–September2008

Read This First

About This Manual

This document describes the universal serial bus OHCI host controller.

Notational Conventions

This document uses the following conventions.

Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.

Registers in this document are shown in figures and described in tables.

Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.

Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments

The following documents describe the TMS320C6745/C6747 DSP. Copies of these documents are available on the Internet at www.ti.com.Tip: Enter the literature number in the search box provided at www.ti.com.

The current documentation that describes the DSP, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.

SPRUFE8 TMS320C674x DSP CPU and Instruction Set Reference Guide.Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added functionality and an expanded instruction set.

SPRUFK4 TMS320C6745/C6747 DSP System Reference Guide.Describes the System-on-Chip (SoC) including the DSP subsystem, system memory, device clocking, phase-locked loop controller (PLLC), power and sleep controller (PSC), power management, and system configuration module.

SPRUFK5 TMS320C674x DSP Megamodule Reference Guide.Describes the TMS320C674x digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.

SPRUFK9 TMS320C6745/C6747 DSP Peripherals Overview Reference Guide.Provides an overview and briefly describes the peripherals available on the TMS320C6745/C6747 DSP.

SPRUG82 TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches and describes how thetwo-levelcache-basedinternal memory architecture in the TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain coherence with external memory, how to use DMA to reduce memory latencies, and how to optimize your code to improve cache efficiency. The internal memory architecture in the C674x DSP is organized in atwo-levelhierarchy consisting of a dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external memory.

6

Preface

SPRUFM8–September2008

 

 

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