Texas Instruments TMS320C6747 DSP User Manual
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TMS320C6747 DSP

Universal Serial Bus (USB)

OHCI Host Controller

User's Guide

Literature Number: SPRUFM8

September 2008

2

SPRUFM8–September2008

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Contents

Preface ........................................................................................................................................

 

6

1

Introduction.........................................................................................................................

7

 

1.1

Purpose of the Peripheral................................................................................................

7

2

Architecture ........................................................................................................................

8

 

2.1

USB1 Module Clock and Reset ........................................................................................

8

 

2.2

USB1 Module Open Host Controller Interface Functionality ........................................................

9

 

2.3

USB1 Module Differences From OHCI Specification for USB ......................................................

9

 

2.4

Implementation of OHCI Specification for USB......................................................................

10

 

2.5

OHCI Interrupts ..........................................................................................................

11

 

2.6

USB Host Controller Access to System Memory....................................................................

11

 

2.7

Physical Addressing.....................................................................................................

11

3

Registers...........................................................................................................................

12

 

3.1

OHCI Revision Number Register (HCREVISION)...................................................................

13

 

3.2

HC Operating Mode Register (HCCONTROL) ......................................................................

13

 

3.3

HC Command and Status Register (HCCOMMANDSTATUS) ....................................................

15

 

3.4

HC Interrupt and Status Register (HCINTERRUPTSTATUS) .....................................................

16

 

3.5

HC Interrupt Enable Register (HCINTERRUPTENABLE)..........................................................

17

 

3.6

HC Interrupt Disable Register (HCINTERRUPTDISABLE) ........................................................

18

 

3.7

HC HCAA Address Register (HCHCCA) .............................................................................

19

 

3.8

HC Current Periodic Register (HCPERIODCURRENTED) ........................................................

19

 

3.9

HC Head Control Register (HCCONTROLHEADED)...............................................................

20

 

3.10

HC Current Control Register (HCCONTROLCURRENTED) ......................................................

21

 

3.11

HC Head Bulk Register (HCBULKHEADED) ........................................................................

22

 

3.12

HC Current Bulk Register (HCBULKCURRENTED) ................................................................

22

 

3.13

HC Head Done Register (HCDONEHEAD) ..........................................................................

23

 

3.14

HC Frame Interval Register (HCFMINTERVAL) ....................................................................

23

 

3.15

HC Frame Remaining Register (HCFMREMAINING) ..............................................................

24

 

3.16

HC Frame Number Register (HCFMNUMBER) .....................................................................

24

 

3.17

HC Periodic Start Register (HCPERIODICSTART) .................................................................

25

 

3.18

HC Low-Speed Threshold Register (HCLSTHRESHOLD).........................................................

26

 

3.19

HC Root Hub A Register (HCRHDESCRIPTORA)..................................................................

27

 

3.20

HC Root Hub B Register (HCRHDESCRIPTORB)..................................................................

28

 

3.21

HC Root Hub Status Register (HCRHSTATUS).....................................................................

29

 

3.22

HC Port 1 Status and Control Register (HCRHPORTSTATUS1) .................................................

30

 

3.23

HC Port 2 Status and Control Register (HCRHPORTSTATUS2) .................................................

32

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Table of Contents

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List of Figures

 

1

Relationships Between Virtual Address Physical Address............................................................

11

2

OHCI Revision Number Register (HCREVISION) .....................................................................

13

3

HC Operating Mode Register (HCCONTROL) .........................................................................

13

4

HC Command and Status Register (HCCOMMANDSTATUS).......................................................

15

5

HC Interrupt and Status Register (HCINTERRUPTSTATUS)........................................................

16

6

HC Interrupt Enable Register (HCINTERRUPTENABLE) ............................................................

17

7

HC Interrupt Disable Register (HCINTERRUPTDISABLE) ...........................................................

18

8

HC HCAA Address Register (HCHCCA) ................................................................................

19

9

HC Current Periodic Register (HCPERIODCURRENTED) ...........................................................

19

10

HC Head Control Register (HCCONTROLHEADED) .................................................................

20

11

HC Current Control Register (HCCONTROLCURRENTED) .........................................................

21

12

HC Head Bulk Register (HCBULKHEADED) ...........................................................................

22

13

HC Current Bulk Register (HCBULKCURRENTED)...................................................................

22

14

HC Head Done Register (HCDONEHEAD).............................................................................

23

15

HC Frame Interval Register (HCFMINTERVAL) .......................................................................

23

16

HC Frame Remaining Register (HCFMREMAINING) .................................................................

24

17

HC Frame Number Register (HCFMNUMBER) ........................................................................

24

18

HC Periodic Start Register (HCPERIODICSTART)....................................................................

25

19

HC Low-Speed Threshold Register (HCLSTHRESHOLD) ...........................................................

26

20

HC Root Hub A Register (HCRHDESCRIPTORA) ....................................................................

27

21

HC Root Hub B Register (HCRHDESCRIPTORB) ....................................................................

28

22

HC Root Hub Status Register (HCRHSTATUS) .......................................................................

29

23

HC Port 1 Status and Control Register (HCRHPORTSTATUS1)....................................................

30

24

HC Port 2 Status and Control Register (HCRHPORTSTATUS2)....................................................

32

4

List of Figures

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List of Tables

 

1

USB Host Controller Registers ...........................................................................................

12

2

OHCI Revision Number Register (HCREVISION) Field Descriptions ...............................................

13

3

HC Operating Mode Register (HCCONTROL) Field Descriptions...................................................

14

4

HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions ................................

15

5

HC Interrupt and Status Register (HCINTERRUPTSTATUS) Field Descriptions..................................

16

6

HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions ......................................

17

7

HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions.....................................

18

8

HC HCAA Address Register (HCHCCA) Field Descriptions..........................................................

19

9

HC Current Periodic Register (HCPERIODCURRENTED) Field Descriptions.....................................

19

10

HC Head Control Register (HCCONTROLHEADED) Field Descriptions ...........................................

20

11

HC Current Control Register (HCCONTROLCURRENTED) Field Descriptions...................................

21

12

HC Head Bulk Register (HCBULKHEADED) Field Descriptions.....................................................

22

13

HC Current Bulk Register (HCBULKCURRENTED) Field Descriptions ............................................

22

14

HC Head Done Register (HCDONEHEAD) Field Descriptions ......................................................

23

15

HC Frame Interval Register (HCFMINTERVAL) Field Descriptions .................................................

23

16

HC Frame Remaining Register (HCFMREMAINING) Field Descriptions...........................................

24

17

HC Frame Number Register (HCFMNUMBER) Field Descriptions..................................................

24

18

HC Periodic Start Register (HCPERIODICSTART) Field Descriptions .............................................

25

19

HC Low-SpeedThreshold Register (HCLSTHRESHOLD) Field Descriptions.....................................

26

20

HC Root Hub A Register (HCRHDESCRIPTORA) Field Descriptions ..............................................

27

21

HC Root Hub B Register (HCRHDESCRIPTORB) Field Descriptions ..............................................

28

22

HC Root Hub Status Register (HCRHSTATUS) Field Descriptions .................................................

29

23

HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions .............................

30

24

HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Field Descriptions .............................

32

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List of Tables

5

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Preface

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Read This First

About This Manual

This document describes the universal serial bus OHCI host controller.

Notational Conventions

This document uses the following conventions.

Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.

Registers in this document are shown in figures and described in tables.

Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.

Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments

The following documents describe the TMS320C6745/C6747 DSP. Copies of these documents are available on the Internet at www.ti.com.Tip: Enter the literature number in the search box provided at www.ti.com.

The current documentation that describes the DSP, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.

SPRUFE8 TMS320C674x DSP CPU and Instruction Set Reference Guide.Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added functionality and an expanded instruction set.

SPRUFK4 TMS320C6745/C6747 DSP System Reference Guide.Describes the System-on-Chip (SoC) including the DSP subsystem, system memory, device clocking, phase-locked loop controller (PLLC), power and sleep controller (PSC), power management, and system configuration module.

SPRUFK5 TMS320C674x DSP Megamodule Reference Guide.Describes the TMS320C674x digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.

SPRUFK9 TMS320C6745/C6747 DSP Peripherals Overview Reference Guide.Provides an overview and briefly describes the peripherals available on the TMS320C6745/C6747 DSP.

SPRUG82 TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches and describes how thetwo-levelcache-basedinternal memory architecture in the TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain coherence with external memory, how to use DMA to reduce memory latencies, and how to optimize your code to improve cache efficiency. The internal memory architecture in the C674x DSP is organized in atwo-levelhierarchy consisting of a dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external memory.

6

Preface

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User's Guide

SPRUFM8–September2008

Universal Serial Bus OHCI Host Controller

1Introduction

This document describes the universal serial bus OHCI host controller.

1.1Purpose of the Peripheral

The USB OHCI host controller (HC) is a single port controller that communicates with USB devices at the USB low-speed(1.5Mbit-per-secondmaximum) andfull-speed(12Mbit-per-secondmaximum) data rates. It is compatible with theUniversal Serial Bus Specification Revision 2.0 and theOpen HCI—Open Host

Controller Interface Specification for USB, Release 1.0a, available through the Compaq Computer Corporation web site, and hereafter called the OHCI Specification for USB. It is assumed that users of the USB host controller are already familiar with the USB Specificationand OHCI Specification for USB.

The USB host controller implements the register set and makes use of the memory data structures defined in the OHCI Specification for USB. These registers and data structures are the mechanisms by which a USB host controller driver software package can control the USB host controller. TheOHCI Specification for USB also defines how the USB host controller implementation must interact with those registers and data structures in system memory.

To reduce processor software and interrupt overhead, the USB host controller generates USB traffic based on data structures and data buffers stored in system memory. The USB host controller accesses these data structures without direct intervention by the processor using its bus master port. These data structures and data buffers can be located in internal or external system RAM.

The USB host controller provides an interrupt to both the ARM and DSP.

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Architecture

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2 Architecture

2.1USB1 Module Clock and Reset

The USB1 module requires that several different clocks are present before it can be accessed:

1.Internal system bus clocks for accesses by the ARM or DSP (Device SYSCLK2 and SYSCLK4)

2.Local bus clock to the USB Host controller (derived from SYSCLK4)

3.USB bus side 48-MHzreference clock must be present. Several options are available to source this clock.

2.1.1Internal System Bus Clocks Needed by the USB1 Module

The internal system bus clocks SYSCLK2 and SYSCLK4 are normally configured during the device reset process; as the device PLL controller is initialized. The USB host controller operates in the SYSCLK4 domain but SYSCLK2 since most of the device level bus infrastructure operates on the SYSCLK2 domain. Normally one or both of the host CPU clock domains (SYSCLK6 for the ARM and SYSCLK1 for the DSP) will be enabled as well.

2.1.2USB1 Module Local Bus Clock and Local Reset

The USB Host Controller actually operates from a local (gated) version of SYSCLK4. This allows the module be put into a low power state when not in use. The module also has its own local reset that is asserted during a device level reset and remains asserted until released by software. Additionally software can at any time assert a hardware reset on the USB Host Controller individually, causing it to reinitialize without affecting any of the other peripherals on the device.

Both the local clock and local reset of the USB Host Controller are under the control of the device level Power Sleep Controller 1 (PSC1) module. This module controls many local power sleep controller modules, and local power sleep controller 2 (LPSC2) of PSC1 controls the USB OHCI Host Controller.

2.1.3USB1 Module Bus 48-MHzReference Clock

This device includes an integrated USB 1.1 Phy for the OHCI Host Controller's Root Hub (Port 0). This Phy requires a 48-MHzreference clock for proper operation. Two options are available to provide this reference clock:

Use the reference clock generated by the USB0 module integrated high-speedphy. Thehigh-speedphy includes a phase locked loop (PLL) that is capable of generating a48-MHzreference clock from multiple different input clock options. This method is probably the most convenient as it does not require an externally sourced clock, and the PLL in the USB0 module has flexibility in the frequency of its input clock. However when using this option, the USB0 phy must be operating in order to use the USB1 OHCI host controller. (This does not mean that the USB0 module must be running, only that its phy needs to be configured properly and enabled).

Provide the 48 MHz clock externally, on the USB_REFCLKIN pin.

For details on device level configuration of the 48-MHzreference clock, see the device clocking chapter in theTMS320C6745/C6747 DSP System Reference Guide (SPRUFK4).

The USB host controller completes its reset after the host controller clock is transitioned from disabled to enabled and the host controller reset is removed. After system software turns on the clock to the USB host controller and removes it from reset, it is necessary to wait until the USB host controller internal reset completes. To ensure that the USB host controller has completely reset, system software must wait until reads of both the HCREVISION register and the HCHCCA register return their correct reset default values.

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Architecture

2.2USB1 Module Open Host Controller Interface Functionality

2.2.1OHCI Controller Overview

The OpenHCI—OpenHost Controller Interface Specification for USB, Release 1.0adefines a set of registers and data structures stored in system memory that control how a USB host controller interfaces to system software. This specification, in conjunction with the Universal Serial Bus Specification Version 2.0, defines most of the USB functionality that the USB host controller provides.

The OHCI Specification for USB focuses on two main aspects of the USB host controller hardware implementation: its register set and the memory data structures that define the appearance of USB bus activity. Other topics include interrupt generation, USB host controller state, USB frame management, and the hardware methods used to process the lists of data structures in system memory.

This document does not duplicate the information presented in the OHCI Specification for USB or theUSB Specification. USB host controller users can refer to theUSB Specification and theOHCI Specification for USB for detailed discussions of USB requirements and OHCI controller operation.

2.3USB1 Module Differences From OHCI Specification for USB

The USB1 Module OHCI compatible host controller implementation does not implement every aspect of the functionality defined in the OHCI Specification for USB. The differences focus on power switching, overcurrent reporting, and the OHCI ownership change interrupt. Other restrictions are imposed by the effects of the pin multiplexing options.

2.3.1Power Switching Output Pins Not Supported

The device does not provide pins that can be controlled directly by the USB host controller OHCI port power control features. The OHCI RHPORTSTATUS register port power control bits can be programmed by the USB host controller driver software, but this does not have any direct effect on any VBUS switching implemented on the board.

You can use software control of GPIO pins or other implementation-specificcontrol mechanisms to control VBUS switching.

2.3.2Overcurrent Protection Input Pins Not Supported

The device does not provide any pins that allow the USB host controller OHCI RHPORTSTATUS overcurrent protection status bits to be directly controlled by external hardware.

You can use software monitoring of GPIO pins or other implementation-specificcontrol mechanisms to report port overcurrent information to the USB host controller driver.

2.3.3No Ownership Change Interrupt

The USB host controller does not implement the OHCI ownership change interrupt.

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2.4Implementation of OHCI Specification for USB

2.4.1USB Host Controller Endpoint Descriptor (ED) List Head Pointers

The OHCI Specification for USB provides a specific sequence of operations for the host controller driver to perform when setting up the host controller. Failure to follow that sequence can result in malfunction. As a specific example, the HCCONTROLHEADED and HCBULKHEADED pointer registers and the 32 HCCAINTERRUPTTABLE pointers must all point to valid physical addresses of valid endpoint descriptors.

The USB host controller does not check HCCONTROLHEADED registers, HCBULKHEADED registers, or the values in the 32 HCCAINTERRUPTTABLE pointers before using them to access EDs. In particular if any of these pointers are NULL when the corresponding list enable bit is set, the USB host controller attempts to access using the physical address of 0, which is not a valid memory region for the USB controller to access.

2.4.2OHCI USB Suspend State

The USB host controller ignores upstream traffic from downstream devices for about 3 ms after the host controller state (HCCONTROL.HCFS) changes from USB resume state to USB operational state. If any TDs cause generation of downstream packets during that time, the downstream packets are sent, but downstream device responses are ignored. Any such TDs are aborted with completion codes marked as Device Not Responding. TDs on any of the lists (periodic, control, bulk, and isochronous) can cause such an occurrence.

The USB specification requires that system software must provide a 10-msresume recovery time (TRSMRCY) after a bus segment transitions from resume signaling to normal operational mode. During that time, only start of frame packets are to be sent on the bus segment. The system software should disable all list enable bits (HCCONTROL.PLE, HCCONTROL.IE, HCCONTROL.CLE, and HCCONTROL.BLE) and then wait for at least 1 ms before setting the host controller into USB suspend state (via HCCONTROL.HCFS). When restoring from suspend, system software must set the host controller into USB resume state, and wait for the host controller to transition into USB operational state. System software must then wait 10 ms before enabling the host controller list enable bits.

When the host controller has been placed into the USB suspend state under software control, but is brought out by a remote wake-up,system software must monitor the HCRHPORTSTATUS[x].PSS and HCRHPORTSTATUS[x].PSSC bits. The HCRHPORTSTATUS[x].PSS bit changes to 0 only after completion of resume signaling on the bus segment, and completion of the3-msperiod (packets from downstream devices are ignored).

When using port-specificsuspend, it is not necessary to disable the host controller lists, as long as there are no active EDs and TDs directed toward devices that are downstream of the suspended port. Forport-specificsuspend operations, the host controller does not issue a root hub status change interrupt (HCRHPORTSTATUS[n].PSSC bit = 1 and HCRHPORTSTATUS[n].PSS = 0), until the end of the approximately3-msdelay after the resume signaling completes.

When using port-specificsuspend, system software must ensure that there are no active EDs for devices that are downstream of the suspended port before setting the port into suspend mode. While the port is in suspend or being resumed, system software must not enable any EDs for any devices downstream of the suspended port. Once the root hub status change interrupt occurs as a result of the suspended port PSS bit changing to 0, EDs can be enabled for devices downstream of the operational port.

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