Texas Instruments TMS320C6712D User Manual
Size:
1.43 Mb
Download

TMS320C6712D FLOATING POINT DIGITAL SIGNAL PROCESSOR

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

DLow-Price/High-PerformanceFloating-PointDigital Signal Processor (DSP): TMS320C6712D

Eight 32-BitInstructions/Cycle

150-MHzClock Rate

6.7-nsInstruction Cycle Time

900 MFLOPS

DAdvanced Very Long Instruction Word (VLIW) C67x DSP Core

Eight Highly Independent Functional Units:

Four ALUs (Floatingand Fixed-Point)

Two ALUs (Fixed-Point)

Two Multipliers (Floatingand

Fixed-Point)

Load-StoreArchitecture With 3232-BitGeneral-PurposeRegisters

Instruction Packing Reduces Code Size

All Instructions Conditional

DInstruction Set Features

− Hardware Support for IEEE

Single-PrecisionandDouble-Precision

Instructions

Byte-Addressable(8-,16-,32-BitData)

8-BitOverflow Protection

Saturation

Bit-FieldExtract, Set, Clear

Bit-Counting

Normalization

DL1/L2 Memory Architecture

32K-Bit(4K-Byte)L1P Program Cache (Direct Mapped)

32K-Bit(4K-Byte)L1D Data Cache

(2-WaySet-Associative)

512K-Bit(64K-Byte)L2 Unified Mapped RAM/Cache

(Flexible Data/Program Allocation)

DDevice Configuration

Boot Mode: 8- and 16-BitROM Boot

Little Endian, Big Endian

DEnhanced Direct-Memory-Access(EDMA) Controller (16 Independent Channels)

D16-BitExternal Memory Interface (EMIF)

Glueless Interface to Asynchronous Memories: SRAM and EPROM

Glueless Interface to Synchronous Memories: SDRAM and SBSRAM

256M-ByteTotal Addressable External Memory Space

DTwo Multichannel Buffered Serial Ports (McBSPs)

Direct Interface to T1/E1, MVIP, SCSA Framers

ST-Bus-SwitchingCompatible

Up to 256 Channels Each

AC97-Compatible

Serial-Peripheral-Interface(SPI) Compatible (Motorola )

DTwo 32-BitGeneral-PurposeTimers

DFlexible Software-ConfigurablePLL-BasedClock Generator Module

DA Dedicated General-PurposeInput/Output (GPIO) Module With 5 Pins

DIEEE-1149.1(JTAG)Boundary-Scan-Compatible

D272-PinBall Grid Array (BGA) Package (GDP and ZDP Suffix)

DCMOS Technology

0.13- m/6-LevelCopper Metal Process

D3.3-VI/Os,1.20-VInternal

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320C67x and C67x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc.

Other trademarks are the property of their respective owners.

IEEE Standard1149.1-1990Standard-Test-AccessPort and Boundary Scan Architecture.

These values are compatible with existing 1.26V designs.

PRODUCTION DATA information is current as of publication date.

Copyright 2005, Texas Instruments Incorporated

Products conform to specifications per the terms of Texas Instruments

 

standard warranty. Production processing does not necessarily include

 

testing of all parameters.

 

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

1

TMS320C6712D

FLOATING POINT DIGITAL SIGNAL PROCESSOR

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

Table of Contents

revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 GDP and ZDP BGA package (bottom view) . . . . . . . . . . . . .5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 functional block and CPU (DSP core) diagram . . . . . . . . . . .9 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . .10 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . .13 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 device support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 CPU CSR register description . . . . . . . . . . . . . . . . . . . . . . . .40 cache configuration (CCFG) register description . . . . . . . .42 interrupt sources and interrupt selector . . . . . . . . . . . . . . . .43

EDMA module and EDMA selector . . . . . . . . . . . . . . . . . . . . 44

PLL and PLL controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 general-purposeinput/output (GPIO) . . . . . . . . . . . . . . . . . .53 power-downmode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 power-supplysequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 power-supplydecoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

IEEE 1149.1 JTAG compatibility statement . . . . . . . . . . . . . 58 EMIF device speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

EMIF big endian mode correctness . . . . . . . . . . . . . . . . 60 bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 61

recommended operating conditions . . . . . . . . . . . . . . . . 61

electrical characteristics over recommended ranges of supply voltage and operating case temperature . 62

parameter measurement information . . . . . . . . . . . . . . . . . .

signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . 63 timing parameters and board routing analysis . . . . . .65 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . .67 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . .70 synchronous-burstmemory timing . . . . . . . . . . . . . . . . .73 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . .75 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . .85 multichannel buffered serial port timing . . . . . . . . . . . . .86 timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 general-purposeinput/output (GPIO) port timing . . . . .96 JTAGtest-porttiming . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

2

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

TMS320C6712D

FLOATING POINT DIGITAL SIGNAL PROCESSOR

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

REVISION HISTORY

The TMS320C6712D device-specificdocumentation has been split fromTMS320C6712, TMS320C6712C, TMS320C6712D Floating−Point Digital Signal Processors , literature number SPRS148L, into a separate Data Sheet, literature number SPRS293. It also highlights technical changes made to SPRS293 to generate SPRS293A; these changes are marked by “[Revision A]” in the Revision History table below

Scope: Updated information on McBSP and JTAG for clarification. Changed Pin Description for A12 and B11 (Revisions SPRS293 and SPRS293A). Updated Nomenclature figure by adding device−specific information for the ZDP package. TI Recommends fornew designs that the following pins be configured as such:

DPin A12 connected directly to CVDD (core power)

DPin B11 connected directly to Vss (ground)

PAGE(S)

ADDITIONS/CHANGES/DELETIONS

NO.

20Device Configurations, device configurations at device reset section:

Added Note

25Terminal Functions, Bootmode section: Added Note

25Terminal Functions, Little/Big Endian Format section: Added Note

26Terminal Functions, Resets and Interrupts section: Updated IPU/IPD for RESET Signal Namefrom “IPU”to “−−”

29Terminal Functions, Reserved for Test section: Changed “IPU” to “−−” for RSV C12

Changed “IPU” to “−−” for RSV D12 Updated Type for RSV D12 from “O” to “I”

30Terminal Functions, Reserved for Test section:

Updated Description for RSV Signal Name, A12 GDP/ZDP Updated Description for RSV Signal Name, B11 GDP/ZDP

30 Terminal Functions, Reserved for Test section:

Updated/changed Description for RSV Signal Name, A12 GDP (to “recommended”) −[Revision A] Updated/changed Description for RSV Signal Name, B11 GDP (to“recommended”)− [Revision A]

38Device Support, device and development-supporttool nomenclature: Updated figure for clarity

39Device Support, document support section: Updated paragraphs for clarity

58IEEE 1149.1 JTAG Compatibility Statement section: Updated/added paragraphs for clarity

61Recommended Operating Conditions:

Added VOS, Maximum voltage during overshoot row and associated footnote Added VUS, Maximum voltage during undershoot row and associated footnote

64Parameter Measurement Information:

AC transient rise/fall time specifications section: Added AC Transient Specification Rise Time figure Added AC Transient Specification Fall Time figure

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

3

TMS320C6712D

FLOATING POINT DIGITAL SIGNAL PROCESSOR

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

PAGE(S)

ADDITIONS/CHANGES/DELETIONS

NO.

 

83RESET TIMING section: Added Note

88MULTICHANNEL BUFFERED SERIAL PORT TIMING:

switching characteristics over recommended operating conditions for McBSP section:

Updated McBSP Timings figure for clarification

4

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

TMS320C6712D

FLOATING POINT DIGITAL SIGNAL PROCESSOR

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

GDP and ZDP BGA package (bottom view)

GDP and ZDP 272-PINBALL GRID ARRAY (BGA) PACKAGE

( BOTTOM VIEW )

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11

13

15

17

19

2

4

6

8

10

12

14

16

18

20

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

5