Texas Instruments TMS320C645x DSP User Manual
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TMS320C645x DSP

Ethernet Media Access Controller (EMAC)/

Management Data Input/Output (MDIO)

User's Guide

Literature Number: SPRU975B

August 2006

2

SPRU975B –August2006

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Contents

Preface..............................................................................................................................

 

10

1

Introduction ..............................................................................................................

11

 

1.1

Purpose of the Peripheral .....................................................................................

11

 

1.2

Features .........................................................................................................

11

 

1.3

Functional Block Diagram .....................................................................................

12

 

1.4

Industry Standard(s) Compliance Statement ...............................................................

13

2

EMAC Functional Architecture ....................................................................................

14

 

2.1

Clock Control ....................................................................................................

14

 

2.2

Memory Map ....................................................................................................

15

 

2.3

System Level Connections ....................................................................................

16

 

2.4

Ethernet Protocol Overview ...................................................................................

24

 

2.5

Programming Interface.........................................................................................

26

 

2.6

EMAC Control Module .........................................................................................

37

 

2.7

Management Data Input/Output (MDIO) Module ...........................................................

38

 

2.8

EMAC Module...................................................................................................

43

 

2.9

Media Independent Interfaces ................................................................................

46

 

2.10

Packet Receive Operation.....................................................................................

50

 

2.11

Packet Transmit Operation ....................................................................................

55

 

2.12

Receive and Transmit Latency ...............................................................................

55

 

2.13

Transfer Node Priority..........................................................................................

56

 

2.14

Reset Considerations ..........................................................................................

56

 

2.15

Initialization ......................................................................................................

57

 

2.16

Interrupt Support................................................................................................

60

 

2.17

Power Management ............................................................................................

63

 

2.18

Emulation Considerations .....................................................................................

63

3

EMAC Control Module Registers .................................................................................

64

 

3.1

Introduction ......................................................................................................

64

 

3.2

EMAC Control Module Interrupt Control Register (EWCTL) ..............................................

64

 

3.3

EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) .................................

65

4

MDIO Registers .........................................................................................................

66

 

4.1

Introduction ......................................................................................................

66

 

4.2

MDIO Version Register (VERSION) .........................................................................

67

 

4.3

MDIO Control Register (CONTROL) .........................................................................

68

 

4.4

PHY Acknowledge Status Register (ALIVE) ................................................................

69

 

4.5

PHY Link Status Register (LINK) .............................................................................

70

 

4.6

MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ............................

71

 

4.7

MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ..........................

72

 

4.8

MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ...................

73

 

4.9

MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) .................

74

 

4.10

MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)................

75

 

4.11

MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)..........

76

 

4.12

MDIO User Access Register 0 (USERACCESS0) .........................................................

77

 

4.13

MDIO User PHY Select Register 0 (USERPHYSEL0) ....................................................

78

 

4.14

MDIO User Access Register 1 (USERACCESS1) .........................................................

79

SPRU975B –August2006

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4.15

MDIO User PHY Select Register 1 (USERPHYSEL1) ....................................................

80

 

5

EMAC Port Registers .................................................................................................

81

 

 

5.1

Introduction ......................................................................................................

81

 

 

5.2

Transmit Identification and Version Register (TXIDVER) .................................................

85

 

 

5.3

Transmit Control Register (TXCONTROL) ..................................................................

86

 

 

5.4

Transmit Teardown Register (TXTEARDOWN) ............................................................

87

 

 

5.5

Receive Identification and Version Register (RXIDVER)..................................................

88

 

 

5.6

Receive Control Register (RXCONTROL) ..................................................................

89

 

 

5.7

Receive Teardown Register (RXTEARDOWN).............................................................

90

 

 

5.8

Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ....................................

91

 

 

5.9

Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)...................................

92

 

 

5.10

Transmit Interrupt Mask Set Register (TXINTMASKSET) ................................................

93

 

 

5.11

Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ..........................................

94

 

 

5.12

MAC Input Vector Register (MACINVECTOR) .............................................................

95

 

 

5.13

Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW).....................................

96

 

 

5.14

Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ...................................

97

 

 

5.15

Receive Interrupt Mask Set Register (RXINTMASKSET) .................................................

98

 

 

5.16

Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)...........................................

99

 

 

5.17

MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW).....................................

100

 

 

5.18

MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ...................................

101

 

 

5.19

MAC Interrupt Mask Set Register (MACINTMASKSET) .................................................

102

 

 

5.20

MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)...........................................

103

 

 

5.21

Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ..........

104

 

 

5.22

Receive Unicast Enable Set Register (RXUNICASTSET)...............................................

106

 

 

5.23

Receive Unicast Clear Register (RXUNICASTCLEAR)..................................................

107

 

 

5.24

Receive Maximum Length Register (RXMAXLEN) .......................................................

108

 

 

5.25

Receive Buffer Offset Register (RXBUFFEROFFSET) ..................................................

109

 

 

5.26

Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) ..................

110

 

 

5.27

Receive Channel 0-7Flow Control Threshold Register (RXnFLOWTHRESH).......................

111

 

 

5.28

Receive Channel 0-7Free Buffer Count Register (RXnFREEBUFFER)..............................

112

 

 

5.29

MAC Control Register (MACCONTROL) ..................................................................

113

 

 

5.30

MAC Status Register (MACSTATUS) ......................................................................

115

 

 

5.31

Emulation Control Register (EMCONTROL) ..............................................................

117

 

 

5.32

FIFO Control Register (FIFOCONTROL) ..................................................................

118

 

 

5.33

MAC Configuration Register (MACCONFIG)..............................................................

119

 

 

5.34

Soft Reset Register (SOFTRESET) ........................................................................

120

 

 

5.35

MAC Source Address Low Bytes Register (MACSRCADDRLO) .......................................

121

 

 

5.36

MAC Source Address High Bytes Register (MACSRCADDRHI) .......................................

122

 

 

5.37

MAC Hash Address Register 1 (MACHASH1) ............................................................

123

 

 

5.38

MAC Hash Address Register 2 (MACHASH2) ............................................................

124

 

 

5.39

Back Off Test Register (BOFFTEST).......................................................................

125

 

 

5.40

Transmit Pacing Algorithm Test Register (TPACETEST) ...............................................

126

 

 

5.41

Receive Pause Timer Register (RXPAUSE) ..............................................................

127

 

 

5.42

Transmit Pause Timer Register (TXPAUSE) ..............................................................

128

 

 

5.43

MAC Address Low Bytes Register (MACADDRLO) ......................................................

129

 

 

5.44

MAC Address High Bytes Register (MACADDRHI) ......................................................

130

 

 

5.45

MAC Index Register (MACINDEX) .........................................................................

131

 

 

5.46

Transmit Channel 0-7DMA Head Descriptor Pointer Register (TXnHDP)............................

132

 

 

5.47

Receive Channel 0-7DMA Head Descriptor Pointer Register (RXnHDP)............................

133

4

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5.48

Transmit Channel 0-7Completion Pointer Register (TXnCP)...........................................

134

5.49

Receive Channel 0-7Completion Pointer Register (RXnCP)...........................................

135

5.50

Network Statistics Registers .................................................................................

136

Appendix A

Glossary ......................................................................................................

145

Appendix B

Revision History ............................................................................................

147

SPRU975B –August2006

Contents

5

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List of Figures

 

1

EMAC and MDIO Block Diagram ........................................................................................

 

12

 

2

Ethernet Configuration with MII Interface ...............................................................................

 

16

 

3

Ethernet Configuration with RMII Interface .............................................................................

 

18

 

4

Ethernet Configuration with GMII Interface .............................................................................

 

20

 

5

Ethernet Configuration with RGMII Interface ...........................................................................

 

22

 

6

Ethernet Frame .............................................................................................................

 

24

 

7

Basic Descriptor Format...................................................................................................

 

26

 

8

Typical Descriptor Linked List ............................................................................................

 

27

 

9

Transmit Descriptor Format ...............................................................................................

 

30

 

10

Receive Descriptor Format................................................................................................

 

33

 

11

EMAC Control Module Block Diagram ..................................................................................

 

37

 

12

MDIO Module Block Diagram.............................................................................................

 

39

 

13

EMAC Module Block Diagram ............................................................................................

 

43

 

14

EMAC Control Module Interrupt Control Register (EWCTL)..........................................................

 

64

 

15

EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) .............................................

 

65

 

16

MDIO Version Register (VERSION) .....................................................................................

 

67

 

17

MDIO Control Register (CONTROL).....................................................................................

 

68

 

18

PHY Acknowledge Status Register (ALIVE)............................................................................

 

69

 

19

PHY Link Status Register (LINK).........................................................................................

 

70

 

20

MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)........................................

 

71

 

21

MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ......................................

 

72

 

22

MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)...............................

 

73

 

23

MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) .............................

 

74

 

24

MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ...........................

 

75

 

25

MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) .....................

76

 

26

MDIO User Access Register 0 (USERACCESS0) .....................................................................

 

77

 

27

MDIO User PHY Select Register 0 (USERPHYSEL0) ................................................................

 

78

 

28

MDIO User Access Register 1 (USERACCESS1) .....................................................................

 

79

 

29

MDIO User PHY Select Register 1 (USERPHYSEL1) ................................................................

 

80

 

30

Transmit Identification and Version Register (TXIDVER) .............................................................

 

85

 

31

Transmit Control Register (TXCONTROL)..............................................................................

 

86

 

32

Transmit Teardown Register (TXTEARDOWN) ........................................................................

 

87

 

33

Receive Identification and Version Register (RXIDVER) .............................................................

 

88

 

34

Receive Control Register (RXCONTROL) ..............................................................................

 

89

 

35

Receive Teardown Register (RXTEARDOWN) ........................................................................

 

90

 

36

Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ................................................

 

91

 

37

Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ..............................................

 

92

 

38

Transmit Interrupt Mask Set Register (TXINTMASKSET) ............................................................

 

93

 

39

Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ......................................................

 

94

 

40

MAC Input Vector Register (MACINVECTOR) .........................................................................

 

95

 

41

Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ................................................

 

96

 

42

Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ...............................................

 

97

 

43

Receive Interrupt Mask Set Register (RXINTMASKSET).............................................................

 

98

 

44

Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ......................................................

 

99

 

45

MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ................................................

 

100

 

46

MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ...............................................

 

101

 

47

MAC Interrupt Mask Set Register (MACINTMASKSET).............................................................

 

102

 

48

MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ......................................................

 

103

 

49

Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ......................

 

104

 

50

Receive Unicast Enable Set Register (RXUNICASTSET) ..........................................................

 

106

 

51

Receive Unicast Clear Register (RXUNICASTCLEAR) .............................................................

 

107

 

52

Receive Maximum Length Register (RXMAXLEN)...................................................................

 

108

6

List of Figures

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53

Receive Buffer Offset Register (RXBUFFEROFFSET) ..............................................................

109

54

Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)..............................

110

55

Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH).....................................

111

56

Receive Channel n Free Buffer Count Register (RXnFREEBUFFER)............................................

112

57

MAC Control Register (MACCONTROL) ..............................................................................

113

58

MAC Status Register (MACSTATUS)..................................................................................

115

59

Emulation Control Register (EMCONTROL) ..........................................................................

117

60

FIFO Control Register (FIFOCONTROL) ..............................................................................

118

61

MAC Configuration Register (MACCONFIG) .........................................................................

119

62

Soft Reset Register (SOFTRESET) ....................................................................................

120

63

MAC Source Address Low Bytes Register (MACSRCADDRLO)...................................................

121

64

MAC Source Address High Bytes Register (MACSRCADDRHI) ...................................................

122

65

MAC Hash Address Register 1 (MACHASH1)........................................................................

123

66

MAC Hash Address Register 2 (MACHASH2)........................................................................

124

67

Back Off Random Number Generator Test Register (BOFFTEST) ................................................

125

68

Transmit Pacing Algorithm Test Register (TPACETEST) ...........................................................

126

69

Receive Pause Timer Register (RXPAUSE) ..........................................................................

127

70

Transmit Pause Timer Register (TXPAUSE)..........................................................................

128

71

MAC Address Low Bytes Register (MACADDRLO)..................................................................

129

72

MAC Address High Bytes Register (MACADDRHI) ..................................................................

130

73

MAC Index Register (MACINDEX) .....................................................................................

131

74

Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP)..........................................

132

75

Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP)..........................................

133

76

Transmit Channel n Completion Pointer Register (TXnCP).........................................................

134

77

Receive Channel n Completion Pointer Register (RXnCP) .........................................................

135

78

Statistics Register.........................................................................................................

136

SPRU975B –August2006

List of Figures

7

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List of Tables

 

1

Interface Selection Pins ...................................................................................................

 

16

 

2

EMAC and MDIO Signals for MII Interface .............................................................................

 

17

 

3

EMAC and MDIO Signals for RMII Interface ...........................................................................

 

19

 

4

EMAC and MDIO Signals for GMII Interface ...........................................................................

 

21

 

5

EMAC and MDIO Signals for RGMII Interface .........................................................................

 

23

 

6

Ethernet Frame Description...............................................................................................

 

24

 

7

Basic Descriptors...........................................................................................................

 

26

 

8

Receive Frame Treatment Summary ....................................................................................

 

53

 

9

Middle of Frame Overrun Treatment ....................................................................................

 

54

 

10

Emulation Control ..........................................................................................................

 

63

 

11

EMAC Control Module Registers.........................................................................................

 

64

 

12

EMAC Control Module Interrupt Control Register (EWCTL) Field Descriptions ...................................

 

64

 

13

EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) Field Descriptions.......................

 

65

 

14

Management Data Input/Output (MDIO) Registers ....................................................................

 

66

 

15

MDIO Version Register (VERSION) Field Descriptions ...............................................................

 

67

 

16

MDIO Control Register (CONTROL) Field Descriptions ..............................................................

 

68

 

17

PHY Acknowledge Status Register (ALIVE) Field Descriptions .....................................................

 

69

 

18

PHY Link Status Register (LINK) Field Descriptions ..................................................................

 

70

 

19

MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions .................

71

 

20

MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions ................

72

 

21

MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions ........

73

 

22

MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions.......

74

 

23

MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions .....

75

 

24

MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field

 

 

 

Descriptions .................................................................................................................

 

76

 

25

MDIO User Access Register 0 (USERACCESS0) Field Descriptions...............................................

 

77

 

26

MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions ..........................................

 

78

 

27

MDIO User Access Register 1 (USERACCESS1) Field Descriptions...............................................

 

79

 

28

MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions ..........................................

 

80

 

29

Ethernet Media Access Controller (EMAC) Registers .................................................................

 

81

 

30

Transmit Identification and Version Register (TXIDVER) Field Descriptions.......................................

 

85

 

31

Transmit Control Register (TXCONTROL) Field Descriptions .......................................................

 

86

 

32

Transmit Teardown Register (TXTEARDOWN) Field Descriptions..................................................

 

87

 

33

Receive Identification and Version Register (RXIDVER) Field Descriptions .......................................

 

88

 

34

Receive Control Register (RXCONTROL) Field Descriptions ........................................................

 

89

 

35

Receive Teardown Register (RXTEARDOWN) Field Descriptions ..................................................

 

90

 

36

Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions..........................

 

91

 

37

Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions ........................

 

92

 

38

Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ......................................

 

93

 

39

Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions................................

 

94

 

40

MAC Input Vector Register (MACINVECTOR) Field Descriptions...................................................

 

95

 

41

Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions ..........................

 

96

 

42

Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions.........................

 

97

 

43

Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ......................................

 

98

 

44

Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ................................

 

99

 

45

MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions ..........................

 

100

 

46

MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions.........................

 

101

 

47

MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ......................................

 

102

 

48

MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ................................

 

103

 

49

Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions

104

8

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50

Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions ....................................

106

51

Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions .......................................

107

52

Receive Maximum Length Register (RXMAXLEN) Field Descriptions ............................................

108

53

Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions........................................

109

54

Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions .......

110

55

Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions...............

111

56

Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions......................

112

57

MAC Control Register (MACCONTROL) Field Descriptions ........................................................

113

58

MAC Status Register (MACSTATUS) Field Descriptions ...........................................................

115

59

Emulation Control Register (EMCONTROL) Field Descriptions....................................................

117

60

FIFO Control Register (FIFOCONTROL) Field Descriptions........................................................

118

61

MAC Configuration Register (MACCONFIG) Field Descriptions ...................................................

119

62

Soft Reset Register (SOFTRESET) Field Descriptions..............................................................

120

63

MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ............................

121

64

MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions.............................

122

65

MAC Hash Address Register 1 (MACHASH1) Field Descriptions .................................................

123

66

MAC Hash Address Register 2 (MACHASH2) Field Descriptions .................................................

124

67

Back Off Test Register (BOFFTEST) Field Descriptions ............................................................

125

68

Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions .....................................

126

69

Receive Pause Timer Register (RXPAUSE) Field Descriptions....................................................

127

70

Transmit Pause Timer Register (TXPAUSE) Field Descriptions ...................................................

128

71

MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ...........................................

129

72

MAC Address High Bytes Register (MACADDRHI) Field Descriptions............................................

130

73

MAC Index Register (MACINDEX) Field Descriptions ...............................................................

131

74

Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions....................

132

75

Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions....................

133

76

Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions..................................

134

77

Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions...................................

135

78

Statistics Register Field Descriptions ..................................................................................

136

A-1

Physical Layer Definitions ...............................................................................................

146

B-1

Document Revision History..............................................................................................

147

SPRU975B –August2006

List of Tables

9

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