Texas Instruments TLV1562 User Manual

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Interfacing the TLV1562 Parallel AD Converter to the TMS320C54x DSP

Application

Report

July 1999

Advanced Analog Products

SLAA040

IMPORTANT NOTICE

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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORTDEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 1999, Texas Instruments Incorporated

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 The Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 TMS320C54x Starter Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 TLV1562EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 ADC TLV1562 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3.1 Suggestions for the ’C54x to TLV1562 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3.2 Recyclic Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.3.3 Note on the Interface, Using an External ADC Clock Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.4 Onboard Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4.1 TLC5618 – Serial DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4.2 TLV5651 – Parallel DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1 Reference Voltage Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Input Data Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 Connections Between the DSP and the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3.1 Jumpers Used on the TLV1562EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 The Serial DAC/DSP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 The DSP Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6 Other DSP/TLV1562 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.1 DSP Internal Serial Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7 Conversation Between the TLV1562 and the DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12

7.1

Writing to the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12

7.2

Mono Interrupt Driven Mode Using

RD

. . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12

7.3

Mono Interrupt Driven Mode Using

CSTART

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14

7.4

Dual Interrupt Driven Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15

7.5

Mono Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16

7.6

Dual Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17

8 Software Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18

8.1

Software Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18

8.2

DSP Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18

8.3

Programming Strategies for the ’C54x, Explanations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20

 

8.3.1 Optimizing CPU Resources for Maximum Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20

 

8.3.2 Address and Data Bus for I/O Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20

 

8.3.3

Timer Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20

 

8.3.4

Data Page Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21

 

8.3.5 Generating the Chip Select Signal and the

CSTART

. . . . . . . . . . . . . . . . . . . . . . . . . . . .Signal

21

 

8.3.6 Interfacing the Serial DAC 5618 to the DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21

 

8.3.7

Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22

 

8.3.8 Branch Optimization (goto/dgoto, call/dcall, ...) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22

 

8.3.9 Enabling Software Modules (.if/.elseif/.endif) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23

8.4

Software Code Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23

 

8.4.1 Software Principals of the Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23

8.5

Flow Charts and Comments for All Software Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27

 

8.5.1 The Mono Interrupt Driven Mode Using

RD

. . . . . . . . . . . . . . . . . . . . . . . .to Start Conversion

27

 

8.5.2 Mono Interrupt Driven Mode Using

CSTART

. . . . . . . . . . . . . . . . . . . . . . .to Start Conversion

30

 

8.5.3 Dual Interrupt Driven Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

33

 

8.5.4

Mono Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

36

Interfacing the TLV1562 Parallel AD-Converterto the TMS320C54x DSP

iii

Contents

 

8.5.5

Dual Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

38

 

8.5.6 C-CallableWith Mono Interrupt Driven Mode Using

CSTART

. . . . . . . . .to Start Conversion

40

 

8.6 Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

41

 

8.6.1 Common Software for all Modes (except C-Callable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

41

 

8.6.2 Mono Mode Interrupt Driven Software Using

RD

. . . . . . . . . . . . . . . . . . . .to Start Conversion

46

 

8.6.3 Calibration of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

53

 

8.6.4 Mono Mode Interrupt Driven Software Using

CSTART

. . . . . . . . . . . . . . .to Start Conversion

58

 

8.6.5 Dual Interrupt Driven Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

66

 

8.6.6

Mono Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

74

 

8.6.7

Dual Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

80

 

8.6.8

C-Callable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

86

9

Summary . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

. . .

. . .

. .

. . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . .

93

10

References . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

. . .

. . .

. .

. . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . .

93

iv

SLAA040

Figures

List of Figures

1 TLV1562 – DSP Interface of the EVM, Using RD or the CSTART Signal to Start Conversion . . . . . . . . . . . . . . . 2 2 TLV1562 – DSP Interface of the EVM, Using RD or the CSTART Signal to Start Conversion . . . . . . . . . . . . . . . 3 3 TLC5618 – DSP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 TLC5651 – DSP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Software Flow of the Mono Interrupt Driven Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 Flow Chart Mono Interrupt Driven Mode Using CSTART to Start Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Time Optimization (monocst1) Maximum Performance at 12 MSPS with Internal Clock . . . . . . . . . . . . . . . . . . . 33 9 Flow Chart Dual Interrupt Driven Mode (Using CSTART) to Start Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 Flow Chart Mono Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 Flow Chart Dual Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

List of Tables

1 Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 3-PositionJumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 32-PositionJumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 DSP/DAC Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 DSP Serial Port Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 DSP Algorithm for Writing to the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 DSP Algorithm for Mono Interrupt Driven Mode Using RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 DSP Algorithm for Mono Interrupt Driven Mode Using CSTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 DSP Algorithm for Dual Interrupt Driven Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10 DSP Algorithm for Mono Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 11 DSP Algorithm for Dual Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 12 Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13 Instruction in the Program Header (Step 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14 Instruction in the Program Header (Step 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Interfacing the TLV1562 Parallel AD-Converterto the TMS320C54x DSP

v

vi

SLAA040

Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP

Falk Alicke and Perry Miller

ABSTRACT

In this application report we discuss the hardware and software interface of the TLV1562, 10-bitparallel-outputanalog-to-digitalconverter (ADC) to the TMS320C54x digital signal processor (DSP).The hardware interface board, or evaluation module (EVM) consists of the TLV1562 10-bit ADC, a THS5651 10-bit parallel output communication digital-to-analog converter (CommsDAC ) and a TLC5618A serial-output digital-to-analog converter (DAC).

Following the discussion of the ADC we explain the need for both the THS5651 CommsDAC and the TLC5618A serial DAC.

The application report concludes with several software application examples and recommendations for simplifying the software through modifications of the DSP hardware interface circuit.

1 Introduction

The analog-to-digital(A/D) interface can present a significant design problem because hardware and software must work together across the interface to produce a usable, complete design. This application report provides a design solution for the interface between the TLV156210-bitparallel-outputanalog-to-digitalconverter (ADC) and the TMS320C54x digital signal processor (DSP).

The report describes the hardware and software needed to interface the ’C54x DSP to the TLV1562 ADC, which is intended for applications, such as industrial control and signal intelligence in which large amounts of data must be processed quickly. The first sections describe the basic operation of the TLV1562. For additional information see the References section at the end of this report.

2 The Board

The TLV1562 evaluation module (EVM) is a four-layerprinted circuit board (PCB) constructed from FR4 material. The PCB dimensions are 180 mm × 112 mm × 12 mm. Ribbon cables are used to interface the TLV1562EVM to the TMS320C54x DSK plus starter kit.

2.1TMS320C54x Starter Kit

The starter kit simplifies the task of interfacing to the ’C54x processor. It comes with an ADC for voice bandwidth, and GoDSP code explorer as the software tool. A 10-MHzoscillator provides the clock signal to allow40-MHzinternal DSP clock cycles generated by the internal DSP PLL. Therefore, the board provides 40 MIPS of processing power.

Ribbon cables are used to connect the DSP with the EVM. Detailed descriptions of all connections are given later in this report.

CommsDAC is a trademark of Texas Instruments.

1

The Board

2.2TLV1562EVM

The TLV1562EVM gives customers an easy start with employing many of the features of this converter. A serial DAC (TLC5618A), a parallel DAC (THS5651), and the ADC (TLV1562) make this EVM flexible enough to test the features of the TLV1562. It also helps show how this ADC can be implemented.

2.3ADC TLV1562 Overview

The TLV1562 is a CMOS 10-bithigh-speedprogrammable resolutionanalog-to-digital converter, using alow-powerrecyclic architecture.

The converter provides two differential or four single-endedinputs to interface the analog input signals.

On the digital side, the device has a chip-select(CS), input clock (CLKIN), sample/conversion start signal (CSTART), read signal input (RD), write signal input (WR), and 10 parallel data I/O lines (D9:0).

The converter integrates the CSTART signal to coordinate sampling and conversion timing without using the parallel bus. Since the TMS320C542 DSP has no second general-purposeoutput, this signal is generated with the signal (CSTART) from the address decoder.

2.3.1Suggestions for the ’C54x to TLV1562 Interface

The following paragraphs describe two suggested interfaces between the ’C54x and the TLV1562.

2.3.1.1The Universal Interface

The schematic in Figure 1 shows the pin-to-pinconnections between the TLV1562 and ’C54x, realized on the EVM. This routing can test the converter in each mode. OneI/O-waitstate is required for write operations to the ADC.The read sequence from the ADC does not require any wait states because the RD signal is generated with XF.

TLV1562

TMS320C54x

INT

 

 

INT

CSTART

01

Address

A0

CS

10

Decoder

A1

 

11

 

 

 

 

RD

 

 

XF

WR

 

1

IOSTRB

 

 

R/W

 

 

 

 

 

1: x

 

CLKIN

 

Divider

CLOCKOUT

D(0–9)

 

 

D(0–9)

Figure 1. TLV1562 to ’C54x DSP Interface of the EVM,

Using RD or the CSTART Signal to Start Conversion

2

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The Board

2.3.1.2Simplification of Software Requirements Through Modified Interface

Of all the TLV1562 modes of operation, only the mono interrupt driven mode uses the RD signal to start the conversion. This requires a very flexible handling of the read signal and therefore has to be performed by ageneral-purposeoutput signal. If the application excludes using the RD signal to start the conversion (using CSTART instead). The TLV1562 RD input signal can be generated with an OR gate, whose inputs are driven by IOSTRB and R/W signals from the DSP (see Figure 2).

Using these connections saves the programming steps of setting/resetting RD with the XF signal. Another advantage is having XF available to control the CSTART signal. This saves busy times on the address bus (in Figure 1, CSTART was generated through A0/A1.) and simplifies the software code.

CAUTION:

The time tEN(DATAOUT) between the RDhigh-to-lowtransition (generated by the DSP) and the arrival of valid ADC output

data on the data bus is related to the capacitive load of the bus. In most cases, the ADC come out of the 3-statemode and supplies the correct voltage levels onto the bus lines in less than 50 ns. Thus, the minimum number ofI/O-waitstates becomes two (for tEN(DATAOUT) 50 ns).

TLV1562

INT

CSTART

CS

 

RD

 

WR

&

 

CLKIN

 

 

 

TMS320C54x

 

 

INT

 

 

XF

01

Address

A0

10

Decoder

A1

11

 

 

 

 

1

IOSTRB

 

R/W

 

 

1

1: x

 

Divider

CLOCKOUT

D(0–9)D(0–9)

Figure 2. TLV1562 to ’C54x DSP Interface of the EVM,

Using RD or the CSTART Signal to Start Conversion

2.3.2Recyclic Architecture

One specialty of this ADC is its recyclic architecture. Instead of limiting the device power by the highest possible resolution at the fastest speed, this converter is able to work at three maximum speeds for three resolutions. The highest resolution runs at 2MSPS maximum throughput rate; 8-bitresolution corresponds to 3MSPS, and4-bitresolution to 7MSPS.

Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP

3

The Board

This feature fits well into monitoring application. For example, the ADC may have to trigger on one event out of some channels inside an extremely small time window and then sample the correct channel with a higher resolution, but lower throughput to analyze this process. This feature also fits well into home security applications or applications that must monitor several inputs simultaneously.

2.3.3Note on the Interface, Using an External ADC Clock Drive

The TLV1562data sheet (Figure 9) shows that RD has to fall as close as possible to the falling edge of the clock signal. The user must adhere to this timing, otherwise the conversion result may be wrong. The user may not recognize the erroneous result, since the ADC will signal that the conversion has finished during the logic low transition of the INT signal. The following timing diagram shows the interface behavior of the ADC whether the timing is correct or not. The following figure shows what happens when the RD falling edge is timed wrong. Although RD falls nearly 1/2 of one cycle too late, the conversion result is valid on the 5th clock cycle.

1

2

3

4

5

6

7

8

9

10

1

 

 

 

 

 

 

 

 

 

 

 

 

CLK

RD

INT

 

 

 

 

 

Conversion Starts

Next Sampling Starts

Conversion Finished

2.4Onboard Components

These sections describe the EVM onboard components.

2.4.1TLC5618A – Serial DAC

This 12-bitDAC has a serial interface that can run at20-MHzclock; therefore, it can update the output at 1.21 MSPS. Two outputs are available on the8-pinpackage. The buffered SPI of the DSP provides the DSP interface. Using theauto-buffermode, updating the data on the DAC requires only four CPU instructions/samples.

4

SLAA040