Texas Instruments SPRU938B User Manual
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TMS320DM643x DMP

VLYNQ Port

User's Guide

Literature Number: SPRU938B

September 2007

2

SPRU938B –September2007

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Contents

Preface ...............................................................................................................................

 

 

7

1

Introduction................................................................................................................

 

8

 

1.1

Purpose of the Peripheral .......................................................................................

 

8

 

1.2

Features ...........................................................................................................

 

8

 

1.3

Functional Block Diagram.......................................................................................

 

9

 

1.4

Industry Standard(s) Compliance Statement .................................................................

 

9

2

Peripheral Architecture ..............................................................................................

 

10

 

2.1

Clock Control ....................................................................................................

 

10

 

2.2

Signal Descriptions .............................................................................................

 

11

 

2.3

Pin Multiplexing .................................................................................................

 

11

 

2.4

Protocol Description ............................................................................................

 

11

 

2.5

VLYNQ Functional Description ...............................................................................

 

12

 

2.6

Initialization ......................................................................................................

 

15

 

2.7

Auto-Negotiation ................................................................................................

 

15

 

2.8

Address Translation ............................................................................................

 

16

 

2.9

Flow Control .....................................................................................................

 

19

 

2.10

Reset Considerations ..........................................................................................

 

20

 

2.11

Interrupt Support................................................................................................

 

20

 

2.12

EDMA Event Support ..........................................................................................

 

22

 

2.13

Power Management ............................................................................................

 

23

 

2.14

Endianness Considerations ...................................................................................

 

23

 

2.15

Emulation Considerations .....................................................................................

 

23

3

VLYNQ Port Registers................................................................................................

 

24

 

3.1

Revision Register (REVID) ....................................................................................

 

25

 

3.2

Control Register (CTRL) .......................................................................................

 

26

 

3.3

Status Register (STAT) ........................................................................................

 

28

 

3.4

Interrupt Priority Vector Status/Clear Register (INTPRI) ..................................................

 

30

 

3.5

Interrupt Status/Clear Register (INTSTATCLR) ............................................................

 

30

 

3.6

Interrupt Pending/Set Register (INTPENDSET) ............................................................

 

31

 

3.7

Interrupt Pointer Register (INTPTR) .........................................................................

 

31

 

3.8

Transmit Address Map Register (XAM)......................................................................

 

32

 

3.9

Receive Address Map Size 1 Register (RAMS1) ..........................................................

 

33

 

3.10

Receive Address Map Offset 1 Register (RAMO1) ........................................................

 

33

 

3.11

Receive Address Map Size 2 Register (RAMS2) ..........................................................

 

34

 

3.12

Receive Address Map Offset 2 Register (RAMO2) ........................................................

 

34

 

3.13

Receive Address Map Size 3 Register (RAMS3) ..........................................................

 

35

 

3.14

Receive Address Map Offset 3 Register (RAMO3) ........................................................

 

35

 

3.15

Receive Address Map Size 4 Register (RAMS4) ..........................................................

 

36

 

3.16

Receive Address Map Offset 4 Register (RAMO4) ........................................................

 

36

 

3.17

Chip Version Register (CHIPVER) ...........................................................................

 

37

 

3.18

Auto Negotiation Register (AUTNGO) .......................................................................

 

37

4

Remote Configuration Registers .................................................................................

 

38

Appendix A

VLYNQ Protocol Specifications ........................................................................

 

39

 

A.1

Introduction ......................................................................................................

 

39

SPRU938B –September2007

Table of Contents

3

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A.2

Special 8b/10b Code Groups .................................................................................

39

A.3

Supported Ordered Sets.......................................................................................

39

A.4

VLYNQ 2.0 Packet Format ....................................................................................

40

A.5

VLYNQ 2.X Packets............................................................................................

42

Appendix B

Write/Read Performance ..................................................................................

44

B.1

Introduction ......................................................................................................

44

B.2

Write Performance..............................................................................................

44

B.3

Read Performance .............................................................................................

46

Appendix C

Revision History .............................................................................................

47

4

Contents

SPRU938B –September2007

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List of Figures

 

1

VLYNQ Port Functional Block Diagram...................................................................................

9

2

External Clock Block Diagram ............................................................................................

10

3

Internal Clock Block Diagram .............................................................................................

10

4

VLYNQ Module Structure .................................................................................................

12

5

Write Operations ...........................................................................................................

13

6

Read Operations ...........................................................................................................

14

7

Example Address Memory Map ..........................................................................................

17

8

Interrupt Generation Mechanism Block Diagram.......................................................................

21

9

Revision Register (REVID)................................................................................................

25

10

Control Register (CTRL)...................................................................................................

26

11

Status Register (STAT)....................................................................................................

28

12

Interrupt Priority Vector Status/Clear Register (INTPRI) ..............................................................

30

13

Interrupt Status/Clear Register (INTSTATCLR) ........................................................................

30

14

Interrupt Pending/Set Register (INTPENDSET)........................................................................

31

15

Interrupt Pointer Register (INTPTR) .....................................................................................

31

16

Transmit Address Map Register (XAM) .................................................................................

32

17

Receive Address Map Size 1 Register (RAMS1) ......................................................................

33

18

Receive Address Map Offset 1 Register (RAMO1) ....................................................................

33

19

Receive Address Map Size 2 Register (RAMS2) ......................................................................

34

20

Receive Address Map Offset 2 Register (RAMO2) ....................................................................

34

21

Receive Address Map Size 3 Register (RAMS3) ......................................................................

35

22

Receive Address Map Offset 3 Register (RAMO3) ....................................................................

35

23

Receive Address Map Size 4 Register (RAMS4) ......................................................................

36

24

Receive Address Map Offset 4 Register (RAMO4) ....................................................................

36

25

Chip Version Register (CHIPVER) .......................................................................................

37

26

Auto Negotiation Register (AUTNGO)...................................................................................

37

A-1

Packet Format (10-bit Symbol Representation) ........................................................................

40

SPRU938B –September2007

List of Figures

5

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List of Tables

 

1

VLYNQ Signal Descriptions...............................................................................................

11

2

Address Translation Example (Single Mapped Region) ..............................................................

17

3

Address Translation Example (Single Mapped Region) ..............................................................

18

4

VLYNQ Register Address Space.........................................................................................

24

5

VLYNQ Port Controller Registers ........................................................................................

24

6

Revision Register (REVID) Field Descriptions .........................................................................

25

7

Control Register (CTRL) Field Descriptions ............................................................................

26

8

Status Register (STAT) Field Descriptions .............................................................................

28

9

Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions........................................

30

10

Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions..................................................

30

11

Interrupt Pending/Set Register (INTPENDSET) Field Descriptions .................................................

31

12

Interrupt Pointer Register (INTPTR) Field Descriptions ...............................................................

31

13

Address Map Register (XAM) Field Descriptions ......................................................................

32

14

Receive Address Map Size 1 Register (RAMS1) Field Descriptions ................................................

33

15

Receive Address Map Offset 1 Register (RAMO1) Field Descriptions..............................................

33

16

Receive Address Map Size 2 Register (RAMS2) Field Descriptions ................................................

34

17

Receive Address Map Offset 2 Register (RAMO2) Field Descriptions..............................................

34

18

Receive Address Map Size 3 Register (RAMS3) Field Descriptions ................................................

35

19

Receive Address Map Offset 3 Register (RAMO3) Field Descriptions..............................................

35

20

Receive Address Map Size 4 Register (RAMS4) Field Descriptions ................................................

36

21

Receive Address Map Offset 4 Register (RAMO4) Field Descriptions..............................................

36

22

Chip Version Register (CHIPVER) Field Descriptions.................................................................

37

23

Auto Negotiation Register (AUTNGO) Field Descriptions ............................................................

37

24

VLYNQ Port Remote Controller Registers ..............................................................................

38

A-1

Special 8b/10b Code Groups .............................................................................................

39

A-2

Supported Ordered Sets ..................................................................................................

39

A-3

Packet Format (10-bit Symbol Representation) Description..........................................................

41

B-1

Scaling Factors .............................................................................................................

45

B-2

Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ) ....................................

45

B-3

Relative Performance with Various Latencies ..........................................................................

46

C-1

Document Revision History ...............................................................................................

47

6

List of Tables

SPRU938B –September2007

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