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SM320C6455-EP

FIXED-POINTDIGITAL SIGNAL PROCESSOR

Data Manual

JANUARY 2008

SPRS462B

SM320C6455-EP

FIXED-POINTDIGITAL SIGNAL PROCESSOR

Data Manual

Literature Number: SPRS462B

SEPTEMBER 2007–RevisedJANUARY 2008

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

 

 

 

SM320C6455-EP

 

 

 

FIXED-POINTDIGITAL SIGNAL PROCESSOR

 

 

 

SPRS462B–SEPTEMBER2007–REVISEDJANUARY 2008

 

 

 

Contents

 

1

Features..............................................................................................................................

 

7

 

1.1

ZTZ/GTZ BGA Package (Bottom View)...................................................................................

8

 

1.2

Description....................................................................................................................

8

 

1.3

Functional Block Diagram .................................................................................................

10

2

Device Overview.................................................................................................................

11

 

2.1

Device Characteristics .....................................................................................................

11

 

2.2

CPU (DSP Core) Description .............................................................................................

12

 

2.3

Memory Map Summary....................................................................................................

15

 

2.4

Boot Sequence .............................................................................................................

17

 

 

2.4.1

Boot Modes Supported .........................................................................................

17

 

 

2.4.2

2nd-Level Bootloaders ..........................................................................................

19

 

2.5

Pin Assignments............................................................................................................

20

 

 

2.5.1

Pin Map ...........................................................................................................

20

 

2.6

Signal Groups Description ................................................................................................

24

 

2.7

Terminal Functions.........................................................................................................

30

 

2.8

Development ................................................................................................................

55

 

 

2.8.1

Development Support...........................................................................................

55

 

 

2.8.2

Device Support ..................................................................................................

55

 

 

 

2.8.2.1 Device and Development-SupportTool Nomenclature........................................

55

 

 

 

2.8.2.2 Documentation Support .............................................................................

56

3

Device Configuration ..........................................................................................................

59

 

3.1

Device Configuration at Device Reset...................................................................................

59

 

3.2

Peripheral Configuration at Device Reset...............................................................................

61

 

3.3

Peripheral Selection After Device Reset ................................................................................

63

 

3.4

Device State Control Registers...........................................................................................

65

 

 

3.4.1 Peripheral Lock Register Description .........................................................................

66

 

 

3.4.2 Peripheral Configuration Register 0 Description ............................................................

67

 

 

3.4.3 Peripheral Configuration Register 1 Description ............................................................

69

 

 

3.4.4 Peripheral Status Registers Description......................................................................

70

 

 

3.4.5 EMAC Configuration Register (EMACCFG) Description ...................................................

73

 

 

3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description ........................................

74

 

3.5

Device Status Register Description ......................................................................................

75

 

3.6

JTAG ID (JTAGID) Register Description ................................................................................

77

 

3.7

Pullup/Pulldown Resistors.................................................................................................

78

 

3.8

Configuration Examples ...................................................................................................

78

4

System Interconnect...........................................................................................................

81

 

4.1

Internal Buses, Bridges, and Switch Fabrics ...........................................................................

81

 

4.2

Data Switch Fabric Connections .........................................................................................

82

 

4.3

Configuration Switch Fabric...............................................................................................

84

 

4.4

Bus Priorities................................................................................................................

86

5

C64x+ Megamodule ............................................................................................................

87

 

5.1

Memory Architecture.......................................................................................................

87

 

5.2

Memory Protection .........................................................................................................

90

 

5.3

Bandwidth Management...................................................................................................

90

 

5.4

Power-Down Control.......................................................................................................

91

 

5.5

Megamodule Resets .......................................................................................................

91

 

5.6

Megamodule Revision .....................................................................................................

92

 

5.7

C64x+ Megamodule Register Description(s) ...........................................................................

93

6

Device Operating Conditions .............................................................................................

101

 

6.1

Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) ..........

101

Contents 3

SM320C6455-EP

FIXED-POINTDIGITAL SIGNAL PROCESSOR

SPRS462B–SEPTEMBER2007–REVISEDJANUARY 2008

6.2

Recommended Operating Conditions..................................................................................

101

6.3Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case

Temperature (Unless Otherwise Noted) ...............................................................................

103

7

C64x+ Peripheral Information and Electrical Specifications ...................................................

105

 

7.1

Parameter Information ...................................................................................................

105

 

 

7.1.1

3.3-V Signal Transition Levels ...............................................................................

105

 

 

7.1.2

3.3-V Signal Transition Rates ................................................................................

105

 

 

7.1.3

Timing Parameters and Board Routing Analysis ..........................................................

106

 

7.2

Recommended Clock and Control Signal Transition Behavior .....................................................

107

 

7.3

Power Supplies ...........................................................................................................

 

107

 

 

7.3.1

Power-Supply Sequencing....................................................................................

107

 

 

7.3.2

Power-Supply Decoupling ....................................................................................

107

 

 

7.3.3

Power-Down Operation .......................................................................................

107

 

 

7.3.4

Preserving Boundary-ScanFunctionality on RGMII and DDR2 Memory Pins.........................

108

 

7.4

Enhanced Direct Memory Access (EDMA3) Controller..............................................................

109

 

 

7.4.1

EDMA3 Device-Specific Information ........................................................................

110

 

 

7.4.2

EDMA3 Channel Synchronization Events ..................................................................

110

 

 

7.4.3

EDMA3 Peripheral Register Description(s).................................................................

111

 

7.5

Interrupts ...................................................................................................................

 

124

 

 

7.5.1

Interrupt Sources and Interrupt Controller ..................................................................

124

 

 

7.5.2

External Interrupts Electrical Data/Timing ..................................................................

127

 

7.6

Reset Controller...........................................................................................................

 

128

 

 

7.6.1

Power-on Reset (POR Pin) ...................................................................................

128

 

 

7.6.2

Warm Reset (RESET Pin) ....................................................................................

129

 

 

7.6.3

Max Reset.......................................................................................................

130

 

 

7.6.4

System Reset...................................................................................................

130

 

 

7.6.5

CPU Reset ......................................................................................................

130

 

 

7.6.6

Reset Priority ...................................................................................................

131

 

 

7.6.7

Reset Controller Register .....................................................................................

132

 

 

 

7.6.7.1 Reset Type Status Register Description .........................................................

132

 

 

7.6.8

Reset Electrical Data/Timing .................................................................................

133

 

7.7

PLL1 and PLL1 Controller ...............................................................................................

136

 

 

7.7.1

PLL1 Controller Device-Specific Information ...............................................................

137

 

 

 

7.7.1.1 Internal Clocks and Maximum Operating Frequencies.........................................

137

 

 

 

7.7.1.2 PLL1 Controller Operating Modes ................................................................

138

 

 

 

7.7.1.3 PLL1 Stabilization, Lock, and Reset Times......................................................

138

 

 

7.7.2

PLL1 Controller Memory Map ................................................................................

139

 

 

7.7.3

PLL1 Controller Register Descriptions ......................................................................

140

 

 

 

7.7.3.1

PLL1 Control Register ..............................................................................

140

 

 

 

7.7.3.2 PLL Multiplier Control Register ....................................................................

141

 

 

 

7.7.3.3 PLL Pre-Divider Control Register .................................................................

142

 

 

 

7.7.3.4 PLL Controller Divider 4 Register .................................................................

143

 

 

 

7.7.3.5 PLL Controller Divider 5 Register .................................................................

144

 

 

 

7.7.3.6 PLL Controller Command Register ...............................................................

145

 

 

 

7.7.3.7 PLL Controller Status Register ....................................................................

146

 

 

 

7.7.3.8 PLL Controller Clock Align Control Register.....................................................

147

 

 

 

7.7.3.9 PLLDIV Ratio Change Status Register...........................................................

148

 

 

 

7.7.3.10

SYSCLK Status Register .........................................................................

149

 

 

7.7.4

PLL1 Controller Input and Output Clock Electrical Data/Timing .........................................

150

 

7.8

PLL2 and PLL2 Controller ...............................................................................................

151

 

 

7.8.1

PLL2 Controller Device-Specific Information ...............................................................

152

 

 

 

7.8.1.1 Internal Clocks and Maximum Operating Frequencies.........................................

152

 

 

 

7.8.1.2 PLL2 Controller Operating Modes ................................................................

152

4

Contents

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SM320C6455-EP

 

 

 

FIXED-POINTDIGITAL SIGNAL PROCESSOR

 

 

 

SPRS462B–SEPTEMBER2007–REVISEDJANUARY 2008

 

7.8.2

PLL2 Controller Memory Map ................................................................................

153

 

7.8.3

PLL2 Controller Register Descriptions ......................................................................

153

 

 

7.8.3.1 PLL Controller Divider 1 Register .................................................................

154

 

 

7.8.3.2 PLL Controller Command Register ...............................................................

155

 

 

7.8.3.3 PLL Controller Status Register ....................................................................

156

 

 

7.8.3.4 PLL Controller Clock Align Control Register.....................................................

156

 

 

7.8.3.5 PLLDIV Ratio Change Status Register...........................................................

157

 

 

7.8.3.6

SYSCLK Status Register...........................................................................

158

 

7.8.4

PLL2 Controller Input Clock Electrical Data/Timing .......................................................

159

7.9

DDR2 Memory Controller ................................................................................................

160

 

7.9.1

DDR2 Memory Controller Device-SpecificInformation...................................................

160

 

7.9.2

DDR2 Memory Controller Peripheral Register Description(s)............................................

161

 

7.9.3

DDR2 Memory Controller Electrical Data/Timing ..........................................................

161

7.10 External Memory Interface A (EMIFA) .................................................................................

162

 

7.10.1

EMIFA Device-Specific Information..........................................................................

162

 

7.10.2

EMIFA Peripheral Register Description(s)..................................................................

163

 

7.10.3

EMIFA Electrical Data/Timing ................................................................................

164

 

 

7.10.3.1

Asynchronous Memory Timing..................................................................

165

 

 

7.10.3.2 Programmable Synchronous Interface Timing................................................

168

 

7.10.4

HOLD/HOLDA Timing .........................................................................................

171

 

7.10.5

BUSREQ Timing ...............................................................................................

172

7.11

I2C Peripheral .............................................................................................................

 

173

 

7.11.1

I2C Device-Specific Information..............................................................................

173

 

7.11.2

I2C Peripheral Register Description(s) ......................................................................

175

 

7.11.3

I2C Electrical Data/Timing ....................................................................................

176

 

 

7.11.3.1 Inter-Integrated Circuits (I2C) Timing ..........................................................

176

7.12 Host-Port Interface (HPI) Peripheral ...................................................................................

179

 

7.12.1

HPI Device-Specific Information .............................................................................

179

 

7.12.2

HPI Peripheral Register Description(s)......................................................................

179

 

7.12.3

HPI Electrical Data/Timing ....................................................................................

180

7.13 Multichannel Buffered Serial Port (McBSP) ...........................................................................

190

 

7.13.1

McBSP Device-Specific Information.........................................................................

191

 

 

7.13.1.1 McBSP Peripheral Register Description(s).....................................................

191

 

7.13.2

McBSP Electrical Data/Timing ...............................................................................

193

 

 

7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing .........................................

193

7.14

Ethernet MAC (EMAC) ...................................................................................................

200

 

7.14.1

EMAC Device-Specific Information ..........................................................................

201

 

7.14.2

EMAC Peripheral Register Description(s) ..................................................................

204

 

7.14.3

EMAC Electrical Data/Timing.................................................................................

208

 

 

7.14.3.1 EMAC MII and GMII Electrical Data/Timing ..................................................

208

 

 

7.14.3.2 EMAC RMII Electrical Data/Timing..............................................................

211

 

 

7.14.3.3 EMAC RGMII Electrical Data/Timing............................................................

213

 

7.14.4

Management Data Input/Output (MDIO) ...................................................................

216

 

 

7.14.4.1

MDIO Device-Specific Information ..............................................................

216

 

 

7.14.4.2 MDIO Peripheral Register Description(s).......................................................

216

 

 

7.14.4.3

MDIO Electrical Data/Timing .....................................................................

217

7.15

Timers

......................................................................................................................

 

218

 

7.15.1

Timers Device-Specific Information..........................................................................

218

 

7.15.2

Timers Peripheral Register Description(s)..................................................................

218

 

7.15.3

Timers Electrical Data/Timing ................................................................................

219

7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2).....................................................................

220

 

7.16.1

VCP2 Device-Specific Information...........................................................................

220

 

7.16.2

VCP2 Peripheral Register Description(s) ...................................................................

220

Contents 5

SM320C6455-EP

FIXED-POINTDIGITAL SIGNAL PROCESSOR

SPRS462B–SEPTEMBER2007–REVISEDJANUARY 2008

 

7.17 Enhanced Turbo Decoder Coprocessor (TCP2)......................................................................

221

 

 

7.17.1

TCP2 Device - Specific Information ...........................................................................

221

 

 

7.17.2 TCP2 Peripheral Register Description(s) ...................................................................

222

 

7.18 Peripheral Component Interconnect (PCI) ............................................................................

223

 

 

7.18.1

PCI Device - Specific Information .............................................................................

223

 

 

7.18.2 PCI Peripheral Register Description(s)......................................................................

224

 

 

7.18.3

PCI Electrical Data/Timing ....................................................................................

229

 

7.19

UTOPIA

....................................................................................................................

230

 

 

7.19.1 ........................................................................

UTOPIA Device - Specific Information

230

 

 

7.19.2 ................................................................UTOPIA Peripheral Register Description(s)

230

 

 

7.19.3 ..............................................................................

UTOPIA Electrical Data/Timing

231

 

7.20 Serial RapidIO ..............................................................................................(SRIO) Port

234

 

 

7.20.1 ................................................................Serial RapidIO Device-SpecificInformation

234

 

 

7.20.2 ........................................................Serial RapidIO Peripheral Register Description(s)

234

 

 

7.20.3 .......................................................................Serial RapidIO Electrical Data/Timing

244

 

7.21

General- .................................................................................PurposeInput/Output (GPIO)

246

 

 

7.21.1 ...........................................................................

GPIO Device - Specific Information

246

 

 

7.21.2 ...................................................................GPIO Peripheral Register Description(s)

246

 

 

7.21.3 ..................................................................................

GPIO Electrical Data/Timing

247

 

7.22 Emulation .....................................................................................Features and Capability

248

 

 

7.22.1 ...........................................................................Advanced Event Triggering (AET)

248

 

 

7.22.2 .............................................................................................................

Trace

248

 

 

7.22.3 .............................................................................................

IEEE 1149.1 JTAG

249

 

 

...............................................................

7.22.3.1 JTAG Device - Specific Information

249

 

 

7.22.4 ...................................................................JTAG Peripheral Register Description(s)

249

 

 

7.22.5 .................................................................................

JTAG Electrical Data/Timing

249

Revision History ........................................................................................................................

 

250

8

Mechanical Data ...............................................................................................................

251

 

8.1

Thermal ..............................................................................................................Data

251

 

8.2

Packaging ...................................................................................................Information

251

6

Contents

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1 Features

Controlled Baseline

One Assembly Site

Test Site

One Fabrication Site

Enhanced Diminishing Manufacturing Sources (DMS) Support

Enhanced Product-ChangeNotification

Qualification Pedigree(1)

High-PerformanceFixed-PointDSP (C6455)

1.39 ns, 1.17 ns, 1 ns, and 0.83 ns Instruction Cycle Time

1 GHz Clock Rate

Eight 32 Bit Instructions/Cycle

9600 MIPS/MMACS (16 Bits)

Commercial Temperature (0°C to 90°C)

Extended Temperature (–40°Cto 105°C)

S-Temp(–55°Cto 105°C)

C64x+™ DSP Core

Dedicated SPLOOP Instruction

Compact Instructions (16 Bit)

Instruction Set Enhancements

Exception Handling

C64x+ Megamodule L1/L2 Memory Architecture:

256K Bit (32K Byte) L1P Program Cache (Direct Mapped)

256K Bit (32K Byte) L1D Data Cache [2-WaySet-Associative]

16M Bit (2096K Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)

256K Bit (32K Byte) L2 ROM

Time Stamp Counter

Enhanced VCP2

Supports Over 694 7.95 Kbps AMR

Programmable Code Parameters

Enhanced Turbo Decoder Coprocessor (TCP2)

Supports up to Eight 2 Mbps 3GPP (6 Iterations)

Programmable Turbo Code and Decoding

(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

SM320C6455-EPFIXED-POINTDIGITAL SIGNAL PROCESSOR

SPRS462B–SEPTEMBER2007–REVISEDJANUARY 2008

Parameters

Endianess: Little Endian, Big Endian

64 Bit External Memory Interface (EMIFA)

Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM) and Synchronous Memories (SBSRAM, ZBT SRAM)

Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.)

32M Byte Total Addressable External Memory Space

Four 1x Serial RapidIO® Links (or One 4x), v1.2 Compliant

1.25/2.5/3.125 Gbps Link Rates

Message Passing, DirectIO Support, Error Management Extensions, and Congestion Control

IEEE 1149.6 Compliant I/Os

DDR2 Memory Controller

Interfaces to DDR2-533SDRAM

32 Bit/16 Bit, 533 MHz (data rate) Bus

512M Byte Total Addressable External Memory Space

EDMA3 Controller (64 Independent Channels)

32/16 Bit Host-PortInterface (HPI)

32 Bit 33/66 MHz, 3.3 V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Local Bus Specification

(version 2.3)

One Inter-IntegratedCircuit (I2C) Bus

Two McBSPs

10/100/1000 Mb/s Ethernet MAC (EMAC)

IEEE 802.3 Compliant

Supports Multiple Media Independent Interfaces (MII, GMII, RMII, and RGMII)

Eight Independent Transmit (TX) and Eight Independent Receive (RX) Channels

Two 64 Bit General-PurposeTimers, Configurable as Four 32 Bit Timers

UTOPIA

UTOPIA Level 2 Slave ATM Controller

8 Bit Transmit and Receive Operations up to 50 MHz per Direction

User-DefinedCell Format up to 64 Bytes

16 General-PurposeI/O (GPIO) Pins

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.

C64x+, JTAG, C64x+, VelociTI, C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007–2008,Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

 

Instruments standard warranty. Production processing does not

 

necessarily include testing of all parameters.

 

SM320C6455-EP

 

FIXED-POINTDIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B–SEPTEMBER2007–REVISEDJANUARY 2008

 

System PLL and PLL Controller

Boundary-Scan-Compatible

Secondary PLL and PLL Controller, Dedicated

697-PinBall Grid Array (BGA) Package

 

to EMAC and DDR2 Memory Controller

(ZTZ or GTZ Suffix), 0.8 mm Ball Pitch

Advanced Event Triggering (AET) Compatible

0.09μm/7-LevelCu Metal Process (CMOS)

Trace-EnabledDevice

3.3/1.8/1.5/1.25/1.2 V I/Os, 1.25/1.2 V Internal

IEEE-1149.1(JTAG™)

 

1.1ZTZ/GTZ BGA Package (Bottom View)

Figure 1-1 shows theSM320C6455-EPdevice697-pinball grid array package (bottom view).

ZTZ/GTZ 697-PINBALL GRID ARRAY (BGA) PACKAGE

( BOTTOM VIEW )

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11

13

15

17

19

21 23

25

27

29

2

 

4

6

8

10

12

14

16

18

20 22

24

26

28

NOTE: The ZTZ mechanical package designator represents the version of the GTZ package with lead-freeballs. For more detailed information, see theMechanical Data section of this document.

Figure 1-1.ZTZ/GTZ BGA Package (Bottom View)

1.2Description

The C64x+™ DSPs (including the SM320C6455-EPdevice) are thehighest-performancefixed-pointDSP generation in the C6000™ DSP platform. The C6455 device is based on thethird-generationhigh-performance,advanced VelociTI™very-long-instruction-word(VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices are upwardcode-compatiblefrom previous devices that are part of the C6000™ DSP platform.

Based on 90-nmprocess technology and with performance of up to 9600 million instructions per second (MIPS) [or 9600 16 bit MMACs per cycle] at a1.2-GHzclock rate, the C6455 device offerscost-effectivesolutions tohigh-performanceDSP programming challenges. The C6455 DSP possesses the operational flexibility ofhigh-speedcontrollers and the numerical capability of array processors.

8

Features

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The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16 bit x 16 bit multiply-accumulates(MACs) every clock cycle. Thus, eight 16 bit x 16 bit MACs can be executed every cycle on the C64x+ core. At a1.2-GHzclock rate, this means 9600 16 bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one 32 bit x 32 bit MAC or four 8 bit x 8 bit MACs every clock cycle.

The C6455 device includes Serial RapidIO. This high bandwidth peripheral dramatically improves system performance and reduces system cost for applications that include multiple DSPs on a board, such as video and telecom infrastructures and medical/imaging.

The C6455 DSP integrates a large amount of on-chipmemory organized as atwo-levelmemory system. Thelevel-1(L1) program and data memories on the C6455 device are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache where as L1 data (L1D) is atwo-wayset associative cache. The level 2 (L2) memory is shared between program and data space and is 2096KB in size. L2 memory also can be configured as mapped RAM, cache, or some combination of the two. The C64x+ Megamodule also has a 32 bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, apower-downcontrol, and afree-running32 bit timer for time stamp.

The peripheral set includes: an inter-integratedcircuit bus module (I2C); two multichannel buffered serial ports (McBSPs); an 8 bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 64 bitgeneral-purposetimers (also configurable as four 32 bit timers); auser-configurable16 bit or 32 bithost-portinterface (HPI16/HPI32); a peripheral component interconnect (PCI); a16-pingeneral-purposeinput/output port (GPIO) with programmable interrupt/event generation modes; an 10/100/1000 Ethernet media access controller (EMAC), which provides an efficient interface between the C6455 DSP core processor and the network; a management data input/output (MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system; a glueless external memory interface (64 bit EMIFA), which is capable of interfacing to synchronous and asynchronous peripherals; and a 32 bit DDR2 SDRAM interface.

The I2C ports on the C6455 allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6455 device has two high-performanceembedded coprocessors [enhanced Viterbi Decoder Coprocessor (VCP2) and enhanced Turbo Decoder Coprocessor (TCP2)] that significantly speed upchannel-decodingoperationson-chip.The VCP2 operating at CPU clockdivided-by-3can decode over 6947.95-Kbpsadaptivemulti-rate(AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5 and flexible polynomials, while generating hard decisions or soft decisions. The TCP2 operating at CPU clockdivided-by-3can decode up to fifty384-Kbpsor eight2-Mbpsturbo encoded channels (assuming 6 iterations). The TCP2 implements themax*log-mapalgorithm and is designed to support all polynomials and rates required byThird-GenerationPartnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP2/TCP2 and the CPU are carried out through the EDMA3 controller.

The C6455 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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Features

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SPRS462B–SEPTEMBER2007–REVISEDJANUARY 2008

1.3Functional Block Diagram

Figure 1-2 shows the functional block diagram of the C6455 device.

DDR2 SDRAM

32

DDR2

 

 

 

 

 

 

 

 

 

 

 

 

 

C6455

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mem Ctlr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SBSRAM

 

PLL2 and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZBT SRAM

 

PLL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Controller(D)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L2 ROM

 

64

 

 

 

 

 

 

L1P Cache Direct-Mapped

 

 

 

 

EMIFA

 

 

 

 

 

 

 

 

32K

 

 

 

 

 

 

 

 

32K Bytes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bytes(E)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRAM

 

TCP2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ROM/FLASH

 

VCP2

 

 

 

L1P Memory Controller (Memory Protect/Bandwidth Mgmt)

I/O Devices

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

McBSP0(A)

 

 

 

 

 

 

C64x+ DSP Core

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Fetch

Control Registers

 

 

L2 Memory Controller (Memory Protect/ Bandwidth Mgmt)

 

 

McBSP1(A)

 

 

 

 

16-/32-bit

 

 

 

 

 

Interrupt and Exception Controller

Power Control

 

 

 

 

L2

 

 

 

SPLOOP Buffer

 

 

 

 

 

Instruction Dispatch

 

 

Serial Rapid

Switched Central Resource

Cache

 

 

Instruction

 

In-CircuitEmulation

 

 

Memory

 

 

 

 

 

I/O

M

 

Decode

 

 

 

2096K

 

 

 

 

 

 

 

 

 

e

 

Data Path A

Data Path B

 

 

 

HPI (32/16)(B)

Bytes

g

 

 

 

 

 

a

 

A Register File

B Register File

 

 

 

 

m

 

 

 

 

 

 

 

o

 

A31−A16

 

 

B31−B16

 

 

 

 

 

PCI66(B)

 

d

 

A15−A0

 

 

B15−B0

 

 

Internal DMA (IDMA)

 

 

 

 

u

 

 

 

 

 

 

 

 

(B)

 

 

 

 

l

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System

 

 

UTOPIA(B)

 

e

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.L1

.S1

.M1

.D1

.D2

.M2

.S2

.L2

 

 

EMAC

 

 

xx

xx

 

 

Primary

 

 

 

 

 

 

 

 

 

 

 

 

 

10/100/1000

 

 

 

 

xx

 

 

xx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MII

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RMII

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GMII

 

 

 

L1D Memory Controller (Memory Protect/Bandwidth Mgmt)

 

 

RMGII(D)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MDIO

 

 

 

 

 

 

L1D Cache

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

GPIO16(B)

 

 

 

 

 

 

2-Way

 

 

 

 

 

 

 

 

 

 

 

 

 

Set-Associative

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32K Bytes Total

 

 

 

 

 

 

 

I2C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timer1(C)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LO

 

 

 

EDMA 3.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLL1 and

 

 

Device

 

 

Timer0(C)

 

 

 

 

 

 

 

 

PLL1

 

Configuration

 

 

HI

 

 

 

Secondary

 

 

 

Controller

 

 

Logic

 

 

 

 

Switched Central

 

 

 

 

 

 

 

 

 

 

 

LO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Resource

 

 

 

Boot Configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A.McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs

B.The PCI peripheral pins are muxed with some of the HPI peripheral pins and the UTOPIA address pins. For more detailed information, see the Device Configuration section of this document.

C.Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as either two 64-bitgeneral-purposetimersor two32-bitgeneral-purposetimersor a watchdog timer.

D.The PLL2 controller also generates clocks for the EMAC.

E.When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.

Figure 1-2.Functional Block Diagram

10

Features

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