Texas Instruments SLOU061A User Manual

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Universal Operational Amplifier

Single, Dual, Quad (SOIC)

Evaluation Module

With Shutdown

User’s Guide

April 2001

Mixed-SignalProducts

SLOU061A

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, license, warranty or endorsement thereof.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.

Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.

Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm

Mailing Address:

Texas Instruments

Post Office Box 655303

Dallas, Texas 75265

Copyright 2001, Texas Instruments Incorporated

Preface

Related Documentation From Texas Instruments

JAmplifiers and Comparators Data Book (literature number SLOD002). This data book contains data sheets and other information on the TI operational amplifiers that can be used with this evaluation module.

JPower Supply Circuits Data Book (literature number SLVD002). This data book contains data sheets and other information on the TI shunt regulators that can be used with this evaluation module.

FCC Warning

This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference.

Trademarks

PowerPAD is a trademark of Texas Instruments.

Chapter Title—AttributeReference

iii

iv

Running Title—AttributeReference

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

2 Evaluation Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Physical Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22.2 Area 100— Single Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-32.3 Area 200— Dual Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-42.4 Area 300— Quad Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-52.5 General Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-72.6 EVM Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-82.7 EVM Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9

3 Example Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

3.1

Schematic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2

3.2

Inverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2

3.3

Noninverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3

3.4

Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-4

3.5

Sallen-KeyLow-PassFilter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-5

3.6

Sallen-KeyHigh-PassFilter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6

3.7

Two Operational Amplifier Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-8

3.8

Quad Operational Amplifier Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-10

Chapter Title—AttributeReference

v

Running Title—AttributeReference

Figures

2–1Area 100 Schematic— Single Device, SOIC(8-pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-32–2Area 200 Schematic— Dual Device, SOIC(14-pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-42–3Area 300 Schematic— Quad Device, SOIC(16-pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-62–4Maximum Power Dissipation vsFree-AirTemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-72–5EVM Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-82–6EVM Board Layout— Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-92–7EVM Board Layout— Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10

3–1Inverting Amplifier with Dual Supply Using Area 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23–2Noninverting Amplifier with Single Supply Using Area 100 . . . . . . . . . . . . . . . . . . . . . . . . . .3-33–3Single Operational Amplifier Differential Amplifier With Single Supply Using Area 100 . .3-43–4Sallen-KeyLow-PassFilter With Dual Supply Using Area 200 . . . . . . . . . . . . . . . . . . . . . . .3-53–5Sallen-KeyHigh-PassFilter With Single Supply Using Area 200 . . . . . . . . . . . . . . . . . . . . .3-73–6Two Operational Amplifier Instrumentation Amplifier With Single Supply Using Area 2003-93–7Quad Operational Amplifier Instrumentation Amplifier With Dual Supply Using Area 3003-11

Table

2–1

Dissipation Rating Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-7

vi

Chapter 1

Introduction

This user’s guide describes the universal operational amplifier single, dual, quad (SOIC) evaluation module (EVM) with shutdown (SLOP248). The EVM simplifies evaluation of Texas Instruments surface-mountop amps with or without shutdown feature.

Topic

 

Page

 

 

 

1.1

Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 1–2

1.2

Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. 1–2

 

 

 

Introduction 1-1

Design Features

1.1 Design Features

The EVM board design allows many circuits to be constructed easily and quickly. There are three circuit development areas on the board, and each uses IC amplifiers in the SOIC package. Area 100 is for a single operational amplifier (op amp), with or without shutdown. It also features offset nulling pin pads. Area 200 is for a dual op amp, with or without shutdown. Area 300 is for a quad op amp, with or without shutdown. A few possible circuits include:

-Voltage follower

-Noninverting amplifier

-Inverting amplifier

-Simple or algebraic summing amplifier

-Difference amplifier

-Current to voltage converter

-Voltage to current converter

-Integrator/low-passfilter

-Differentiator/high-passfilter

-Instrumentation amplifier

-Sallen-Keyfilter

The EVM PCB is of two-layerconstruction, with a ground plane on the solder side. Circuit performance should be comparable to final production designs.

1.2 Power Requirements

The devices and designs that are used dictate the input power requirements. Three input terminals are provided for each area of the board:

Vx+

Positive input power for area x00

i.e., V1+

area 100

GNDx

Ground reference for area x00

i.e., GND2

area 200

Vx–

Negative input power for area x00

i.e., V3–

area 300

Each area has four bypass capacitors – two for the positive supply, and two for the negative supply. Each supply should have a 1- F to 10- F capacitor for low-frequencybypassing and a 0.01- F to 0.1- F capacitor forhigh-frequencybypassing.

When using single-supplycircuits, the negative supply is shorted to ground by bridging C104 or C105 in area 100, C209 or C210 in area 200, or C311 or C312 in area 300. Power input is between Vx+ and GNDx. The voltage reference circuitry is provided forsingle-supplyapplications that require a reference voltage to be generated.

1-2

Introduction

Chapter 2

Evaluation Module Layout

This chapter shows the universal operational amplifier single, dual, quad (SOIC) evaluation module (EVM) with shutdown board layout, schematics of each area, and describes the relationships between the three areas.

Topic

 

Page

 

 

 

2.1

Physical Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 2–2

2.2

Area 100—SingleDevice SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. 2–3

2.3

Area 200—DualDevice SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. 2–4

2.4

Area 300—QuadDevice SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. 2–5

2.5

General Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . .

. 2–7

2.6

Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. 2–8

2.7

Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. 2–9

 

 

 

Evaluation Module Layout

2-1

Physical Considerations

2.1 Physical Considerations

The EVM board has three circuit development areas. Each area can be separated from the others by breaking along the score lines. The circuit layout in each area supports an op amp package, voltage reference, and ancillary devices. The op amp package is unique to each area as described in the following paragraphs. The voltage reference and supporting devices are the same for all areas. Surface-mountorthrough-holecomponents can be used for all capacitors and resistors on the board.

The voltage reference can be either surface-mountorthrough-hole.Ifsurface-mountis desired, the TLV431ACDBV5 or TLV431AIDBV5 adjustable shunt regulators can be used. If through hole is desired, the TLV431ACLP, TLV431AILP, TL431CLP, TL431ACLP, TL431ILP, or TL431AILP adjustable shunt regulators can be used. Refer to Texas Instruments’Power Supply Circuits Data Book (literature number SLVD002) for details on usage of these shunt regulators.

Each passive component (resistor or capacitor) has a surface mount 1206 footprint with through holes at 0.2″ spacing on the outside of the 1206 pads. C105, C106, C107, C207, C208, C209, C312, C314, and C315 have a surface mount 1210 footprint with through holes at 0.2″ spacing on the outside of the 1210 pads. Therefore, either surface-mountorthrough-holeparts can be used. The potentiometer for the offset nulling feature in area 100 can also be either asurface-mountor athrough-holeunit.

Figures 2–1through2–3show schematics for each of the board areas. The schematics show all components that the board layout can accommodate. These should only be used as reference, since not all components will be used at any one time.

2-2

Evaluation Module Layout