Texas Instruments SCAU020 User Manual
Size:
987.23 Kb
Download

10.9MHz–1175MHzLow Phase Noise Clock Evaluation Board

User's Guide

March 2007

Serial Link Products

SCAU020

2

SCAU020 –March2007

Submit Documentation Feedback

Contents

1

General Description.....................................................................................................

5

2

Signal Path and Control Circuitry..................................................................................

6

3

Block Description........................................................................................................

7

 

3.1

Block A ............................................................................................................

7

 

3.2

Block B ............................................................................................................

7

 

3.3

Block C ............................................................................................................

7

 

3.4

Block D ............................................................................................................

7

4

Software-Selectable Options ........................................................................................

7

5

Installing the Software GUI and USB Driver....................................................................

8

6

ChronosGUI ...............................................................................................................

9

 

6.1

Using Software-Enabled Automatic PLL Selection ..........................................................

9

 

6.2

Manual PLL Block Selection (Advanced Control) ..........................................................

11

7

Configuring the Board ...............................................................................................

13

 

7.1

Programming and Testing Configuration (USB Cable Attached)—DefaultConfiguration.............

13

 

7.2

Programming Configuration (USB Cable Attached)........................................................

13

7.3Testing Configuration from a Saved Configuration (with USB Cable Removed After

 

Programming) ...................................................................................................

13

8

Schematics and Layout ..............................................................................................

14

Important Notices ...............................................................................................................

20

SCAU020 –March2007

Table of Contents

3

Submit Documentation Feedback

 

 

List of Figures

 

1

CDCE421EVM Evaluation Board ..........................................................................................

5

2

CDCE421EVM Programming Blocks......................................................................................

6

3

Software Installation Screen................................................................................................

 

8

4

Installation Prompt ...........................................................................................................

 

8

5

TI Chronos Software GUI ...................................................................................................

 

9

6

Chronos GUI—Loop Filter Configuration Pop-Up......................................................................

10

7

Chronos GUI—Manual PLL Block Selection Pop-Up..................................................................

11

8

JP1 Setting for USB Programming Configuration......................................................................

13

9

CDCE421EVM Block Switch Off .........................................................................................

14

10

CDCE421EVM Board Schematic ........................................................................................

15

11

CDCE421EVM Board—Block

A Schematic ............................................................................

16

12

CDCE421EVM Board—Block

B Schematic ............................................................................

17

13

CDCE421EVM Board—Block

C Schematic ............................................................................

18

14

CDCE421EVM Board—Block

D Schematic ............................................................................

19

4

List of Figures

SCAU020 –March2007

Submit Documentation Feedback

User's Guide

SCAU020 – March 2007

10.9MHz–1175MHzLow Phase Noise Clock Evaluation Board

Figure 1. CDCE421EVM Evaluation Board

Features:

Easy-to-useevaluation module generates low phase noise clocks between10.9MHz—1175MHz

Simple device programming via host-poweredUSB port

Fast configuration through provided software GUI

Total board power provided either through USB port or separate 3.3V and ground connections

LVCMOS input interface or crystal input

Standard 6-pinXO package connection available (forCDCE421-enabledXO devices)

1General Description

The CDCE421 is a high-performance,low phase noise clock generator. It has two fully integrated,low-noise,liquid crystal(LC)-basedvoltage-controlledoscillators (VCOs) that operate in the1.75GHz–2.35GHzrange.

The CDCE421 has an integrated crystal oscillator circuitry that operates in conjunction with an external AT-cutcrystal to produce a stable frequency reference for thePLL-basedfrequency synthesizer. A 3.3V LVCMOS level input can also be used instead of a crystal to provide a PLL frequency reference.

The evaluation module (EVM) is designed to quickly demonstrate the electrical performance of the device. This fully assembled and factory-testedEVM allows complete validation of all device functions for a variety of applications. Throughout this document, the acronymEVM and the phrasesevaluation module andevaluation board are synonymous with the CDCE421EVM.Figure 1 illustrates the CDCE421EVM.

For optimum performance, the board is equipped with 50Ω SMA connectors andwell-controlled50Ω impedance microstrip transmission lines.

Windows, Windows XP are registered trademarks of Microsoft Corporation.

All other trademarks are the property of their respective owners.

SCAU020 –March2007

10.9MHz–1175MHzLow Phase Noise Clock Evaluation Board

5

Submit Documentation Feedback

www.ti.com

Signal Path and Control Circuitry

2Signal Path and Control Circuitry

The CDCE421 can accept a 27MHz—38.33MHzfrequency input from either an LVCMOS source (up to 3.3V) or a crystal in the same frequency range.

The CDCE421EVM is divided into four blocks. The programming section and device power for each sector can be enabled or disabled through individual switches provided for each block. For example, in order to enable power and programming for Block A, the switch must be in the setting shown in Figure 2. The other blocks are enabled and disabled with the respective switches in the same manner.

The CDCE421 output frequency is always an integer multiple or integer divide of the input frequency, and is determined through selection of VCO1 or VCO2 and the appropriate prescalar and output divider, based on the CDCE421 data sheet.

The loop filter selection affects the output frequency phase noise and should be considered in conjunction with the type of input used.

In LVDS mode, the device can achieve up to 500MHz output. In LVPECL mode, the device can achieve 1175MHz output. The output signaling level and LVPECL termination are selectable through the software interface.

Figure 2. CDCE421EVM Programming Blocks

6

10.9MHz–1175MHzLow Phase Noise Clock Evaluation Board

SCAU020 –March2007

Submit Documentation Feedback