Texas Instruments MSP430x11x1 User Manual

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MSP430x11x1

 

 

 

 

 

 

MIXED SIGNAL MICROCONTROLLER

 

 

 

 

 

 

 

 

 

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

 

 

 

 

 

 

 

 

 

 

 

 

 

D Low Supply Voltage Range 1.8 V ± 3.6 V

 

 

D

 

Serial Onboard Programming

D Ultralow-PowerConsumption

 

 

D Programmable Code Protection by Security

Low Operation Current,

 

 

 

 

Fuse (C11x1 Only)

 

 

1.3 A at 4 kHz, 2.2 V

 

 

D

 

Family Members Include:

 

 

160 A at 1 MHz, 2.2 V

 

 

 

 

 

 

 

 

 

MSP430C1111: 2KB ROM,128B RAM

 

 

 

 

 

D Five Power Saving Modes:

 

 

 

 

MSP430C1121: 4KB ROM, 256B RAM

(Standby Mode: 0.8 A,

 

 

 

 

MSP430F1101: 1KB + 128B Flash Memory

RAM Retention Off Mode: 0.1 A)

 

 

 

 

 

 

 

 

 

(MTP{), 128B RAM

D Wake-UpFrom Standby Mode in 6 s

 

 

 

 

MSP430F1121: 4KB + 256B Flash Memory

D 16-BitRISC Architecture, 125 ns

 

 

 

 

 

 

 

 

 

(MTP{), 256B RAM

 

 

D Available in a20-PinPlasticSmall-Outline

Instruction Cycle Time

 

 

 

 

 

 

Wide Body (SOWB) Package and 20-Pin

D Basic Clock Module Configurations:

 

 

 

 

 

 

 

 

Plastic Thin Shrink Small-OutlinePackage

± Various Internal Resistors

 

 

 

 

 

 

 

 

(TSSOP)

 

 

 

 

 

± Single External Resistor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

± 32 kHz Crystal

 

 

 

 

 

 

 

DW OR PW PACKAGE

 

 

± High Frequency Crystal

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(TOP VIEW)

 

 

± Resonator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

± External Clock Source

 

 

 

TEST

 

 

 

1

20

 

 

P1.7/TA2/TDO/TDI

 

 

 

 

 

 

 

 

D 16-BitTimer With Three Capture/Compare

 

 

VCC

 

 

 

2

19

 

 

P1.6/TA1/TDI

 

 

 

 

 

 

 

P2.5/Rosc

 

 

 

3

18

 

 

P1.5/TA0/TMS

Registers

 

 

 

 

VSS

 

 

 

4

17

 

 

P1.4/SMCLK/TCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D Slope A/D Converter With External

 

 

XOUT

 

 

 

5

16

 

 

P1.3/TA2

 

 

 

 

XIN

 

 

 

6

15

 

 

P1.2/TA1

Components

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RST/NMI

 

 

 

7

14

 

 

P1.1/TA0

 

 

 

 

 

 

 

D On-ChipComparator for Analog Signal

 

P2.0/ACLK

 

 

 

8

13

 

 

P1.0/TACLK

 

 

 

 

 

 

Compare Function or Slope A/D

 

P2.1/INCLK

 

 

 

9

12

 

 

P2.4/CA1/TA2

 

 

 

 

 

 

 

 

 

 

 

 

Conversion

P2.2/CAOUT/TA0

 

 

 

10

11

 

 

P2.3/CA0/TA1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

description

The Texas Instruments MSP430 series is an ultralow-powermicrocontroller family consisting of several devices featuring different sets of modules targeted to various applications. The microcontroller is designed to be battery operated for anextended-applicationlifetime. With16-bitRISC architecture, 16 bit integrated registers on the CPU, and a constant generator, the MSP430 achieves maximum code efficiency. Thedigitally-controlledoscillator provides fastwake-upfrom alllow-powermodes to active mode in less than 6ms.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. Stand alone RF sensor front end is another area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors. The MSP430x11x series is an ultralow-powermixed signal microcontroller with a built in16-bittimer and fourteen I/O pins. The MSP430x11x1 family adds a versatile analog comparator.

The flash memory provides added flexibility of in-systemprogramming and data storage without significantly increasing the current consumption of the device. The programming voltage is generatedon-chip,thereby alleviating the need for an additional supply, and even allowing for reprogramming ofbattery-operatedsystems.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

{ MTP = Multiple Time Programmable

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

1

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

AVAILABLE OPTIONS

 

PACKAGED DEVICES

 

 

 

TA

PLASTIC

PLASTIC

20-PINSOWB

20-PINTSSOP

 

 

(DW)

(PW)

 

 

 

 

MSP430C1111IDW

MSP430F1101IPW

±40°C to 85°C

MSP430C1121IDW

MSP430F1121IPW

MSP430F1101IDW

 

 

 

 

MSP430F1121IDW

 

 

 

 

functional block diagram

 

 

 

XIN XOUT

 

 

VCC

VSS

 

 

 

 

 

 

 

 

 

 

 

RST/NMI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rosc

 

 

Oscillator

 

ACLK

1/2/4 KB ROM/

 

128/256B

 

Power-on-

 

 

 

 

 

 

 

System Clock

 

SMCLK

Flash+126/256B

 

 

 

 

 

 

 

 

 

Flash INFO

 

RAM

 

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

'C': ROM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

'F': Flash

 

 

 

 

 

 

 

 

 

 

MCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.0±7

 

 

8

 

Outx

I/O Port P1

JTAG

CCIxA

8 I/O's, All With

 

TACLK

 

Interrupt

 

SMCLK

 

Capabililty

 

 

 

 

 

 

 

 

 

 

 

 

 

MAB, 16 Bit

 

 

 

 

 

 

 

 

 

 

 

MAB, 4 Bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPU

 

Test

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Incl. 16 Reg.

 

JTAG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MDB, 16 Bit

 

 

 

 

 

 

 

 

 

 

 

MDB, 8 Bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Conv.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TACLK or

 

 

 

INCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Watchdog

 

Timer_A

 

 

INCLK

Comparator-A

 

 

 

 

 

 

I/O Port P2

 

 

 

 

²

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CCI1

 

 

 

CCI1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timer

 

 

3 CC

 

 

 

 

Input Multiplexer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6 I/O's All With

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register

 

 

Outx

RC Filtered O/P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Out0

 

 

 

 

Interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ACLK

 

 

 

 

 

CCR0/1/2

 

 

CCIx

Internal Vref

 

 

 

 

Capabililty

 

 

 

ACLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15/16 Bit

 

 

 

Analog Switch

 

 

 

 

 

 

 

 

 

 

 

 

DCOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SMCLK

 

 

x = 0, 1, 2

 

 

CCIx

CCI0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P2.0 / ACLK

 

 

 

 

 

 

 

 

P2.5 / Rosc

 

 

 

 

 

 

 

P2.1 / INCLK

 

 

 

 

P2.4 / CA1/TA2

 

 

 

 

 

 

 

²

P2.2 / CAOUT/TA0

 

 

 

 

 

P2.3 / CA0/TA1

 

 

 

 

A pulldown resistor of 30 kΩ is needed on F11x1.

 

 

 

 

 

2

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

 

 

 

 

 

MSP430x11x1

 

 

 

 

 

MIXED SIGNAL MICROCONTROLLER

 

 

 

 

 

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

 

 

 

 

 

 

 

 

 

 

 

 

Terminal Functions

 

 

 

 

 

 

 

 

 

TERMINAL

 

I/O

DESCRIPTION

 

 

 

NAME

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.0/TACLK

13

I/O

General-purposedigital I/O pin/Timer_A, clock signal TACLK input

 

 

 

 

 

 

 

 

 

P1.1/TA0

14

I/O

General-purposedigital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output

 

 

 

 

 

 

 

 

 

P1.2/TA1

15

I/O

General-purposedigital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output

 

 

 

 

 

 

 

 

 

P1.3/TA2

16

I/O

General-purposedigital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output

 

 

 

 

 

 

 

 

 

P1.4/SMCLK/TCK

17

I/O

General-purposedigital I/O pin/SMCLK signal output/test clock, input terminal for device programming

 

 

 

 

 

 

and test

 

 

 

 

 

 

 

 

 

P1.5/TA0/TMS

18

I/O

General-purposedigital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for

 

 

 

 

 

 

device programming and test

 

 

 

 

 

 

 

 

 

P1.6/TA1/TDI

19

I/O

General-purposedigital I/O pin/Timer_A, compare: Out1 output/test data input terminal

 

 

 

 

 

 

 

 

 

P1.7/TA2/TDO/TDI²

20

I/O

General-purposedigital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input

 

 

 

 

 

 

during programming

 

 

 

 

 

 

 

 

 

P2.0/ACLK

8

I/O

General-purposedigital I/O pin/ACLK output

 

 

 

 

 

 

 

 

 

P2.1/INCLK

9

I/O

General-purposedigital I/O pin/Timer_A, clock signal at INCLK

 

 

 

 

 

 

 

 

 

P2.2/CAOUT/TA0

10

I/O

General-purposedigital I/O pin/Timer_A, capture: CCI0B input/comparator_A, output

 

 

 

 

 

 

 

 

 

P2.3/CA0/TA1

11

I/O

General-purposedigital I/O pin/Timer_A, compare: Out1 output/comparator_A, input

 

 

 

 

 

 

 

 

 

P2.4/CA1/TA2

12

I/O

General-purposedigital I/O pin/Timer_A, compare: Out2 output/comparator_A, input

 

 

 

 

 

 

 

 

 

P2.5/Rosc

3

I/O

General-purposedigital I/O pin/Input for external resistor that defines the DCO nominal frequency

 

 

 

 

7

I

Reset or nonmaskable interrupt input

 

 

RST/NMI

 

 

 

 

 

 

 

 

TEST

1

I

Select of test mode for JTAG pins on Port1. Must be tied low with less than 30 kΩ (F11x1).

 

 

 

 

 

 

 

 

VCC

2

 

Supply voltage

 

 

 

 

 

 

 

 

VSS

4

 

Ground reference

 

 

XIN

6

I

Input terminal of crystal oscillator

 

 

 

 

 

 

 

 

XOUT

5

I/O

Output terminal of crystal oscillator

 

² TDO or TDI is selected via JTAG instruction.

short-formdescription

processing unit

The processing unit is based on a consistent, and orthogonally-designedCPU and instruction set. This design structure results in aRISC-likearchitecture, highly transparent to the application development, and noted for its programming simplicity. All operations other thanprogram-flowinstructions are consequently performed as register operations in conjunction with seven addressing modes for source, and four modes for destination operands.

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

3

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

short-formdescription (continued)

CPU

All sixteen registers are located inside the CPU, providing reduced instruction execution time. This reduces a register-registeroperation execution time to one cycle of the processor.

Program Counter

PC/R0

 

SP/R1

 

Stack Pointer

 

SR/CG1/R2

 

Status Register

 

 

Four registers are reserved for special use as a program counter, a stack pointer, a status register, and a constant generator. The remaining twelve registers are available as general-purposeregisters.

Peripherals are connected to the CPU using a data address and control buses and can be handled easily with all instructions for memory manipulation.

instruction set

Constant Generator

CG2/R3

 

 

 

 

General-PurposeRegister

R4

 

R5

 

General-PurposeRegister

 

 

 

 

General-PurposeRegister

R14

 

R15

 

General-PurposeRegister

 

 

The instructions set for this register-registerarchitecture provides a powerful andeasy-to-useassembly language. The instruction set consists of 51 instructions with three formats and seven addressing modes. Table 1 provides a summation and example of the three types of instruction formats; the addressing modes are listed in Table 2.

Table 1. Instruction Word Formats

Dual operands, source-destination

e.g. ADD R4, R5

R4 + R5 → R5

Single operands, destination only

e.g. CALL R8

PC → (TOS), R8 → PC

Relative jump, un-/conditional

e.g. JNE

Jump-onequal bit = 0

 

 

 

Most instructions can operate on both word and byte data. Byte operations are identified by the suffix B.

Examples:

Instructions for word operation

Instructions for byte operation

 

 

MOV

 

EDE,TONI

MOV.B

EDE,TONI

 

 

ADD

 

#235h,&MEM

ADD.B

#35h,&MEM

 

 

PUSH

 

R5

PUSH.B

R5

 

 

 

SWPB

 

R5

Ð

 

 

 

 

 

 

Table 2. Address Mode Descriptions

 

 

 

 

 

 

 

 

 

 

ADDRESS MODE

s

d

 

SYNTAX

EXAMPLE

OPERATION

 

 

 

 

 

 

 

 

 

 

Register

 

MOV Rs, Rd

MOV R10, R11

 

R10 → R11

 

 

 

 

 

 

 

 

 

Indexed

 

MOV X(Rn), Y(Rm)

MOV 2(R5), 6(R6)

M(2 + R5) → M(6 + R6)

 

 

 

 

 

 

 

 

 

 

Symbolic (PC relative)

 

MOV EDE, TONI

 

 

M(EDE) → M(TONI)

 

 

 

 

 

 

 

 

 

 

Absolute

 

MOV &MEM, &TCDAT

 

 

M(MEM) → M(TCDAT)

 

 

 

 

 

 

 

 

 

Indirect

 

 

MOV @Rn, Y(Rm)

MOV @R10, Tab(R6)

M(R10) → M(Tab + R6)

 

 

 

 

 

 

 

 

 

Indirect autoincrement

 

 

MOV @Rn+, RM

MOV @R10+, R11

M(R10) → R11, R10 + 2 → R10

 

Immediate

 

 

MOV #X, TONI

MOV #45, TONI

 

#45 → M(TONI)

 

 

 

 

 

 

 

 

NOTE: s = source d = destination

Rs/Rd = source register/destination register Rn = register number

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

instruction set (continued)

Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other instructions. These addressing modes provide indirect addressing, ideally suited for computed branches and calls. The full use of this programming capability permits a program structure different from conventional 8- and16-bitcontrollers. For example, numerous routines can easily be designed to deal with pointers and stacks instead of using flag type programs for flow control.

operation modes and interrupts

The MSP430 operating modes support various advanced requirements for ultralow-powerand ultralow energy consumption. This is achieved by the intelligent management of the operations during the different module operation modes and CPU states. The advanced requirements are fully supported during interrupt event handling. An interrupt event awakens the system from each of the various operating modes and returns with theRETI instruction to the mode that was selected before the interrupt event. The different requirements of the CPU and modules, which are driven by system cost and current consumption objectives, necessitate the use of different clock signals:

DAuxiliary clock ACLK (from LFXT1CLK/crystal's frequency), used by the peripheral modules

DMain system clock MCLK, used by the CPU and system

DSubsystem clock SMCLK, used by the peripheral modules

low-powerconsumption capabilities

The various operating modes are controlled by the software through controlling the operation of the internal clock system. This clock system provides many combinations of hardware and software capabilities to run the application with the lowest power consumption and with optimized system costs:

DUse the internal clock (DCO) generator without any external components.

DSelect an external crystal or ceramic resonator for lowest frequency or cost.

DSelect and activate the proper clock signals (LFXT1CLK and/or DCOCLK) and clock pre-dividerfunction.

DApply an external clock source.

Four of the control bits that influence the operation of the clock system and support fast turnon from low power operating modes are located in the status register SR. The four bits that control the CPU and the system clock generator are SCG1, SCG0, OscOff, and CPUOff:

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5

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

status register R2

15

9

8

7

6

5

4

3

2

1

0

Reserved For Future

 

V

SCG1

SCG0

OscOff

CPUOff

GIE

N

Z

C

Enhancements

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rw-0

 

rw-0

rw-0

rw-0

rw-0

rw-0

rw-0

rw-0

rw-0

rw-0

The bits CPUOff, SCG1, SCG0, and OscOff are the most important low-powercontrol bits when the basic function of the system clock generator is established. They are pushed onto the stack whenever an interrupt is accepted and thereby saved so that the previous mode of operation can be retrieved after the interrupt request. During execution of an interrupt handler routine, the bits can be manipulated via indirect access of the data on the stack. That allows the program to resume execution in another power operating mode after the return from interrupt (RETI).

SCG1:

The clock signal SMCLK, used for peripherals, is enabled when bit SCG1 is reset or disabled if

 

the bit is set.

SCG0:

The dc-generatoris active when SCG0 is reset. Thedc-generatorcan be deactivated only if the

 

SCG0 bit is set and the DCOCLK signal is not used for MCLK or SMCLK. The current consumed

 

by the dc-generatordefines the basic frequency of the DCOCLK. It is a dc current.

 

The clock signal DCOCLK is deactivated if it is not used for MCLK or SMCLK or if the SCG0 bit

 

is set. There are two situations when the SCG0 bit cannot switch off the DCOCLK signal:

 

1. DCOCLK frequency is used for MCLK (CPUOff=0 and SELM.1=0).

 

2. DCOCLK frequency is used for SMCLK (SCG1=0 and SELS=0).

 

NOTE:

 

When the current is switched off (SCG0=1) the start of the DCOCLK is delayed slightly. The delay

 

is in the s-range(see device parameters for details).

OscOff:

The LFXT1 crystal oscillator is active when the OscOff bit is reset. The LFXT1 oscillator can only

 

be deactivated if the OscOff bit is set and it is not used for MCLK or SMCLK. The setup time to

 

start a crystal oscillation needs consideration when oscillator off option is used. Mask

 

programmable (ROM) devices can disable this feature so that the oscillator can never be switched

 

off by software.

CPUOff:

The clock signal MCLK, used for the CPU, is active when the CPUOff bit is reset or stopped if it

 

is set.

6

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MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

interrupt vector addresses

The interrupt vectors and the power-upstarting address are located in the memory with an address range of0FFFFh-0FFE0h.The vector contains the16-bitaddress of the appropriate interrupt handler instruction sequence.

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD ADDRESS

PRIORITY

 

 

 

 

 

Power-up,external reset, watchdog

WDTIFG (Note1)

Reset

0FFFEh

15, highest

KEYV (Note 1)

 

 

 

 

 

 

 

 

 

NMI, oscillator fault, flash memory

NMIIFG (Notes 1 and 4)

(non)-maskable,

 

 

OFIFG (Notes 1 and 4)

(non)-maskable,

0FFFCh

14

access violation

ACCVIFG (Notes 1 and 4)

(non)-maskable

 

 

 

 

 

 

 

 

 

 

 

 

 

0FFFAh

13

 

 

 

 

 

 

 

 

0FFF8h

12

 

 

 

 

 

Comparator_A

CAIFG

maskable

0FFF6h

11

 

 

 

 

 

Watchdog timer

WDTIFG

maskable

0FFF4h

10

 

 

 

 

 

Timer_A

CCIFG0 (Note 2)

maskable

0FFF2h

9

 

 

 

 

 

Timer_A

CCIFG1, CCIFG2, TAIFG

maskable

0FFF0h

8

(Notes 1 and 2)

 

 

 

 

 

 

 

 

 

 

 

 

0FFEEh

7

 

 

 

 

 

 

 

 

0FFECh

6

 

 

 

 

 

 

 

 

0FFEAh

5

 

 

 

 

 

 

 

 

0FFE8h

4

 

 

 

 

 

I/O Port P2 (eight flags ± see Note 3)

P2IFG.0 to P2IFG.7

maskable

0FFE6h

3

(Notes 1 and 2)

 

 

 

 

 

 

 

 

 

I/O Port P1 (eight flags)

P1IFG.0 to P1IFG.7

maskable

0FFE4h

2

(Notes 1 and 2)

 

 

 

 

 

 

 

 

 

 

 

 

0FFE2h

1

 

 

 

 

 

 

 

 

0FFE0h

0, lowest

 

 

 

 

 

NOTES: 1. Multiple source flags

2.Interrupt flags are located in the module

3.There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0±5) are implemented on the 11x1 devices.

4.(non)-maskable:the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot. Nonmaskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.

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MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

interrupt enable 1 and 2

Address

0h

WDTIE:

OFIE:

NMIIE:

ACCVIE:

Address

01h

7

6

5

4

3

2

1

0

 

 

ACCVIE

NMIIE

 

 

OFIE

WDTIE

 

 

 

 

 

 

 

 

 

 

rw-0

rw-0

 

 

rw-0

rw-0

Watchdog timer enable signal

Oscillator fault enable signal

Nonmaskable interrupt enable signal

Access violation at flash memory

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

interrupt flag register 1 and 2

Address

7

6

 

5

 

4

 

 

3

 

2

1

0

02h

 

 

 

 

 

 

NMIIFG

 

 

 

 

 

 

OFIFG

WDTIFG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rw-0

 

 

 

 

rw-1

rw-0

WDTIFG:

Set on overflow or security key violation or

 

 

 

 

 

 

 

 

Reset on VCC power-onor reset condition at

RST/NMI-pin

 

 

 

OFIFG:

Flag set on oscillator fault

 

 

 

 

 

 

 

 

 

NMIIFG:

Set via

 

 

 

 

 

 

 

 

 

 

 

 

 

RST/NMI-pin

 

 

 

 

 

 

 

 

 

 

 

Address

7

6

 

5

 

4

 

 

3

 

2

1

0

03h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Legend

rw:

Bit can be read and written.

 

 

 

 

 

 

 

 

 

 

rw-0:

Bit can be read and written. It is reset by PUC

 

 

 

 

 

 

 

 

SFR bit is not present in device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

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MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

memory organization

 

MSP430C1111

 

MSP430C1121

 

MSP430F1101

 

MSP430F1121

 

FFFFh

 

 

FFFFh

 

 

FFFFh

 

 

FFFFh

 

 

 

 

Int. Vector

 

Int. Vector

 

Int. Vector

 

Int. Vector

 

 

FFE0h

 

FFE0h

 

FFE0h

 

FFE0h

 

 

 

 

 

 

 

 

 

 

 

 

FFDFh

2 KB ROM

 

FFDFh

 

 

FFDFh

1 KB Flash

 

FFDFh

 

4 KB

 

Main

 

 

 

FC00h

 

 

 

F800h

 

 

 

4 KB

 

Segment0,1

 

 

 

Flash

 

 

 

 

 

 

 

 

 

Segment0±7

 

Memory

 

 

 

 

ROM

 

 

 

 

F000h

 

 

 

 

F000h

 

10FFh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

128B Flash

 

10FFh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1080h

SegmentA

 

2

× 128B

 

Information

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Flash

 

Memory

 

 

 

 

 

 

 

 

 

1000h

SegmentA,B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0FFFh

 

 

 

 

 

 

 

 

 

 

 

 

1 KB

 

 

 

1 KB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0C00h

Boot ROM

 

0FFFh

Boot ROM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0C00h

 

 

 

 

 

 

 

02FFh

 

 

 

 

 

02FFh

 

 

 

 

027Fh

 

 

256B RAM

 

027Fh

 

 

256B RAM

 

 

 

 

 

 

 

 

 

 

 

128B RAM

 

 

128B RAM

 

 

 

 

 

 

 

 

 

 

 

 

 

0200h

 

0200h

 

 

0200h

 

0200h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

01FFh

16b Per.

 

01FFh

16b Per.

 

01FFh

16b Per.

 

01FFh

16b Per.

 

 

0100h

 

0100h

 

0100h

 

0100h

 

 

 

 

 

 

 

 

 

 

 

 

00FFh

8b Per.

 

00FFh

8b Per.

 

00FFh

8b Per.

 

00FFh

8b Per.

 

 

0010h

 

0010h

 

0010h

 

0010h

 

 

 

 

 

 

 

 

 

 

 

 

000Fh

SFR

 

000Fh

SFR

 

000Fh

SFR

 

000Fh

 

SFR

 

 

0000h

 

 

0000h

 

 

0000h

 

 

0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

boot ROM containing bootstrap loader

The intention of the bootstrap loader is to download data into the flash memory module. Various write, read, and erase operations are needed for a proper download environment. The bootstrap loader is only available on F devices.

functions of the bootstrap loader:

Definition of read:

apply and transmit data of peripheral registers or memory to pin P1.1 (BSLTX)

write:

read data from pin P2.2 (BSLRX) and write them into flash memory

unprotected functions

Mass erase, erase of the main memory (Segment0 to Segment7)

Access to the MSP430 via the bootstrap loader is protected. It must be enabled before any protected function can be performed. The 256 bits in 0FFE0h to 0FFFFh provide the access key.

protected functions

All protected functions can be executed only if the access is enabled.

DWrite/program byte into flash memory; Parameters passed are start address and number of bytes (the segment-writefeature of the flash memory is not supported and not useful with the UART protocol).

DSegment erase of Segment0 to Segment7 in the main memory and segment erase of SegmentA and SegmentB in the information memory.

DRead all data in main memory and information memory.

DRead and write to all byte peripheral modules and RAM.

DModify PC and start program execution immediately.

NOTE:

Unauthorized readout of code and data is prevented by the user's definition of the data in the interrupt memory locations.

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MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

boot ROM containing bootstrap loader (continued)

features of the bootstrap loader are:

DUART communication protocol, fixed to 9600 baud

DPort pin P1.1 for transmit, P2.2 for receive

DTI standard serial protocol definition

DImplemented in flash memory version only

DProgram execution starts with the user vector at 0FFFEh or with the bootstrap loader (start vector is at address 0C00h)

hardware resources used for serial input/output:

DPins P1.1 and P2.2 for serial data transmission

DTest and RST/NMI to start program execution at the reset or bootstrap loader vector

DBasic clock module: Rsel=5, DCO=4, MOD=0, DCOCLK for MCLK and SMCLK, clock divider for MCLK

and SMCLK at default: dividing by 1

DTimer_A: Timer_A operates in continuous mode with MCLK source selected, input divider set to 1,

 

using CCR0, and polling of CCIFG0.

D WDT:

Watchdog timer is halted

DInterrupt: GIE=0, NMIIE=0, OFIFG=0, ACCVIFG=0

DMemory allocation and stack pointer:

If the stack pointer points to RAM addresses above 0220h, 6 bytes of the stack are allocated plus RAM addresses 0200h to 0219h. Otherwise the stack pointer is set to 0220h and allocates RAM from 0200h to 021Fh.

NOTE:

When writing RAM data via bootstrap loader, take care that the stack is outside the range of the data being written.

Program execution begins with the user's reset vector at FFFEh (standard method) if TEST is held low while RST/NMI goes from low to high:

VCC

RST/NMI PIN

TEST PIN

User Program Starts

Reset Condition

10

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