Texas Instruments DUAL SOCKET PC CARD CONTROLLER PCI1520 User Manual

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SCPA033 - October 2002

PCI1520 Implementation Guide

Computer Connectivity Solutions

ABSTRACT

This document is provided to assist platform designers using the PCI1520 dual-socketPC Card controller. Detailed information can be found in the PCI1520 data manual. However, this document provides design suggestions for the various options when designing in the PCI1520.

 

 

 

Contents

 

1

PCI1520 Typical System Implementation .......................................................................................................................

3

2

Power Considerations......................................................................................................................................................

4

 

2.1

Internal Voltage Regulator ........................................................................................................................................

4

 

2.2

Clamping Rails ..........................................................................................................................................................

4

 

2.3

Bypass Capacitors ....................................................................................................................................................

4

3

Power Switch Implementation.........................................................................................................................................

5

4

PCI Bus Interface ..............................................................................................................................................................

6

5

PC Card Interface..............................................................................................................................................................

7

6

Miscellaneous Pin Interface.............................................................................................................................................

8

 

6.1

Multifunction Terminals .............................................................................................................................................

8

 

6.2

SPKROUT.................................................................................................................................................................

8

 

6.3

SUSPEND#...............................................................................................................................................................

8

7

Interrupt Configurations ..................................................................................................................................................

9

 

7.1

Parallel PCI Interrupts Only.......................................................................................................................................

9

 

7.2

Parallel IRQ and Parallel PCI Interrupts....................................................................................................................

9

 

7.3

Serial IRQ and Parallel PCI Interrupts.......................................................................................................................

9

 

7.4

Serial IRQ and Serial PCI Interrupts .........................................................................................................................

9

8

Software Considerations ...............................................................................................................................................

10

 

8.1

EEPROM Configuration ..........................................................................................................................................

10

 

8.2

BIOS Considerations...............................................................................................................................................

11

 

 

8.2.1

PCI Configuration Registers (Standard)....................................................................................................

11

 

 

8.2.2

PCI Configuration Registers (TI Extension) ..............................................................................................

12

 

 

8.2.3

ExCA Compatibility Registers ...................................................................................................................

12

 

 

8.2.4

CardBus Socket Registers........................................................................................................................

12

9

Power Management Considerations .............................................................................................................................

13

 

9.1

D3 Wake Information ..............................................................................................................................................

13

 

 

9.1.1

GRST# Only Registers .............................................................................................................................

14

 

 

9.1.2

PME# Context Registers...........................................................................................................................

15

 

9.2

PME#/RI_OUT# Behavior .......................................................................................................................................

15

 

9.3

CLKRUN# Protocol .................................................................................................................................................

15

 

9.4

SUSPEND#.............................................................................................................................................................

16

10

Pin Compatibility with Other Devices ...........................................................................................................................

16

11

Migration to the PCI1520 from the PCI1420..................................................................................................................

17

 

11.1

Hardware and Pin Assignment Changes ................................................................................................................

17

 

11.2

Configuration Register Changes .............................................................................................................................

18

 

11.3

Other Functional Differences ..................................................................................................................................

19

12

Migration to the PCI1420 from the PCI1225..................................................................................................................

20

 

12.1

Hardware and Pin Assignment Changes ................................................................................................................

20

 

12.2

Configuration Register Changes .............................................................................................................................

21

 

12.3

Other Functional Differences ..................................................................................................................................

21

13

Reference Schematics ...................................................................................................................................................

22

14

References

......................................................................................................................................................................

24

1

SCPA033

 

 

 

 

Figures

Figure 1.

Typical System Implementation

.......................................................................................................................3

Figure 2.

Power Switch Implementation..........................................................................................................................

5

Figure 3.

EEPROM Implementation................................................................................................................................

10

Figure 4.

Reference Schematics – Page 1.....................................................................................................................

22

Figure 5.

Reference Schematics – Page 2.....................................................................................................................

23

Document History

Revised by

Date

Document Name

Revision Comments

 

 

 

 

DGB

8/6/02

PCI1520 Implementation

*Initial Draft

 

 

Guide – 1.00.doc

 

DGB

8/8/02

PCI1520 Implementation

*Added information about switchable pullup/pulldown on

 

 

Guide – 1.10.doc

CSTSCHG to Section 5

 

 

 

*Corrected explanation of single socket implementation in

 

 

 

Section 5

 

 

 

*Added PCLK to list of SUSPEND# gated signals in Section 6.3

 

 

 

*Corrected bit number for INTRTIE in Section 7

 

 

 

*Changed description of Cache Line Size Reg in Section 8.2.1

 

 

 

*Removed duplicate Dev Cntl Reg in Section 8.2.2

 

 

 

*Corrected PC Card Standard rev number in Section 14

DGB

8/9/02

PCI1520 Implementation

*Fixed typo in Rev History

 

 

Guide – 1.11.doc

 

2

PCI1520 Implementation Guide

SCPA033

1 PCI1520 Typical System Implementation

The figure below represents a typical implementation of the PCI1520 PC Card Controller. The device serves as a bridge between a PCI Bus and a PC Card interface. The PCI1520 will operate only with the PCI Bus as a primary bus and the PC Card interface as the secondary bus. The PC Card interface operates with both CardBus (32-bit)and16-bitPC Cards.

Vcc/Vpp

 

 

TPS2226A

 

 

Power

 

 

Switch

 

 

4

 

 

3

 

 

P2C Bus

 

 

Socket A

 

 

PCI1520

 

Bus

CardBus

 

 

PCI

Controller

 

Socket B

PME#

 

2

 

 

I2C Bus

IRQSER

Interrupt

 

 

Controller

Serial EEPROM

(Optional)

CardBus Controller Block

System Side

Figure 1. Typical System Implementation

A power switch is necessary in order to control power to the PC Card sockets. The recommended power switch is the TPS2226A. Other possibilities include the TPS2224A, TPS2216A, and the TPS2206. The TPS2223A is also available but does not provide 12V Vpp.

The EEPROM can be used to set various configuration registers but is not necessary if those registers are settable via software/BIOS for the system.

IRQSER is used to pass both PCI interrupts and ISA style legacy interrupts to the system. Only PCI interrupts are necessary in order for CardBus cards to operate correctly. Some 16-bitPC Cards require ISA style legacy interrupts in order to function properly.

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2 Power Considerations

2.1Internal Voltage Regulator

One of the major differences between the PCI1520 and previous Texas Instruments CardBus controllers is that the PCI1520 uses an internal voltage regulator to power the core logic at 2.5V. This allows for a more than 50% reduction in power consumption over previous controllers. The voltage regulator is enabled using the VR_EN# pin. If VR_EN# is high, the voltage regulator is disabled and VRPORT serves as a 2.5V external input to power the core. If VR_EN# is low, the voltage regulator is enabled and VRPORT serves as a 2.5V output. This 2.5V output cannot be used to power other devices and is only available externally in order to provide a 1µF bypass capacitor. VRPORT must have a 1µF bypass capacitor to ground in order for proper operation if the voltage regulator is enabled.

2.2Clamping Rails

The PCI1520 has 3 clamping rails: VCCP, VCCA, and VCCB. VCCP is the PCI interface I/O clamp rail and can be either 3.3V or 5V depending on the system implementation. The PCI1520 will only signal on the PCI bus at 3.3V but is 5V tolerant. VCCA and VCCB are connected to the PC Card power rails for Socket A and Socket B, respectively. These terminals serve as the clamping inputs for the PC Card interface to the PCI1520.

2.3Bypass Capacitors

Standard design rules for power supply bypass should be followed. A value of 0.1µF is recommended for each of the power pins VCC, VCCP, VCCA, and VCCB.

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3 Power Switch Implementation

The following figure shows the serial interface between the PCI1520 and the TPS2226A power switch:

VCCB

VCCA

PCI1520

Pull-downfor I2C interface (optional)

CLOCK

VPPA

 

VCCA

Socket A

 

 

DATA

TPS2226A

 

 

 

 

VPPB

 

LATCH

VCCB

Socket B

Pulldown if using internal clock

Figure 2. Power Switch Implementation

A power switch is necessary in order to control power to the PC Card sockets. When the PCI1520 receives a socket power request, it sends the appropriate data across the P2C interface (CLOCK, DATA, and LATCH). In turn, the power switch turns on the appropriate levels for VCC and VPP for that socket. A 2.7kΩ pulldown on LATCH is used to indicate to the PCI1520 that an EEPROM is being used to program the PCI1520. CLOCK can be provided either internally or externally depending on bit 27 in System Control register in the PCI configuration space at offset 80h. If an external clock is used, the frequency should be between 32kHz and 100kHz. If the internal clock is used, a 43k pulldown resistor is necessary.

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4 PCI Bus Interface

The PCI1520 has a 33MHz, 32 bit PCI Interface compliant with PCI Local Bus Specification Revision 2.2.

PCLK, AD31:0, C/BE#3:0, PAR, DEVSEL#, FRAME#, STOP#, TRDY#, IRDY#, GNT#, and REQ# are required PCI signals. All except PCLK, GNT#, and REQ# are bussed signals. PCLK is a 33MHz point-to-pointclock. GNT# and REQ# arepoint-to-pointsignals form the PCI bus arbitrator.

PERR#, SERR#, and LOCK# are optional PCI signals. PERR# and SERR# are bussed signals and should be pulled up to VCC if unused. LOCK# is available on a Multifunction Terminal. If LOCK# is not needed for system implementation, it should not be configured as such in the Multifunction Routing register (PCI configuration offset 8Ch).

GRST# (Global reset) and PRST# (PCI reset) are both used to initialize the PCI1520. The assertion of GRST# puts the PCI1520 in its default state. The assertion of PRST# does not initialize GRST# only bits. PRST# also does not initialize PME# context bits if PME# in enabled. More information can be found in Section 9.1 – D3 Wake Information.

IDSEL should be resistively coupled (100Ω ) to one of the address lines between AD31 and AD11. Please refer to Section 3.2.2.3.5 (System Generation of IDSEL) and Section 4.2.6, footnote 31 (Pinout Recommendation) of the PCI Local Bus Specification Revision 2.2 for more information.

PCI Interrupts can be routed through INTA# and INTB# through the Multifunction terminals. More information can be found in Section 7 – Interrupt Configurations.

PCI CLKRUN# can be routed through Multifunction terminal 6. For more information, please refer to Section 9 – Power Management Considerations.

PME# is used to signal Power Management Events. This signal is important for waking the PCI1520 from low power states. PME# is an open-drainsignal.

Pullup resistors are needed on the following PCI terminals: IRDY#, TRDY#, FRAME#, STOP#, DEVSEL#, PERR#, SERR#, LOCK#, PRST#, GRST#, INTA#, INTB#, CLKRUN#, and PME#.

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PCI1520 Implementation Guide

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5 PC Card Interface

There are two different modes on the PC Card interface. The first is 16-bitmode which is analogous to the legacy ISA bus. The second is32-bitCardBus mode which is very similar to a PCI Bus. The terminal functions for these two modes are multiplexed and routed to the PC Card sockets. The following suggestions apply to the PC Card interface:

Pullup resistors for the PC Card interface have been integrated into the PCI1520. These include: A14/CPERR#, A15/CIRDY#, A19/CBLOCK#, A20/CSTOP#, A21/CDEVSEL#, A22/CTRDY#, BVD2(SPKR#)/CAUDIO, CD1#/CCD1#, CD2#/CCD2#, INPACK#/CREQ#, READY/CINT#, RESET/CRST#, VS1#/CVS1, VS2#/CVS2, WAIT#/CSERR#, WP(IOIS16#)/CCLKRUN#.

A switchable pullup/pulldown resistor has been implemented on BVD1(STSCHG#)/CSTSCHG. The pulldown is implemented when a CardBus card is being used or when the socket is empty. A pullup is implemented when a 16-bitPC card is being used.

A damping resistor is necessary on the CCLK terminals between the PCI1520 and the PC Card sockets. The value is system dependent. If line impedance is in the

range of 60-90Ω ,a 47Ω resistor is recommended. For more information, please see the PC Card Standard Revision 7.1, Section 5.3.2.1.4.

CD# line noise filtering is no longer required because the PCI1520 has an integrated digital noise filter.

Three PC Card terminals on each socket are not necessary for CardBus mode but are necessary for 16-bitmode. These terminals are: CRSVD/D14, CRSVD/A18, and CRSVD/D2. These terminals must be connected to the PC Card Socket according to their16-bitdesignations. By default, when in CardBus mode, these terminals are driven low. They can be tristated by setting bit 22 (CBRSVD) in the System Control register at PCI configuration offset 80h.

Texas Instruments provides single socket CardBus controllers such as the PCI1510 for systems requiring only one PC card socket. However, the PCI1520 can be used as a single socket controller simply by leaving the Socket B interface floating.

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6 Miscellaneous Pin Interface

6.1Multifunction Terminals

The multifunction terminals (MFUNC6:0) can be programmed to serve many different roles using the Multifunction Routing register at PCI configuration offset 8Ch. The discrete ISA interrupts (IRQ15:2), INTA#, INTB#, and IRQSER are explained in Section 7 – Interrupt Configurations. CLKRUN#, D3STAT#, and RI_OUT# are discussed in Section 9 – Power Management Considerations. ZVSTAT, ZVSEL1#, and ZVSEL0# are used for ZV control. For more information, please refer to the PCI1520 Data Manual.

LED_SKT, LEDA1, and LEDA2 can be used to indicate socket activity. When a PC Card is being accessed, these outputs will be driven high. LED_SKT will be driven high for access to either socket. LEDA1 and LEDA2 will only be driven high during access to their respective socket.

GPE#, GPIx, and GPOx can be used to signal general purpose events to the system.

CAUDPWM provides a PWM output for the CAUDIO terminals (as opposed to the binary output SPKROUT).

PCI LOCK# is an optional PCI signal as mentioned in Section 4 – PCI Bus Interface.

All unused multifunction terminals require a 43kΩ pullup resistor.

6.2SPKROUT

SPKROUT is the output to the host system that can carry SPKR# or CAUDIO through the PCI1520 from the PC Card interface. If SPKROUT is enabled for both sockets, it is driven as an exclusive-ORof the two inputs. A 43k pulldown resistor is required to prevent oscillation when SPKROUT is disabled and therefore tristated.

6.3SUSPEND#

The assertion of SUSPEND# gates PRST#, GRST#, and PCLK from the PCI1520. More information can be found in Section 9 – Power Management Considerations. A 43kΩ pullup resistor is required on SUSPEND#. SUSPEND# cannot be low during boot.

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PCI1520 Implementation Guide

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7 Interrupt Configurations

The PCI1520 provides system designers with great flexibility in configuring interrupts. The PCI1520 allows four interrupt modes which are selected via bits 2:1 of the Device Control register at PCI offset 92h.

PCI interrupts are available on INTA# and INTB#. These signals are available on MFUNC0 and MFUNC1 respectively. The Multifunction Routing register at PCI configuration offset 8Ch must be programmed correspondingly. If MFUNC1 is not available (i.e. EEPROM implementations which use MFUNC1 as SDA), the INTRTIE bit can be set at bit 29 in the System Control register at PCI offset 80h. This allows both INTA# and INTB# signaling to both be reported on INTA#. PCI interrupts can also be signaled through IRQSER.

ISA style IRQ interrupts are available on IRQ15:2. These signals are available on MFUNC6:0. These interrupts are necessary for some 16-bitPC Cards to function properly. IRQ interrupts can also be signaled through IRQSER.

IRQSER is available on MFUNC3 and requires a 43k pullup resistor to VCC.

7.1Parallel PCI Interrupts Only

The parallel PCI interrupts only mode is selected by programming bits 2:1 to a value of 00b. This allows interrupts to be routed through INTA# and INTB#. This is not a recommended interrupt configuration because many 16-bitPC Cards require legacy ISA interrupts and will not function properly.

7.2Parallel IRQ and Parallel PCI Interrupts

The parallel IRQ and parallel PCI interrupts mode is selected by programming bits 2:1 to a value of 01b. This allows interrupts to be routed through IRQ15:2, INTA#, and INTB#. This is not a recommended interrupt configuration because this requires all the multifunction terminals to be used as interrupts which limits other functions on the PCI1520.

7.3Serial IRQ and Parallel PCI Interrupts

The serial IRQ and parallel PCI interrupts mode is selected by programming bits 2:1 a value of 10b. This allows interrupts to be routed through IRQSER, INTA#, and INTB#. This is the recommended interrupt configuration for a PCI add-incard implementation of the PCI1520. INTA# and INTB# can be routed through the PCI edge connector while IRQSER must be attached to a Serial IRQ input on the motherboard. If no Serial IRQ input is available, this mode still allows CardBus cards to function properly. However, many16-bitcards will not.

7.4Serial IRQ and Serial PCI Interrupts

The serial IRQ and serial PCI interrupts mode is selected by programming bits 2:1 to a value of 11b. This allows all interrupts to be routed through IRQSER. This is the recommended interrupt configuration for all designs other than PCI add-incards. It is the simplest method of routing interrupts and allows the other multifunction terminals to be used for other purposes.

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8 Software Considerations

The PCI1520 is natively supported by Windows XP. The PCI1520 will be recognized natively as a Generic CardBus Controller under Windows 2000, Windows ME, and Windows 98SE. The device will function properly using this driver. However, it is recommended that new drivers provided by Texas Instruments be used for non-XPsystems. These drivers have a few small tweaks and allow the device to be reported in Device Manager properly.

Other operating systems are not supported directly by Texas Instruments. However, many nonMicrosoft operating systems have generic CardBus device drivers which are compatible with the PCI1520. Any driver which was compatible with a previous Texas Instruments CardBus controller (such as the PCI1225 or PCI1420) or the Intel 82365SL should also be compatible with the PCI1520.

8.1EEPROM Configuration

The following diagram represents the implementation of an EEPROM for the PCI1520 for configuration:

Vcc

LATCH

SDA

TPS2226A

EEPROM

SCL PCI1520

Figure 3. EEPROM Implementation

On the rising edge of GRST#, if LATCH is low, the Serial Bus Detect bit (bit 3, PCI offset B3h) is set and the EEPROM contents are loaded into the PCI1520. MFUNC1 and MFUNC4 become SDA and SCL respectively. In order for the PCI1520 to detect the EEPROM and load configuration information, a pulldown resistor must be implemented on LATCH. Pullups are needed on SDA and SCL. The EEPROM slave address should be 1010000b. If the Serial Bus Detect bit is cleared after the EEPROM data is loaded, MFUNC1 and MFUNC4 are returned to their functions as indicated by the Multifunction Routing Register (PCI offset 8Ch).

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PCI1520 Implementation Guide